From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2EBCFC433F5 for ; Mon, 24 Jan 2022 17:59:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244773AbiAXR7p (ORCPT ); Mon, 24 Jan 2022 12:59:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58934 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244714AbiAXR7p (ORCPT ); Mon, 24 Jan 2022 12:59:45 -0500 Received: from mail-ot1-x331.google.com (mail-ot1-x331.google.com [IPv6:2607:f8b0:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E12DAC06173B for ; Mon, 24 Jan 2022 09:59:44 -0800 (PST) Received: by mail-ot1-x331.google.com with SMTP id j38-20020a9d1926000000b0059fa6de6c71so3564079ota.10 for ; Mon, 24 Jan 2022 09:59:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vanguardiasur-com-ar.20210112.gappssmtp.com; s=20210112; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=BWwjW0EgyeuAgOSjmucK+gRx+PtrFHCFEX+4W9R0sEU=; b=YSweSEefUIGjTO7Imvy1aBv4aceTxzYRkl9vNQVQArDmVSgcsBRvXuSCtqg1Ql2fF9 5PGUleSjA7aaCdqSfARUJPculq5XPpCzT3Vxh0XROBNnPvadRxCWDp6Xg1ZNujvsy82o a0QlZiE43WGqZ3GwOZFtfJJhvZIP9JPIGY7Leo7ySep+wcXRHcO9pAUf/pmutY2ukWN1 vuL3PbmWITR77XnUNyYiAdbgcLiIDDteYWmVps5I4zkD2zdOTiZEtPAVQVGdsTWyaLzu ojUNlZvnnQaejg+5fHh1pQLGkDmnvzBU6VfqLG6oTCztj4XP/RLABz0mkEDJ9lcZOw7N VghQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=BWwjW0EgyeuAgOSjmucK+gRx+PtrFHCFEX+4W9R0sEU=; b=RXbntM6jJKjdHVVSuBCmmabxvPSofJKRrcTzjkXbz/m6vmjiuno6XpPfK4Pfpj3pch cZyAiQa9Fov6rsluKz5+ic7TAWgc6lQpbWUEkCz4U4tZFaHl/siPE7dLByxeLUtiBWcC M+d+imkGvLwEbnNoGjOqSFrW/LCocaxjrLbToFWu1GAdKpQaXPXHfFlAiguq3Oia8xl+ a+6Q+tKIu2yAcEL91bmK2SzCwjPbFBwCBIC/zK+ICJ1J8GNY0bI7ca6wcK6rCrVQXqf8 bR/8giUWzaIStlPr7IB2jJBI4neFJzF9TTNy0KOpHoEBhq7FZQC3Be28JBY0+MkeLgT5 GGsw== X-Gm-Message-State: AOAM531csMkD8SJwKPL/7KaE8aoczsLnmQK4ea009H1HApOQemRKT3In KQdOme/XGQWTMSyrUAYYE2rwfA== X-Google-Smtp-Source: ABdhPJySYnuZd0DI70tivFuNgNTa7ff7pGvfWbGlgF9rKiiZAQ114+3pPAVe9TWT1/FEsJ21HcSG0A== X-Received: by 2002:a05:6830:34a3:: with SMTP id c35mr12681501otu.206.1643047184272; Mon, 24 Jan 2022 09:59:44 -0800 (PST) Received: from eze-laptop ([190.194.87.200]) by smtp.gmail.com with ESMTPSA id a128sm2663439oob.17.2022.01.24.09.59.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Jan 2022 09:59:43 -0800 (PST) Date: Mon, 24 Jan 2022 14:59:37 -0300 From: Ezequiel Garcia To: Adam Ford Cc: linux-media@vger.kernel.org, linux-arm-kernel@lists.infradead.org, shawnguo@kernel.org, aford@beaconembedded.com, Philipp Zabel , Mauro Carvalho Chehab , Rob Herring , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Greg Kroah-Hartman , Lucas Stach , linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev Subject: Re: [PATCH V3 06/10] arm64: dts: imx8mq: Enable both G1 and G2 VPU's with vpu-blk-ctrl Message-ID: References: <20220124023125.414794-1-aford173@gmail.com> <20220124023125.414794-7-aford173@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220124023125.414794-7-aford173@gmail.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Sun, Jan 23, 2022 at 08:31:20PM -0600, Adam Ford wrote: > With the Hantro G1 and G2 now setup to run independently, update > the device tree to allow both to operate. This requires the > vpu-blk-ctrl node to be configured. Since vpu-blk-ctrl needs > certain clock enabled to handle the gating of the G1 and G2 > fuses, the clock-parents and clock-rates for the various VPU's > to be moved into the pgc_vpu because they cannot get re-parented > once enabled, and the pgc_vpu is the highest in the chain. > > Signed-off-by: Adam Ford > Reviewed-by: Ezequiel Garcia Thanks, Ezequiel > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > index 2df2510d0118..549b2440f55d 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > @@ -737,7 +737,21 @@ pgc_gpu: power-domain@5 { > pgc_vpu: power-domain@6 { > #power-domain-cells = <0>; > reg = ; > - clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; > + clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>, > + <&clk IMX8MQ_CLK_VPU_G1_ROOT>, > + <&clk IMX8MQ_CLK_VPU_G2_ROOT>; > + assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, > + <&clk IMX8MQ_CLK_VPU_G2>, > + <&clk IMX8MQ_CLK_VPU_BUS>, > + <&clk IMX8MQ_VPU_PLL_BYPASS>; > + assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, > + <&clk IMX8MQ_VPU_PLL_OUT>, > + <&clk IMX8MQ_SYS1_PLL_800M>, > + <&clk IMX8MQ_VPU_PLL>; > + assigned-clock-rates = <600000000>, > + <600000000>, > + <800000000>, > + <0>; > }; > > pgc_disp: power-domain@7 { > @@ -1457,30 +1471,31 @@ usb3_phy1: usb-phy@382f0040 { > status = "disabled"; > }; > > - vpu: video-codec@38300000 { > - compatible = "nxp,imx8mq-vpu"; > - reg = <0x38300000 0x10000>, > - <0x38310000 0x10000>, > - <0x38320000 0x10000>; > - reg-names = "g1", "g2", "ctrl"; > - interrupts = , > - ; > - interrupt-names = "g1", "g2"; > + vpu_g1: video-codec@38300000 { > + compatible = "nxp,imx8mq-vpu-g1"; > + reg = <0x38300000 0x10000>; > + interrupts = ; > + clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>; > + power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>; > + }; > + > + vpu_g2: video-codec@38310000 { > + compatible = "nxp,imx8mq-vpu-g2"; > + reg = <0x38310000 0x10000>; > + interrupts = ; > + clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>; > + power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>; > + }; > + > + vpu_blk_ctrl: blk-ctrl@38320000 { > + compatible = "fsl,imx8mq-vpu-blk-ctrl"; > + reg = <0x38320000 0x100>; > + power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>; > + power-domain-names = "bus", "g1", "g2"; > clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, > - <&clk IMX8MQ_CLK_VPU_G2_ROOT>, > - <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; > - clock-names = "g1", "g2", "bus"; > - assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, > - <&clk IMX8MQ_CLK_VPU_G2>, > - <&clk IMX8MQ_CLK_VPU_BUS>, > - <&clk IMX8MQ_VPU_PLL_BYPASS>; > - assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, > - <&clk IMX8MQ_VPU_PLL_OUT>, > - <&clk IMX8MQ_SYS1_PLL_800M>, > - <&clk IMX8MQ_VPU_PLL>; > - assigned-clock-rates = <600000000>, <600000000>, > - <800000000>, <0>; > - power-domains = <&pgc_vpu>; > + <&clk IMX8MQ_CLK_VPU_G2_ROOT>; > + clock-names = "g1", "g2"; > + #power-domain-cells = <1>; > }; > > pcie0: pcie@33800000 { > -- > 2.32.0 >