[RFC 00/28] Add RZ/G2L Display support

[RFC 00/28] Add RZ/G2L Display support

[Biju Das]

RZ/G2L LCD controller composed of Frame compression Processor(FCPVD),
Video signal processor (VSPD) and Display unit(DU). The output of
LCDC is connected to Display parallel interface and MIPI link video
interface. 

This patch series aims to add basic display support on RZ/G2L SMARC
EVK platform. The output from DSI is connected to ADV7535.

Implemntation details:-

Clock:-

PLL5 generates 2 clock sources, FOUTPOSTDIV and FOUT1PH0
and vclk is sourced through DSI divider which is connected
to a mux with the above clock sources.

Pll5-->Mux->DSI divider--> vclk.

The parameters used for generating PLL5 frequency is based on
a LUT[1] from the bsp release.

DSI mode and DPI mode needs different set of PLL5 parameters
for generating the video clock. Currently we support only
DSI mode. later extend this to support DPI mode.

LCDC:

DU shares same clocks and reset line with VSPD and FCPVD.
it does not have DU group and plane registers like R-Car.
it supports FHD@60 for DSI interface.

VSPD:
 
VSPD does not have version register, so a new compatible
introduced to get version string.

Please share your valuable comments on this patch series.

[1]https://github.com/renesas-rz/rz_linux-cip/tree/rzg2l-cip41/drivers/gpu/drm/rcar-du

Biju Das (28):
  clk: renesas: rzg2l: Add FOUTPOSTDIV clk support
  clk: renesas: rzg2l: Add PLL5_4 clk mux support
  clk: renesas: rzg2l: Add DSI divider clk support
  clk: renesas: r9a07g044: Add M1 clock support
  clk: renesas: r9a07g044: Add {M2, M2_DIV2} Clocks support
  clk: renesas: r9a07g044: Add M3 Clock support
  clk: renesas: r9a07g044: Add M4 Clock support
  clk: renesas: r9a07g044: Add LCDC clock and reset entries
  clk: renesas: r9a07g044: Add DSI clock and reset entries
  drm: rcar-du: of: Increase buff size for compatible variable
  drm: rcar-du: Add num_rpf to struct rcar_du_device_info
  drm: rcar-du: Add max_width and max_height to struct
    rcar_du_device_info
  drm: rcar-du: Add RCAR_DU_FEATURE_PLANE feature bit
  drm: rcar-du: Allow DU plane feature based on DU feature bit
  drm: rcar_du: Add RCAR_DU_FEATURE_GROUP feature bit
  drm: rcar-du: Allow DU group feature based on feature bit
  dt-bindings: display: renesas,du: Document r9a07g044l bindings
  drm: rcar-du: Add RZ/G2L LCDC Support
  media: dt-bindings: media: renesas,vsp1: Document RZ/{G2L,V2L} VSPD
    bindings
  media: vsp1: Add support for the RZ/G2L VSPD
  dt-bindings: display: bridge: Document RZ/G2L MIPI DSI TX bindings
  drm: rcar-du: Add RZ/G2L DSI driver
  arm64: dts: renesas: r9a07g044: Add fcpvd node
  arm64: dts: renesas: r9a07g044: Add vspd node
  arm64: dts: renesas: r9a07g044: Add DU node
  arm64: dts: renesas: r9a07g044: Add dsi node
  arm64: dts: renesas: r9a07g044: Link DSI with DU node
  arm64: dts: renesas: rzg2l-smarc: Enable Display on carrier board

 .../bindings/display/bridge/renesas,dsi.yaml  | 143 ++++
 .../bindings/display/renesas,du.yaml          |  54 ++
 .../bindings/media/renesas,vsp1.yaml          |   4 +-
 arch/arm64/boot/dts/renesas/r9a07g044.dtsi    |  94 +++
 arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi  |  61 ++
 drivers/clk/renesas/r9a07g044-cpg.c           |  57 ++
 drivers/clk/renesas/rzg2l-cpg.c               | 426 +++++++++++
 drivers/clk/renesas/rzg2l-cpg.h               |  31 +
 drivers/gpu/drm/rcar-du/Kconfig               |   7 +
 drivers/gpu/drm/rcar-du/Makefile              |   1 +
 drivers/gpu/drm/rcar-du/rcar_du_crtc.c        | 151 +++-
 drivers/gpu/drm/rcar-du/rcar_du_crtc.h        |   2 +
 drivers/gpu/drm/rcar-du/rcar_du_drv.c         | 144 +++-
 drivers/gpu/drm/rcar-du/rcar_du_drv.h         |   9 +
 drivers/gpu/drm/rcar-du/rcar_du_group.c       |  15 +-
 drivers/gpu/drm/rcar-du/rcar_du_kms.c         |  17 +-
 drivers/gpu/drm/rcar-du/rcar_du_of.c          |   2 +-
 drivers/gpu/drm/rcar-du/rcar_du_regs.h        |  52 ++
 drivers/gpu/drm/rcar-du/rcar_du_vsp.c         |   9 +-
 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c      | 676 ++++++++++++++++++
 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h | 151 ++++
 drivers/media/platform/vsp1/vsp1.h            |   1 +
 drivers/media/platform/vsp1/vsp1_drv.c        |  31 +-
 drivers/media/platform/vsp1/vsp1_lif.c        |   7 +-
 drivers/media/platform/vsp1/vsp1_regs.h       |   1 +
 25 files changed, 2070 insertions(+), 76 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h

-- 
2.17.1

[RFC 17/28] dt-bindings: display: renesas,du: Document r9a07g044l bindings

[Biju Das]

Extend the Renesas DU display bindings to support the r9a07g044l RZ/G2L.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 .../bindings/display/renesas,du.yaml          | 54 +++++++++++++++++++
 1 file changed, 54 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/renesas,du.yaml b/Documentation/devicetree/bindings/display/renesas,du.yaml
index 13efea574584..fc050b1088f3 100644
--- a/Documentation/devicetree/bindings/display/renesas,du.yaml
+++ b/Documentation/devicetree/bindings/display/renesas,du.yaml
@@ -40,6 +40,7 @@ properties:
       - renesas,du-r8a77990 # for R-Car E3 compatible DU
       - renesas,du-r8a77995 # for R-Car D3 compatible DU
       - renesas,du-r8a779a0 # for R-Car V3U compatible DU
+      - renesas,du-r9a07g044l # for RZ/G2L compatible DU
 
   reg:
     maxItems: 1
@@ -824,6 +825,59 @@ allOf:
         - reset-names
         - renesas,vsps
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - renesas,du-r9a07g044l
+    then:
+      properties:
+        clocks:
+          items:
+            - description: LCDC Main clock
+            - description: LCDC Register Access Clock
+            - description: LCDC Video Clock
+
+        clock-names:
+          items:
+            - const: du.0
+            - const: pclk
+            - const: vclk
+
+        interrupts:
+          maxItems: 1
+
+        resets:
+          maxItems: 1
+
+        reset-names:
+          items:
+            - const: du.0
+
+        ports:
+          properties:
+            port@0:
+              description: DPAD 0
+            port@1:
+              description: DSI 0
+            port@2: false
+            port@3: false
+
+          required:
+            - port@0
+            - port@1
+
+        renesas,vsps:
+          minItems: 1
+
+      required:
+        - clock-names
+        - interrupts
+        - resets
+        - reset-names
+        - renesas,vsps
+
 additionalProperties: false
 
 examples:
-- 
2.17.1

Re: [RFC 17/28] dt-bindings: display: renesas,du: Document r9a07g044l bindings

[Rob Herring]

On Wed, Jan 12, 2022 at 05:46:01PM +0000, Biju Das wrote:
> Extend the Renesas DU display bindings to support the r9a07g044l RZ/G2L.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
>  .../bindings/display/renesas,du.yaml          | 54 +++++++++++++++++++
>  1 file changed, 54 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/display/renesas,du.yaml b/Documentation/devicetree/bindings/display/renesas,du.yaml
> index 13efea574584..fc050b1088f3 100644
> --- a/Documentation/devicetree/bindings/display/renesas,du.yaml
> +++ b/Documentation/devicetree/bindings/display/renesas,du.yaml
> @@ -40,6 +40,7 @@ properties:
>        - renesas,du-r8a77990 # for R-Car E3 compatible DU
>        - renesas,du-r8a77995 # for R-Car D3 compatible DU
>        - renesas,du-r8a779a0 # for R-Car V3U compatible DU
> +      - renesas,du-r9a07g044l # for RZ/G2L compatible DU
>  
>    reg:
>      maxItems: 1
> @@ -824,6 +825,59 @@ allOf:
>          - reset-names
>          - renesas,vsps
>  
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - renesas,du-r9a07g044l
> +    then:
> +      properties:
> +        clocks:
> +          items:
> +            - description: LCDC Main clock
> +            - description: LCDC Register Access Clock
> +            - description: LCDC Video Clock
> +
> +        clock-names:
> +          items:
> +            - const: du.0
> +            - const: pclk
> +            - const: vclk
> +
> +        interrupts:
> +          maxItems: 1
> +
> +        resets:
> +          maxItems: 1
> +
> +        reset-names:
> +          items:
> +            - const: du.0
> +
> +        ports:
> +          properties:
> +            port@0:
> +              description: DPAD 0
> +            port@1:
> +              description: DSI 0
> +            port@2: false
> +            port@3: false
> +
> +          required:
> +            - port@0
> +            - port@1
> +
> +        renesas,vsps:
> +          minItems: 1

The minimum number of items is 1 by default if not otherwise specified.

maxItems: 1 ???

> +
> +      required:
> +        - clock-names
> +        - interrupts
> +        - resets
> +        - reset-names
> +        - renesas,vsps
> +
>  additionalProperties: false
>  
>  examples:
> -- 
> 2.17.1
> 
> 

RE: [RFC 17/28] dt-bindings: display: renesas,du: Document r9a07g044l bindings

[Biju Das]

Hi Rob,

Thanks for the feedback.

> Subject: Re: [RFC 17/28] dt-bindings: display: renesas,du: Document
> r9a07g044l bindings
> 
> On Wed, Jan 12, 2022 at 05:46:01PM +0000, Biju Das wrote:
> > Extend the Renesas DU display bindings to support the r9a07g044l RZ/G2L.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> >  .../bindings/display/renesas,du.yaml          | 54 +++++++++++++++++++
> >  1 file changed, 54 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/display/renesas,du.yaml
> b/Documentation/devicetree/bindings/display/renesas,du.yaml
> > index 13efea574584..fc050b1088f3 100644
> > --- a/Documentation/devicetree/bindings/display/renesas,du.yaml
> > +++ b/Documentation/devicetree/bindings/display/renesas,du.yaml
> > @@ -40,6 +40,7 @@ properties:
> >        - renesas,du-r8a77990 # for R-Car E3 compatible DU
> >        - renesas,du-r8a77995 # for R-Car D3 compatible DU
> >        - renesas,du-r8a779a0 # for R-Car V3U compatible DU
> > +      - renesas,du-r9a07g044l # for RZ/G2L compatible DU
> >
> >    reg:
> >      maxItems: 1
> > @@ -824,6 +825,59 @@ allOf:
> >          - reset-names
> >          - renesas,vsps
> >
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            enum:
> > +              - renesas,du-r9a07g044l
> > +    then:
> > +      properties:
> > +        clocks:
> > +          items:
> > +            - description: LCDC Main clock
> > +            - description: LCDC Register Access Clock
> > +            - description: LCDC Video Clock
> > +
> > +        clock-names:
> > +          items:
> > +            - const: du.0
> > +            - const: pclk
> > +            - const: vclk
> > +
> > +        interrupts:
> > +          maxItems: 1
> > +
> > +        resets:
> > +          maxItems: 1
> > +
> > +        reset-names:
> > +          items:
> > +            - const: du.0
> > +
> > +        ports:
> > +          properties:
> > +            port@0:
> > +              description: DPAD 0
> > +            port@1:
> > +              description: DSI 0
> > +            port@2: false
> > +            port@3: false
> > +
> > +          required:
> > +            - port@0
> > +            - port@1
> > +
> > +        renesas,vsps:
> > +          minItems: 1
> 
> The minimum number of items is 1 by default if not otherwise specified.
> 
> maxItems: 1 ???

Agreed, I should use maxItems: 1

Regards,
Biju

> 
> > +
> > +      required:
> > +        - clock-names
> > +        - interrupts
> > +        - resets
> > +        - reset-names
> > +        - renesas,vsps
> > +
> >  additionalProperties: false
> >
> >  examples:
> > --
> > 2.17.1
> >
> >

[RFC 19/28] media: dt-bindings: media: renesas,vsp1: Document RZ/{G2L,V2L} VSPD bindings

[Biju Das]

Document VSPD found in RZ/G2L and RZ/V2L family SoC's.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 Documentation/devicetree/bindings/media/renesas,vsp1.yaml | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/media/renesas,vsp1.yaml b/Documentation/devicetree/bindings/media/renesas,vsp1.yaml
index 990e9c1dbc43..b27ee23d2b29 100644
--- a/Documentation/devicetree/bindings/media/renesas,vsp1.yaml
+++ b/Documentation/devicetree/bindings/media/renesas,vsp1.yaml
@@ -19,6 +19,7 @@ properties:
     enum:
       - renesas,vsp1 # R-Car Gen2 and RZ/G1
       - renesas,vsp2 # R-Car Gen3 and RZ/G2
+      - renesas,vsp2-r9a07g044 # RZ/G2L and RZ/V2L
 
   reg:
     maxItems: 1
@@ -27,7 +28,8 @@ properties:
     maxItems: 1
 
   clocks:
-    maxItems: 1
+    minItems: 1
+    maxItems: 3
 
   power-domains:
     maxItems: 1
-- 
2.17.1

Re: [RFC 19/28] media: dt-bindings: media: renesas,vsp1: Document RZ/{G2L,V2L} VSPD bindings

[Rob Herring]

On Wed, Jan 12, 2022 at 05:46:03PM +0000, Biju Das wrote:
> Document VSPD found in RZ/G2L and RZ/V2L family SoC's.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
>  Documentation/devicetree/bindings/media/renesas,vsp1.yaml | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/media/renesas,vsp1.yaml b/Documentation/devicetree/bindings/media/renesas,vsp1.yaml
> index 990e9c1dbc43..b27ee23d2b29 100644
> --- a/Documentation/devicetree/bindings/media/renesas,vsp1.yaml
> +++ b/Documentation/devicetree/bindings/media/renesas,vsp1.yaml
> @@ -19,6 +19,7 @@ properties:
>      enum:
>        - renesas,vsp1 # R-Car Gen2 and RZ/G1
>        - renesas,vsp2 # R-Car Gen3 and RZ/G2
> +      - renesas,vsp2-r9a07g044 # RZ/G2L and RZ/V2L
>  
>    reg:
>      maxItems: 1
> @@ -27,7 +28,8 @@ properties:
>      maxItems: 1
>  
>    clocks:
> -    maxItems: 1
> +    minItems: 1
> +    maxItems: 3

You have to define what each one is once you have more than 1.

>  
>    power-domains:
>      maxItems: 1
> -- 
> 2.17.1
> 
> 

RE: [RFC 19/28] media: dt-bindings: media: renesas,vsp1: Document RZ/{G2L,V2L} VSPD bindings

[Biju Das]

Hi Rob,

Thanks for the review.

> Subject: Re: [RFC 19/28] media: dt-bindings: media: renesas,vsp1: Document
> RZ/{G2L,V2L} VSPD bindings
> 
> On Wed, Jan 12, 2022 at 05:46:03PM +0000, Biju Das wrote:
> > Document VSPD found in RZ/G2L and RZ/V2L family SoC's.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> >  Documentation/devicetree/bindings/media/renesas,vsp1.yaml | 4 +++-
> >  1 file changed, 3 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/media/renesas,vsp1.yaml
> b/Documentation/devicetree/bindings/media/renesas,vsp1.yaml
> > index 990e9c1dbc43..b27ee23d2b29 100644
> > --- a/Documentation/devicetree/bindings/media/renesas,vsp1.yaml
> > +++ b/Documentation/devicetree/bindings/media/renesas,vsp1.yaml
> > @@ -19,6 +19,7 @@ properties:
> >      enum:
> >        - renesas,vsp1 # R-Car Gen2 and RZ/G1
> >        - renesas,vsp2 # R-Car Gen3 and RZ/G2
> > +      - renesas,vsp2-r9a07g044 # RZ/G2L and RZ/V2L
> >
> >    reg:
> >      maxItems: 1
> > @@ -27,7 +28,8 @@ properties:
> >      maxItems: 1
> >
> >    clocks:
> > -    maxItems: 1
> > +    minItems: 1
> > +    maxItems: 3
> 
> You have to define what each one is once you have more than 1.

Agreed, Will define each clocks.

Regards,
Biju

> 
> >
> >    power-domains:
> >      maxItems: 1
> > --
> > 2.17.1
> >
> >

Re: [RFC 19/28] media: dt-bindings: media: renesas,vsp1: Document RZ/{G2L,V2L} VSPD bindings

[Laurent Pinchart]

Hi Biju,

On Sat, Jan 22, 2022 at 11:23:32AM +0000, Biju Das wrote:
> > Subject: Re: [RFC 19/28] media: dt-bindings: media: renesas,vsp1: Document
> > RZ/{G2L,V2L} VSPD bindings
> > 
> > On Wed, Jan 12, 2022 at 05:46:03PM +0000, Biju Das wrote:
> > > Document VSPD found in RZ/G2L and RZ/V2L family SoC's.
> > >
> > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > ---
> > >  Documentation/devicetree/bindings/media/renesas,vsp1.yaml | 4 +++-
> > >  1 file changed, 3 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/Documentation/devicetree/bindings/media/renesas,vsp1.yaml b/Documentation/devicetree/bindings/media/renesas,vsp1.yaml
> > > index 990e9c1dbc43..b27ee23d2b29 100644
> > > --- a/Documentation/devicetree/bindings/media/renesas,vsp1.yaml
> > > +++ b/Documentation/devicetree/bindings/media/renesas,vsp1.yaml
> > > @@ -19,6 +19,7 @@ properties:
> > >      enum:
> > >        - renesas,vsp1 # R-Car Gen2 and RZ/G1
> > >        - renesas,vsp2 # R-Car Gen3 and RZ/G2
> > > +      - renesas,vsp2-r9a07g044 # RZ/G2L and RZ/V2L

The commit message should explain why a new device-specific compatible
value is needed.

> > >
> > >    reg:
> > >      maxItems: 1
> > > @@ -27,7 +28,8 @@ properties:
> > >      maxItems: 1
> > >
> > >    clocks:
> > > -    maxItems: 1
> > > +    minItems: 1
> > > +    maxItems: 3
> > 
> > You have to define what each one is once you have more than 1.
> 
> Agreed, Will define each clocks.

This should also be conditioned by the compatible string, to have
maxItems set to 1 for renesas,vsp1 and renesas,vsp2, and 3 for
renesas,vsp2-r9a07g044.

> > >    power-domains:
> > >      maxItems: 1

-- 
Regards,

Laurent Pinchart

RE: [RFC 19/28] media: dt-bindings: media: renesas,vsp1: Document RZ/{G2L,V2L} VSPD bindings

[Biju Das]

Hi Laurent,

Thanks for the feedback.

> Subject: Re: [RFC 19/28] media: dt-bindings: media: renesas,vsp1: Document
> RZ/{G2L,V2L} VSPD bindings
> 
> Hi Biju,
> 
> On Sat, Jan 22, 2022 at 11:23:32AM +0000, Biju Das wrote:
> > > Subject: Re: [RFC 19/28] media: dt-bindings: media: renesas,vsp1:
> > > Document RZ/{G2L,V2L} VSPD bindings
> > >
> > > On Wed, Jan 12, 2022 at 05:46:03PM +0000, Biju Das wrote:
> > > > Document VSPD found in RZ/G2L and RZ/V2L family SoC's.
> > > >
> > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > ---
> > > >  Documentation/devicetree/bindings/media/renesas,vsp1.yaml | 4
> > > > +++-
> > > >  1 file changed, 3 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git
> > > > a/Documentation/devicetree/bindings/media/renesas,vsp1.yaml
> > > > b/Documentation/devicetree/bindings/media/renesas,vsp1.yaml
> > > > index 990e9c1dbc43..b27ee23d2b29 100644
> > > > --- a/Documentation/devicetree/bindings/media/renesas,vsp1.yaml
> > > > +++ b/Documentation/devicetree/bindings/media/renesas,vsp1.yaml
> > > > @@ -19,6 +19,7 @@ properties:
> > > >      enum:
> > > >        - renesas,vsp1 # R-Car Gen2 and RZ/G1
> > > >        - renesas,vsp2 # R-Car Gen3 and RZ/G2
> > > > +      - renesas,vsp2-r9a07g044 # RZ/G2L and RZ/V2L
> 
> The commit message should explain why a new device-specific compatible
> value is needed.

OK. Will add this in next version.

Basically It does not have version register compared to other SoC's supported by
this driver. 

> 
> > > >
> > > >    reg:
> > > >      maxItems: 1
> > > > @@ -27,7 +28,8 @@ properties:
> > > >      maxItems: 1
> > > >
> > > >    clocks:
> > > > -    maxItems: 1
> > > > +    minItems: 1
> > > > +    maxItems: 3
> > >
> > > You have to define what each one is once you have more than 1.
> >
> > Agreed, Will define each clocks.
> 
> This should also be conditioned by the compatible string, to have maxItems
> set to 1 for renesas,vsp1 and renesas,vsp2, and 3 for renesas,vsp2-
> r9a07g044.

Agreed.

Regards,
Biju
> 
> > > >    power-domains:
> > > >      maxItems: 1
> 
> --
> Regards,
> 
> Laurent Pinchart

[RFC 21/28] dt-bindings: display: bridge: Document RZ/G2L MIPI DSI TX bindings

[Biju Das]

The RZ/G2L MIPI DSI TX is embedded in the Renesas RZ/G2L family SoC's. It
can operate in DSI mode, with up to four data lanes.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 .../bindings/display/bridge/renesas,dsi.yaml  | 143 ++++++++++++++++++
 1 file changed, 143 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml

diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
new file mode 100644
index 000000000000..8e56a9c53cc5
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
@@ -0,0 +1,143 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/renesas,dsi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas R-Car MIPI DSI Encoder
+
+maintainers:
+  - Biju Das <biju.das.jz@bp.renesas.com>
+
+description: |
+  This binding describes the MIPI DSI encoder embedded in the Renesas
+  RZ/G2L family of SoC's. The encoder can operate in DSI mode with up
+  to four data lanes.
+
+properties:
+  compatible:
+    enum:
+      - renesas,r9a07g044-mipi-dsi    # for RZ/G2L
+
+  reg:
+    items:
+      - description: Link register
+      - description: D-PHY register
+
+  clocks:
+    items:
+      - description: DSI D-PHY PLL multiplied clock
+      - description: DSI D-PHY system clock
+      - description: DSI AXI bus clock
+      - description: DSI Register access clock
+      - description: DSI Video clock
+      - description: DSI D_PHY Escape mode Receive clock
+
+  clock-names:
+    items:
+      - const: pllclk
+      - const: sysclk
+      - const: aclk
+      - const: pclk
+      - const: vclk
+      - const: lpclk
+
+  power-domains:
+    maxItems: 1
+
+  resets:
+    items:
+      - description: MIPI_DSI_CMN_RSTB
+      - description: MIPI_DSI_ARESET_N
+      - description: MIPI_DSI_PRESET_N
+
+  reset-names:
+    items:
+      - const: rst
+      - const: arst
+      - const: prst
+
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: Parallel input port
+
+      port@1:
+        $ref: /schemas/graph.yaml#/$defs/port-base
+        unevaluatedProperties: false
+        description: DSI output port
+
+        properties:
+          endpoint:
+            $ref: /schemas/media/video-interfaces.yaml#
+            unevaluatedProperties: false
+
+            properties:
+              data-lanes:
+                minItems: 1
+                maxItems: 4
+
+            required:
+              - data-lanes
+
+    required:
+      - port@0
+      - port@1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - power-domains
+  - resets
+  - reset-names
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/r9a07g044-cpg.h>
+
+    dsi0: dsi@10860000 {
+        compatible = "renesas,r9a07g044-mipi-dsi";
+        reg = <0x10860000 0x10000>,
+              <0x10850000 0x10000>;
+        power-domains = <&cpg>;
+        clocks = <&cpg CPG_MOD R9A07G044_MIPI_DSI_PLLCLK>,
+                 <&cpg CPG_MOD R9A07G044_MIPI_DSI_SYSCLK>,
+                 <&cpg CPG_MOD R9A07G044_MIPI_DSI_ACLK>,
+                 <&cpg CPG_MOD R9A07G044_MIPI_DSI_PCLK>,
+                 <&cpg CPG_MOD R9A07G044_MIPI_DSI_VCLK>,
+                 <&cpg CPG_MOD R9A07G044_MIPI_DSI_LPCLK>;
+        clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk";
+        resets = <&cpg R9A07G044_MIPI_DSI_CMN_RSTB>,
+                 <&cpg R9A07G044_MIPI_DSI_ARESET_N>,
+                 <&cpg R9A07G044_MIPI_DSI_PRESET_N>;
+        reset-names = "rst", "arst", "prst";
+
+        ports {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            port@0 {
+                reg = <0>;
+                dsi0_in: endpoint {
+                    remote-endpoint = <&du_out_dsi0>;
+                };
+            };
+
+            port@1 {
+                reg = <1>;
+                dsi0_out: endpoint {
+                    data-lanes = <1 2 3 4>;
+                    remote-endpoint = <&adv7535_in>;
+                };
+            };
+        };
+    };
+...
-- 
2.17.1

Re: [RFC 21/28] dt-bindings: display: bridge: Document RZ/G2L MIPI DSI TX bindings

[Rob Herring]

On Wed, Jan 12, 2022 at 05:46:05PM +0000, Biju Das wrote:
> The RZ/G2L MIPI DSI TX is embedded in the Renesas RZ/G2L family SoC's. It
> can operate in DSI mode, with up to four data lanes.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
>  .../bindings/display/bridge/renesas,dsi.yaml  | 143 ++++++++++++++++++
>  1 file changed, 143 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
> 
> diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
> new file mode 100644
> index 000000000000..8e56a9c53cc5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
> @@ -0,0 +1,143 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/bridge/renesas,dsi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas R-Car MIPI DSI Encoder
> +
> +maintainers:
> +  - Biju Das <biju.das.jz@bp.renesas.com>
> +
> +description: |
> +  This binding describes the MIPI DSI encoder embedded in the Renesas
> +  RZ/G2L family of SoC's. The encoder can operate in DSI mode with up
> +  to four data lanes.

Need a ref to dsi-controller.yaml.

> +
> +properties:
> +  compatible:
> +    enum:
> +      - renesas,r9a07g044-mipi-dsi    # for RZ/G2L
> +
> +  reg:
> +    items:
> +      - description: Link register
> +      - description: D-PHY register

D-PHY isn't a separate block?

> +
> +  clocks:
> +    items:
> +      - description: DSI D-PHY PLL multiplied clock
> +      - description: DSI D-PHY system clock
> +      - description: DSI AXI bus clock
> +      - description: DSI Register access clock
> +      - description: DSI Video clock
> +      - description: DSI D_PHY Escape mode Receive clock
> +
> +  clock-names:
> +    items:
> +      - const: pllclk
> +      - const: sysclk
> +      - const: aclk
> +      - const: pclk
> +      - const: vclk
> +      - const: lpclk
> +
> +  power-domains:
> +    maxItems: 1
> +
> +  resets:
> +    items:
> +      - description: MIPI_DSI_CMN_RSTB
> +      - description: MIPI_DSI_ARESET_N
> +      - description: MIPI_DSI_PRESET_N
> +
> +  reset-names:
> +    items:
> +      - const: rst
> +      - const: arst
> +      - const: prst
> +
> +  ports:
> +    $ref: /schemas/graph.yaml#/properties/ports
> +
> +    properties:
> +      port@0:
> +        $ref: /schemas/graph.yaml#/properties/port
> +        description: Parallel input port
> +
> +      port@1:
> +        $ref: /schemas/graph.yaml#/$defs/port-base
> +        unevaluatedProperties: false
> +        description: DSI output port
> +
> +        properties:
> +          endpoint:
> +            $ref: /schemas/media/video-interfaces.yaml#
> +            unevaluatedProperties: false
> +
> +            properties:
> +              data-lanes:
> +                minItems: 1
> +                maxItems: 4
> +
> +            required:
> +              - data-lanes
> +
> +    required:
> +      - port@0
> +      - port@1
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - clock-names
> +  - power-domains
> +  - resets
> +  - reset-names
> +  - ports
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/r9a07g044-cpg.h>
> +
> +    dsi0: dsi@10860000 {
> +        compatible = "renesas,r9a07g044-mipi-dsi";
> +        reg = <0x10860000 0x10000>,
> +              <0x10850000 0x10000>;
> +        power-domains = <&cpg>;
> +        clocks = <&cpg CPG_MOD R9A07G044_MIPI_DSI_PLLCLK>,
> +                 <&cpg CPG_MOD R9A07G044_MIPI_DSI_SYSCLK>,
> +                 <&cpg CPG_MOD R9A07G044_MIPI_DSI_ACLK>,
> +                 <&cpg CPG_MOD R9A07G044_MIPI_DSI_PCLK>,
> +                 <&cpg CPG_MOD R9A07G044_MIPI_DSI_VCLK>,
> +                 <&cpg CPG_MOD R9A07G044_MIPI_DSI_LPCLK>;
> +        clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk";
> +        resets = <&cpg R9A07G044_MIPI_DSI_CMN_RSTB>,
> +                 <&cpg R9A07G044_MIPI_DSI_ARESET_N>,
> +                 <&cpg R9A07G044_MIPI_DSI_PRESET_N>;
> +        reset-names = "rst", "arst", "prst";
> +
> +        ports {
> +            #address-cells = <1>;
> +            #size-cells = <0>;
> +
> +            port@0 {
> +                reg = <0>;
> +                dsi0_in: endpoint {
> +                    remote-endpoint = <&du_out_dsi0>;
> +                };
> +            };
> +
> +            port@1 {
> +                reg = <1>;
> +                dsi0_out: endpoint {
> +                    data-lanes = <1 2 3 4>;
> +                    remote-endpoint = <&adv7535_in>;
> +                };
> +            };
> +        };
> +    };
> +...
> -- 
> 2.17.1
> 
> 

RE: [RFC 21/28] dt-bindings: display: bridge: Document RZ/G2L MIPI DSI TX bindings

[Biju Das]

Hi Rob,

Thanks for the review.

> Subject: Re: [RFC 21/28] dt-bindings: display: bridge: Document RZ/G2L
> MIPI DSI TX bindings
> 
> On Wed, Jan 12, 2022 at 05:46:05PM +0000, Biju Das wrote:
> > The RZ/G2L MIPI DSI TX is embedded in the Renesas RZ/G2L family SoC's.
> > It can operate in DSI mode, with up to four data lanes.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> >  .../bindings/display/bridge/renesas,dsi.yaml  | 143
> > ++++++++++++++++++
> >  1 file changed, 143 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
> > b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
> > new file mode 100644
> > index 000000000000..8e56a9c53cc5
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yam
> > +++ l
> > @@ -0,0 +1,143 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id:
> > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> > +cetree.org%2Fschemas%2Fdisplay%2Fbridge%2Frenesas%2Cdsi.yaml%23&amp;d
> > +ata=04%7C01%7Cbiju.das.jz%40bp.renesas.com%7C0494a54e80ad4334fbd208d9
> > +dd43393b%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C637784103062464
> > +167%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBT
> > +iI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&amp;sdata=krF2TinxFIRvSQWNMrJpAjUpkk
> > +cghJsFzWIOmh2Nwno%3D&amp;reserved=0
> > +$schema:
> > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> > +cetree.org%2Fmeta-schemas%2Fcore.yaml%23&amp;data=04%7C01%7Cbiju.das.
> > +jz%40bp.renesas.com%7C0494a54e80ad4334fbd208d9dd43393b%7C53d82571da19
> > +47e49cb4625a166a4a2a%7C0%7C0%7C637784103062464167%7CUnknown%7CTWFpbGZ
> > +sb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%
> > +3D%7C3000&amp;sdata=XrwV3g0Jw0%2Bsi0J5PygxWTw614a0%2FtQGDF2HeMdBVsA%3
> > +D&amp;reserved=0
> > +
> > +title: Renesas R-Car MIPI DSI Encoder
> > +
> > +maintainers:
> > +  - Biju Das <biju.das.jz@bp.renesas.com>
> > +
> > +description: |
> > +  This binding describes the MIPI DSI encoder embedded in the Renesas
> > +  RZ/G2L family of SoC's. The encoder can operate in DSI mode with up
> > +  to four data lanes.
> 
> Need a ref to dsi-controller.yaml.

Agreed. Will add this.

> 
> > +
> > +properties:
> > +  compatible:
> > +    enum:
> > +      - renesas,r9a07g044-mipi-dsi    # for RZ/G2L
> > +
> > +  reg:
> > +    items:
> > +      - description: Link register
> > +      - description: D-PHY register
> 
> D-PHY isn't a separate block?

MIPI-DSI Tx module composed of MIPI DSI-2 Host Controller (LINK), and MIPI D-PHY Tx (DPHY).

Basically both D-PHY and Link are integrated inside MIPI-DSI Tx module.

Regards,
Biju

> 
> > +
> > +  clocks:
> > +    items:
> > +      - description: DSI D-PHY PLL multiplied clock
> > +      - description: DSI D-PHY system clock
> > +      - description: DSI AXI bus clock
> > +      - description: DSI Register access clock
> > +      - description: DSI Video clock
> > +      - description: DSI D_PHY Escape mode Receive clock
> > +
> > +  clock-names:
> > +    items:
> > +      - const: pllclk
> > +      - const: sysclk
> > +      - const: aclk
> > +      - const: pclk
> > +      - const: vclk
> > +      - const: lpclk
> > +
> > +  power-domains:
> > +    maxItems: 1
> > +
> > +  resets:
> > +    items:
> > +      - description: MIPI_DSI_CMN_RSTB
> > +      - description: MIPI_DSI_ARESET_N
> > +      - description: MIPI_DSI_PRESET_N
> > +
> > +  reset-names:
> > +    items:
> > +      - const: rst
> > +      - const: arst
> > +      - const: prst
> > +
> > +  ports:
> > +    $ref: /schemas/graph.yaml#/properties/ports
> > +
> > +    properties:
> > +      port@0:
> > +        $ref: /schemas/graph.yaml#/properties/port
> > +        description: Parallel input port
> > +
> > +      port@1:
> > +        $ref: /schemas/graph.yaml#/$defs/port-base
> > +        unevaluatedProperties: false
> > +        description: DSI output port
> > +
> > +        properties:
> > +          endpoint:
> > +            $ref: /schemas/media/video-interfaces.yaml#
> > +            unevaluatedProperties: false
> > +
> > +            properties:
> > +              data-lanes:
> > +                minItems: 1
> > +                maxItems: 4
> > +
> > +            required:
> > +              - data-lanes
> > +
> > +    required:
> > +      - port@0
> > +      - port@1
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - clocks
> > +  - clock-names
> > +  - power-domains
> > +  - resets
> > +  - reset-names
> > +  - ports
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/clock/r9a07g044-cpg.h>
> > +
> > +    dsi0: dsi@10860000 {
> > +        compatible = "renesas,r9a07g044-mipi-dsi";
> > +        reg = <0x10860000 0x10000>,
> > +              <0x10850000 0x10000>;
> > +        power-domains = <&cpg>;
> > +        clocks = <&cpg CPG_MOD R9A07G044_MIPI_DSI_PLLCLK>,
> > +                 <&cpg CPG_MOD R9A07G044_MIPI_DSI_SYSCLK>,
> > +                 <&cpg CPG_MOD R9A07G044_MIPI_DSI_ACLK>,
> > +                 <&cpg CPG_MOD R9A07G044_MIPI_DSI_PCLK>,
> > +                 <&cpg CPG_MOD R9A07G044_MIPI_DSI_VCLK>,
> > +                 <&cpg CPG_MOD R9A07G044_MIPI_DSI_LPCLK>;
> > +        clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk",
> "lpclk";
> > +        resets = <&cpg R9A07G044_MIPI_DSI_CMN_RSTB>,
> > +                 <&cpg R9A07G044_MIPI_DSI_ARESET_N>,
> > +                 <&cpg R9A07G044_MIPI_DSI_PRESET_N>;
> > +        reset-names = "rst", "arst", "prst";
> > +
> > +        ports {
> > +            #address-cells = <1>;
> > +            #size-cells = <0>;
> > +
> > +            port@0 {
> > +                reg = <0>;
> > +                dsi0_in: endpoint {
> > +                    remote-endpoint = <&du_out_dsi0>;
> > +                };
> > +            };
> > +
> > +            port@1 {
> > +                reg = <1>;
> > +                dsi0_out: endpoint {
> > +                    data-lanes = <1 2 3 4>;
> > +                    remote-endpoint = <&adv7535_in>;
> > +                };
> > +            };
> > +        };
> > +    };
> > +...
> > --
> > 2.17.1
> >
> >

[RFC 23/28] arm64: dts: renesas: r9a07g044: Add fcpvd node

[Biju Das]

Add fcpvd node to SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 027b873ea5d3..080b4c8af427 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -611,6 +611,16 @@
 			status = "disabled";
 		};
 
+		fcpvd0: fcp@10880000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0x10880000 0 0x10000>;
+			clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>,
+				 <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>,
+				 <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>;
+			power-domains = <&cpg>;
+			resets = <&cpg R9A07G044_LCDC_RESET_N>;
+		};
+
 		cpg: clock-controller@11010000 {
 			compatible = "renesas,r9a07g044-cpg";
 			reg = <0 0x11010000 0 0x10000>;
-- 
2.17.1

Re: [RFC 23/28] arm64: dts: renesas: r9a07g044: Add fcpvd node

[Sergey Shtylyov]

On 1/12/22 8:46 PM, Biju Das wrote:

> Add fcpvd node to SoC DTSI.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
>  arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> index 027b873ea5d3..080b4c8af427 100644
> --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> @@ -611,6 +611,16 @@
>  			status = "disabled";
>  		};
>  
> +		fcpvd0: fcp@10880000 {
> +			compatible = "renesas,fcpv";
> +			reg = <0 0x10880000 0 0x10000>;
> +			clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>,
> +				 <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>,
> +				 <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>;

   clock-names?

[...]

MBR, Sergey

[RFC 24/28] arm64: dts: renesas: r9a07g044: Add vspd node

[Biju Das]

Add vspd node to SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 080b4c8af427..9dc407c37976 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -611,6 +611,18 @@
 			status = "disabled";
 		};
 
+		vspd0: vsp@10870000 {
+			compatible = "renesas,vsp2-r9a07g044";
+			reg = <0 0x10870000 0 0x10000>;
+			interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>,
+				 <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>,
+				 <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>;
+			power-domains = <&cpg>;
+			resets = <&cpg R9A07G044_LCDC_RESET_N>;
+			renesas,fcp = <&fcpvd0>;
+		};
+
 		fcpvd0: fcp@10880000 {
 			compatible = "renesas,fcpv";
 			reg = <0 0x10880000 0 0x10000>;
-- 
2.17.1

Re: [RFC 24/28] arm64: dts: renesas: r9a07g044: Add vspd node

[Sergey Shtylyov]

Hello!

On 1/12/22 8:46 PM, Biju Das wrote:

> Add vspd node to SoC DTSI.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
>  arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> index 080b4c8af427..9dc407c37976 100644
> --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> @@ -611,6 +611,18 @@
>  			status = "disabled";
>  		};
>  
> +		vspd0: vsp@10870000 {
> +			compatible = "renesas,vsp2-r9a07g044";
> +			reg = <0 0x10870000 0 0x10000>;
> +			interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>,
> +				 <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>,
> +				 <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>;

   What about clock-names?

[...]

MBR, Sergey

[RFC 25/28] arm64: dts: renesas: r9a07g044: Add DU node

[Biju Das]

Add DU node to SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 33 ++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 9dc407c37976..86bbc536aee4 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -633,6 +633,39 @@
 			resets = <&cpg R9A07G044_LCDC_RESET_N>;
 		};
 
+		du: display@0x10890000 {
+			compatible = "renesas,du-r9a07g044l";
+			reg = <0 0x10890000 0 0x10000>;
+			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>,
+				 <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>,
+				 <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>;
+			clock-names = "du.0", "pclk", "vclk";
+			power-domains = <&cpg>;
+			resets = <&cpg R9A07G044_LCDC_RESET_N>;
+			reset-names = "du.0";
+			renesas,vsps = <&vspd0 0>;
+
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					du_out_rgb: endpoint {
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					du_out_dsi0: endpoint {
+					};
+				};
+			};
+		};
+
 		cpg: clock-controller@11010000 {
 			compatible = "renesas,r9a07g044-cpg";
 			reg = <0 0x11010000 0 0x10000>;
-- 
2.17.1

[RFC 26/28] arm64: dts: renesas: r9a07g044: Add dsi node

[Biju Das]

Add dsi node to SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 37 ++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 86bbc536aee4..f5e63ffab9cc 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -666,6 +666,43 @@
 			};
 		};
 
+		dsi0: dsi@10860000 {
+			compatible = "renesas,r9a07g044-mipi-dsi";
+			reg =	<0 0x10860000 0 0x10000>, /* LINK */
+				<0 0x10850000 0 0x10000>; /* DPHY */
+
+			clocks = <&cpg CPG_MOD R9A07G044_MIPI_DSI_PLLCLK>,
+				 <&cpg CPG_MOD R9A07G044_MIPI_DSI_SYSCLK>,
+				 <&cpg CPG_MOD R9A07G044_MIPI_DSI_ACLK>,
+				 <&cpg CPG_MOD R9A07G044_MIPI_DSI_PCLK>,
+				 <&cpg CPG_MOD R9A07G044_MIPI_DSI_VCLK>,
+				 <&cpg CPG_MOD R9A07G044_MIPI_DSI_LPCLK>;
+			clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk";
+			power-domains = <&cpg>;
+			resets = <&cpg R9A07G044_MIPI_DSI_CMN_RSTB>,
+				 <&cpg R9A07G044_MIPI_DSI_ARESET_N>,
+				 <&cpg R9A07G044_MIPI_DSI_PRESET_N>;
+			reset-names = "rst", "arst", "prst";
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					dsi0_in: endpoint {
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					dsi0_out: endpoint {
+					};
+				};
+			};
+		};
+
 		cpg: clock-controller@11010000 {
 			compatible = "renesas,r9a07g044-cpg";
 			reg = <0 0x11010000 0 0x10000>;
-- 
2.17.1

[RFC 27/28] arm64: dts: renesas: r9a07g044: Link DSI with DU node

[Biju Das]

Link DSI with DU node to SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index f5e63ffab9cc..fa29664b6a7c 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -661,6 +661,7 @@
 				port@1 {
 					reg = <1>;
 					du_out_dsi0: endpoint {
+						remote-endpoint = <&dsi0_in>;
 					};
 				};
 			};
@@ -692,6 +693,7 @@
 				port@0 {
 					reg = <0>;
 					dsi0_in: endpoint {
+					remote-endpoint = <&du_out_dsi0>;
 					};
 				};
 
-- 
2.17.1

[RFC 28/28] arm64: dts: renesas: rzg2l-smarc: Enable Display on carrier board

[Biju Das]

Enable display interface on RZ/G2L SMARC EVK.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 61 ++++++++++++++++++++
 1 file changed, 61 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
index 6f2a8bdfa225..3851f5b4c855 100644
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
@@ -37,6 +37,17 @@
 		stdout-path = "serial0:115200n8";
 	};
 
+	hdmi-out {
+		compatible = "hdmi-connector";
+		type = "d";
+
+		port {
+			hdmi_con_out: endpoint {
+				remote-endpoint = <&adv7535_out>;
+			};
+		};
+	};
+
 	audio_mclock: audio_mclock {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
@@ -107,6 +118,23 @@
 	};
 };
 
+&dsi0 {
+	status = "okay";
+
+	ports {
+		port@1 {
+			dsi0_out: endpoint {
+				data-lanes = <1 2 3 4>;
+				remote-endpoint = <&adv7535_in>;
+			};
+		};
+	};
+};
+
+&du {
+	status = "okay";
+};
+
 &ehci0 {
 	dr_mode = "otg";
 	status = "okay";
@@ -133,6 +161,39 @@
 	pinctrl-names = "default";
 
 	status = "okay";
+
+	adv7535: hdmi@3d {
+		compatible = "adi,adv7535";
+		reg = <0x3d>;
+
+		avdd-supply = <&reg_1p8v>;
+		dvdd-supply = <&reg_1p8v>;
+		pvdd-supply = <&reg_1p8v>;
+		a2vdd-supply = <&reg_1p8v>;
+		v3p3-supply = <&reg_3p3v>;
+		v1p2-supply = <&reg_1p8v>;
+
+		adi,dsi-lanes = <4>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				adv7535_in: endpoint {
+					remote-endpoint = <&dsi0_out>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				adv7535_out: endpoint {
+					remote-endpoint = <&hdmi_con_out>;
+				};
+			};
+		};
+	};
 };
 
 &i2c3 {
-- 
2.17.1

Re: [RFC 28/28] arm64: dts: renesas: rzg2l-smarc: Enable Display on carrier board

[Geert Uytterhoeven]

Hi Biju,

On Wed, Jan 12, 2022 at 6:47 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Enable display interface on RZ/G2L SMARC EVK.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Thanks for your patch!

> --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
> +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
> @@ -107,6 +118,23 @@
>         };
>  };
>
> +&dsi0 {
> +       status = "okay";
> +
> +       ports {
> +               port@1 {
> +                       dsi0_out: endpoint {
> +                               data-lanes = <1 2 3 4>;
> +                               remote-endpoint = <&adv7535_in>;
> +                       };
> +               };
> +       };
> +};
> +
> +&du {
> +       status = "okay";
> +};
> +
>  &ehci0 {
>         dr_mode = "otg";
>         status = "okay";

JFYI, as rzg2l-smarc.dtsi is now shared by the RZ/G2L(C) and RZ/V2L
DTS files, placeholders for "dsi0" and "du" need to be added to
r9a07g054.dtsi.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds