From: Bjorn Andersson <bjorn.andersson@linaro.org>
To: David Heidelberg <david@ixit.cz>
Cc: Andy Gross <agross@kernel.org>, Rob Herring <robh+dt@kernel.org>,
~okias/devicetree@lists.sr.ht, Andy Gross <andy.gross@linaro.org>,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] dt-bindings: firmware: convert Qualcomm SCM binding to the yaml
Date: Mon, 31 Jan 2022 15:26:22 -0600 [thread overview]
Message-ID: <YfhT/ltPDhQZV0Bo@builder.lan> (raw)
In-Reply-To: <20211218194038.26913-1-david@ixit.cz>
On Sat 18 Dec 13:40 CST 2021, David Heidelberg wrote:
> Convert Qualcomm SCM firmware binding to the yaml format.
>
> Signed-off-by: David Heidelberg <david@ixit.cz>
> ---
> This patch comes with followup question -> since not all definitions
> follow `"qcom,scm-*chipset*", "qcom,scm"`, should I change them or adjust this
> binding to cover all cases?
>
I don't remember why some platforms has the generic "fallback" and
others doesn't. I don't have any objections to defining the binding as
you've done.
> .../devicetree/bindings/firmware/qcom,scm.txt | 54 ---------
> .../bindings/firmware/qcom,scm.yaml | 112 ++++++++++++++++++
> 2 files changed, 112 insertions(+), 54 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/firmware/qcom,scm.txt
> create mode 100644 Documentation/devicetree/bindings/firmware/qcom,scm.yaml
>
> diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.txt b/Documentation/devicetree/bindings/firmware/qcom,scm.txt
> deleted file mode 100644
> index d7e3cda8924e..000000000000
> --- a/Documentation/devicetree/bindings/firmware/qcom,scm.txt
> +++ /dev/null
> @@ -1,54 +0,0 @@
> -QCOM Secure Channel Manager (SCM)
> -
> -Qualcomm processors include an interface to communicate to the secure firmware.
> -This interface allows for clients to request different types of actions. These
> -can include CPU power up/down, HDCP requests, loading of firmware, and other
> -assorted actions.
> -
> -Required properties:
> -- compatible: must contain one of the following:
> - * "qcom,scm-apq8064"
> - * "qcom,scm-apq8084"
> - * "qcom,scm-ipq4019"
> - * "qcom,scm-ipq806x"
> - * "qcom,scm-ipq8074"
> - * "qcom,scm-mdm9607"
> - * "qcom,scm-msm8226"
> - * "qcom,scm-msm8660"
> - * "qcom,scm-msm8916"
> - * "qcom,scm-msm8953"
> - * "qcom,scm-msm8960"
> - * "qcom,scm-msm8974"
> - * "qcom,scm-msm8994"
> - * "qcom,scm-msm8996"
> - * "qcom,scm-msm8998"
> - * "qcom,scm-sc7180"
> - * "qcom,scm-sc7280"
> - * "qcom,scm-sdm845"
> - * "qcom,scm-sdx55"
> - * "qcom,scm-sm8150"
> - * "qcom,scm-sm8250"
> - * "qcom,scm-sm8350"
> - and:
> - * "qcom,scm"
> -- clocks: Specifies clocks needed by the SCM interface, if any:
> - * core clock required for "qcom,scm-apq8064", "qcom,scm-msm8660" and
> - "qcom,scm-msm8960"
> - * core, iface and bus clocks required for "qcom,scm-apq8084",
> - "qcom,scm-msm8916", "qcom,scm-msm8953" and "qcom,scm-msm8974"
> -- clock-names: Must contain "core" for the core clock, "iface" for the interface
> - clock and "bus" for the bus clock per the requirements of the compatible.
> -- qcom,dload-mode: phandle to the TCSR hardware block and offset of the
> - download mode control register (optional)
> -
> -Example for MSM8916:
> -
> - firmware {
> - scm {
> - compatible = "qcom,msm8916", "qcom,scm";
> - clocks = <&gcc GCC_CRYPTO_CLK> ,
> - <&gcc GCC_CRYPTO_AXI_CLK>,
> - <&gcc GCC_CRYPTO_AHB_CLK>;
> - clock-names = "core", "bus", "iface";
> - };
> - };
> diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
> new file mode 100644
> index 000000000000..3a7261734fad
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
> @@ -0,0 +1,112 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/firmware/qcom,scm.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: QCOM Secure Channel Manager (SCM)
> +
> +description: |
I don't think there's value in the formatting, so perhaps omitting the
pipe?
> + Qualcomm processors include an interface to communicate to the secure firmware.
> + This interface allows for clients to request different types of actions. These
> + can include CPU power up/down, HDCP requests, loading of firmware, and other
> + assorted actions.
> +
> +maintainers:
> + - Andy Gross <andy.gross@linaro.org>
It's been a while since Andy left that address behind. Please put mine
instead.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - qcom,scm-apq8064
> + - qcom,scm-apq8084
> + - qcom,scm-ipq4019
> + - qcom,scm-ipq806x
> + - qcom,scm-ipq8074
> + - qcom,scm-mdm9607
> + - qcom,scm-msm8226
> + - qcom,scm-msm8660
> + - qcom,scm-msm8916
> + - qcom,scm-msm8953
> + - qcom,scm-msm8960
> + - qcom,scm-msm8974
> + - qcom,scm-msm8994
> + - qcom,scm-msm8996
> + - qcom,scm-msm8998
> + - qcom,scm-sc7180
> + - qcom,scm-sc7280
> + - qcom,scm-sdm845
> + - qcom,scm-sdx55
> + - qcom,scm-sm8150
> + - qcom,scm-sm8250
> + - qcom,scm-sm8350
> + - const: qcom,scm
> +
> + clocks:
> + minItems: 1
> + maxItems: 3
> +
> + clock-names: true
> +
> + qcom,dload-mode:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description: >
> + TCSR hardware block and offset of the download mode control register
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,scm-apq8064
> + - qcom,scm-msm8660
> + - qcom,scm-msm8960
> + then:
> + properties:
> + clock-names:
> + items:
> + - const: core
> +
> + required:
> + - clocks
> + - clock-names
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,scm-apq8084
> + - qcom,scm-msm8916
> + - qcom,scm-msm8953
> + - qcom,scm-msm8974
> + then:
> + properties:
> + clock-names:
> + items:
> + - const: core
> + - const: iface
> + - const: bus
> +
> + required:
> + - clocks
> + - clock-names
> +
> +required:
> + - compatible
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + firmware {
> + scm {
> + compatible = "qcom,msm8916", "qcom,scm";
> + clocks = <&gcc 104>,
> + <&gcc 77>,
> + <&gcc 86>;
Can we include dt-bindings/clock/qcom,gcc-msm8916.h and continue to use
the constants in the example?
Regards,
Bjorn
> + clock-names = "core", "bus", "iface";
> + };
> + };
> --
> 2.34.1
>
next prev parent reply other threads:[~2022-01-31 21:26 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-18 19:40 [PATCH] dt-bindings: firmware: convert Qualcomm SCM binding to the yaml David Heidelberg
2021-12-19 21:57 ` Rob Herring
2022-01-31 21:26 ` Bjorn Andersson [this message]
2022-04-10 8:50 ` Krzysztof Kozlowski
2022-04-10 8:58 ` Krzysztof Kozlowski
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=YfhT/ltPDhQZV0Bo@builder.lan \
--to=bjorn.andersson@linaro.org \
--cc=agross@kernel.org \
--cc=andy.gross@linaro.org \
--cc=david@ixit.cz \
--cc=devicetree@vger.kernel.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=robh+dt@kernel.org \
--cc=~okias/devicetree@lists.sr.ht \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).