From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A787C433EF for ; Mon, 31 Jan 2022 21:47:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1381177AbiAaVrb (ORCPT ); Mon, 31 Jan 2022 16:47:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53656 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1381154AbiAaVr3 (ORCPT ); Mon, 31 Jan 2022 16:47:29 -0500 Received: from mail-oi1-x22a.google.com (mail-oi1-x22a.google.com [IPv6:2607:f8b0:4864:20::22a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2FFE0C061714 for ; Mon, 31 Jan 2022 13:47:29 -0800 (PST) Received: by mail-oi1-x22a.google.com with SMTP id t199so12826835oie.10 for ; Mon, 31 Jan 2022 13:47:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=i4ZNON8jjEqhdUhXt2lm8yAa37L58m4tSj1GfdxY8fY=; b=hYQh9jnUfIqiLu881VQDp+oCeamuUvhXtTawHjvucMbffYwqzgdl9YuT5XOQW30ztY oQemAMYrcEB6QlQemd2uNZWPymLOuISHd5Lj3aV+VTxyEaDNU6pJEUZW/2sgx4xxuEQz Z8cruvZT0/q9rqGmqFStKqU27q0xtM1VSVs28k7xbB2ZekSekWGney+HB2oDdLcB5sXJ isR2t5jZDAdOak3nzs06IIoeKkRHhEQrqOfQwy2hslIV/ugLAxLY2j6zWD6tzyK/hX2G iEoB0Kh58qWypHKItSpBtL/a5GcUlwLmoHZjToXJL+G1Vxke1DSo6E7+zOkGsANE3Qy1 y0aA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=i4ZNON8jjEqhdUhXt2lm8yAa37L58m4tSj1GfdxY8fY=; b=f9phceB9nIrfYFHjxptDQMK2OwX50dAfg2d19zPSwLSgbX/6mMuHGp+CQcMK71cXjd 1dDrfrgSayBb1zY1gMm3vfF9bqHyBWXAAF/KDtxXT7ZCw9gM++gQ8/8UyKxF5NLU4Kd2 RANgLuwYdvKkxBnNIOV+xE9pE4muVqYADSGN7nMKpn0AM1xGT+iG2gR3X8dw1ZYXWmXR p12fZqCYbMr6bTqfraGIqB5Bb7d97XRq4M20zg7a/KEgpXjGxx2fxcOipsR2YreUATf+ jiPvUc78BHIOWJEZhI4BWN//TUFbcCGre72a8U2ldP5LgtPpL1O/7HtCzdRo86GIvGYx 91Hw== X-Gm-Message-State: AOAM5320iYHaiyyVyn7/q1roA9qhFVyVsXsdqEKhMlTy+wDdddGIkSKG jMXQQBL1enjwdSAE3XeeQjvCI1+7OvTUnQ== X-Google-Smtp-Source: ABdhPJxv2BQ99VhEEybtEde4R7t1XK2VPNj5P94cmRD1qpbZ70xYPRLnqD31ijFF4oVSs3O/Arlt6A== X-Received: by 2002:a05:6808:f0a:: with SMTP id m10mr10743268oiw.127.1643665648575; Mon, 31 Jan 2022 13:47:28 -0800 (PST) Received: from builder.lan ([2600:1700:a0:3dc8:3697:f6ff:fe85:aac9]) by smtp.gmail.com with ESMTPSA id w42sm12923738ooi.40.2022.01.31.13.47.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Jan 2022 13:47:27 -0800 (PST) Date: Mon, 31 Jan 2022 15:47:26 -0600 From: Bjorn Andersson To: David Heidelberg Cc: Andy Gross , Rob Herring , ~okias/devicetree@lists.sr.ht, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] ARM: dts: qcom: fix timer node clock-frequency Message-ID: References: <20211224234631.109315-1-david@ixit.cz> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20211224234631.109315-1-david@ixit.cz> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Fri 24 Dec 17:46 CST 2021, David Heidelberg wrote: > Clock frequency is read by driver a single uint32, > so the second value was never processed. > I'm not familiar with the reasoning behind this, but the binding says that we should have > 1 clock-frequency specified. Regards, Bjorn > Signed-off-by: David Heidelberg > --- > arch/arm/boot/dts/qcom-apq8064.dtsi | 3 +-- > arch/arm/boot/dts/qcom-ipq8064.dtsi | 3 +-- > arch/arm/boot/dts/qcom-mdm9615.dtsi | 3 +-- > arch/arm/boot/dts/qcom-msm8660.dtsi | 3 +-- > arch/arm/boot/dts/qcom-msm8960.dtsi | 3 +-- > 5 files changed, 5 insertions(+), 10 deletions(-) > > diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi > index 2d539d77bad4..3d5d9ffb66af 100644 > --- a/arch/arm/boot/dts/qcom-apq8064.dtsi > +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi > @@ -380,8 +380,7 @@ timer@200a000 { > <1 2 0x301>, > <1 3 0x301>; > reg = <0x0200a000 0x100>; > - clock-frequency = <27000000>, > - <32768>; > + clock-frequency = <27000000>; > cpu-offset = <0x80000>; > }; > > diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi > index 996f4458d9fc..d663521bdd02 100644 > --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi > +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi > @@ -458,8 +458,7 @@ IRQ_TYPE_EDGE_RISING)>, > IRQ_TYPE_EDGE_RISING)>; > reg = <0x0200a000 0x100>; > - clock-frequency = <25000000>, > - <32768>; > + clock-frequency = <25000000>; > clocks = <&sleep_clk>; > clock-names = "sleep"; > cpu-offset = <0x80000>; > diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi > index c32415f0e66d..8b58f80093e8 100644 > --- a/arch/arm/boot/dts/qcom-mdm9615.dtsi > +++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi > @@ -120,8 +120,7 @@ timer@200a000 { > , > ; > reg = <0x0200a000 0x100>; > - clock-frequency = <27000000>, > - <32768>; > + clock-frequency = <27000000>; > cpu-offset = <0x80000>; > }; > > diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi > index 1e8aab357f9c..b16060b65593 100644 > --- a/arch/arm/boot/dts/qcom-msm8660.dtsi > +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi > @@ -105,8 +105,7 @@ timer@2000000 { > <1 1 0x301>, > <1 2 0x301>; > reg = <0x02000000 0x100>; > - clock-frequency = <27000000>, > - <32768>; > + clock-frequency = <27000000>; > cpu-offset = <0x40000>; > }; > > diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi > index 2a0ec97a264f..ca093b89c9ea 100644 > --- a/arch/arm/boot/dts/qcom-msm8960.dtsi > +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi > @@ -99,8 +99,7 @@ timer@200a000 { > <1 2 0x301>, > <1 3 0x301>; > reg = <0x0200a000 0x100>; > - clock-frequency = <27000000>, > - <32768>; > + clock-frequency = <27000000>; > cpu-offset = <0x80000>; > }; > > -- > 2.34.1 >