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[66.90.148.213]) by smtp.gmail.com with ESMTPSA id s64sm13024778oos.0.2022.02.01.09.22.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Feb 2022 09:22:34 -0800 (PST) Received: (nullmailer pid 235445 invoked by uid 1000); Tue, 01 Feb 2022 17:22:33 -0000 Date: Tue, 1 Feb 2022 11:22:33 -0600 From: Rob Herring To: Sascha Hauer Cc: dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, kernel@pengutronix.de, Andy Yan , Benjamin Gaignard , Michael Riesch , Sandy Huang , Heiko =?iso-8859-1?Q?St=FCbner?= , Peter Geis Subject: Re: [PATCH 17/27] dt-bindings: display: rockchip: Add binding for VOP2 Message-ID: References: <20220126145549.617165-1-s.hauer@pengutronix.de> <20220126145549.617165-18-s.hauer@pengutronix.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220126145549.617165-18-s.hauer@pengutronix.de> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Wed, Jan 26, 2022 at 03:55:39PM +0100, Sascha Hauer wrote: > The VOP2 is found on newer Rockchip SoCs like the rk3568 or the rk3566. > The binding differs slightly from the existing VOP binding, so add a new > binding file for it. > > Changes since v3: > - drop redundant _vop suffix from clock names > > Signed-off-by: Sascha Hauer > --- > .../display/rockchip/rockchip-vop2.yaml | 146 ++++++++++++++++++ > 1 file changed, 146 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml > > diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml > new file mode 100644 > index 000000000000..572cfb307c20 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml > @@ -0,0 +1,146 @@ > +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/rockchip/rockchip-vop2.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Rockchip SoC display controller (VOP2) > + > +description: > + VOP2 (Video Output Processor v2) is the display controller for the Rockchip > + series of SoCs which transfers the image data from a video memory > + buffer to an external LCD interface. > + > +maintainers: > + - Sandy Huang > + - Heiko Stuebner > + > +properties: > + compatible: > + enum: > + - rockchip,rk3566-vop > + - rockchip,rk3568-vop > + > + reg: > + minItems: 1 > + items: > + - description: > + Must contain one entry corresponding to the base address and length > + of the register space. > + - description: > + Can optionally contain a second entry corresponding to > + the CRTC gamma LUT address. > + > + interrupts: > + maxItems: 1 > + description: > + The VOP interrupt is shared by several interrupt sources, such as > + frame start (VSYNC), line flag and other status interrupts. > + > + clocks: > + items: > + - description: Clock for ddr buffer transfer. > + - description: Clock for the ahb bus to R/W the phy regs. > + - description: Pixel clock for video port 0. > + - description: Pixel clock for video port 1. > + - description: Pixel clock for video port 2. > + > + clock-names: > + items: > + - const: aclk > + - const: hclk > + - const: dclk_vp0 > + - const: dclk_vp1 > + - const: dclk_vp2 > + > + rockchip,grf: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: > + Phandle to GRF regs used for misc control > + > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + > + properties: > + port@0: > + $ref: /schemas/graph.yaml#/properties/port > + description: > + Output endpoint of VP0 > + > + port@1: > + $ref: /schemas/graph.yaml#/properties/port > + description: > + Output endpoint of VP1 > + > + port@2: > + $ref: /schemas/graph.yaml#/properties/port > + description: > + Output endpoint of VP2 > + > + assigned-clocks: true > + > + assigned-clock-rates: true > + > + assigned-clock-parents: true You can drop these. They are implicitly allowed with 'clocks'. > + > + iommus: > + maxItems: 1 > + > + power-domains: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + - clock-names > + - ports > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + bus { > + #address-cells = <2>; > + #size-cells = <2>; > + vop: vop@fe040000 { > + compatible = "rockchip,rk3568-vop"; > + reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>; > + interrupts = ; > + clocks = <&cru ACLK_VOP>, > + <&cru HCLK_VOP>, > + <&cru DCLK_VOP0>, > + <&cru DCLK_VOP1>, > + <&cru DCLK_VOP2>; > + clock-names = "aclk_vop", > + "hclk_vop", > + "dclk_vp0", > + "dclk_vp1", > + "dclk_vp2"; > + power-domains = <&power RK3568_PD_VO>; > + iommus = <&vop_mmu>; > + vop_out: ports { > + #address-cells = <1>; > + #size-cells = <0>; > + vp0: port@0 { > + reg = <0>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + vp1: port@1 { > + reg = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + vp2: port@2 { > + reg = <2>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + }; > + }; > + }; > -- > 2.30.2 > >