From: Jisheng Zhang <jszhang@kernel.org>
To: Heiko Stuebner <heiko@sntech.de>
Cc: palmer@dabbelt.com, paul.walmsley@sifive.com,
aou@eecs.berkeley.edu, linux-riscv@lists.infradead.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
robh+dt@kernel.org, wefu@redhat.com, liush@allwinnertech.com,
guoren@kernel.org, atishp@atishpatra.org, anup@brainfault.org,
drew@beagleboard.org, hch@lst.de, arnd@arndb.de, wens@csie.org,
maxime@cerno.tech, gfavor@ventanamicro.com,
andrea.mondelli@huawei.com, behrensj@mit.edu,
xinhaoqu@huawei.com, huffman@cadence.com, mick@ics.forth.gr,
allen.baum@esperantotech.com, jscheid@ventanamicro.com,
rtrauben@gmail.com, samuel@sholland.org, cmuellner@linux.com,
philipp.tomsich@vrull.eu
Subject: Re: [PATCH v6 00/14] riscv: support for Svpbmt and D1 memory types
Date: Thu, 10 Feb 2022 01:49:19 +0800 [thread overview]
Message-ID: <YgP+n5OMhQPSbICV@xhacker> (raw)
In-Reply-To: <20220209123800.269774-1-heiko@sntech.de>
On Wed, Feb 09, 2022 at 01:37:46PM +0100, Heiko Stuebner wrote:
> Svpbmt is an extension defining "Supervisor-mode: page-based memory types"
> for things like non-cacheable pages or I/O memory pages.
>
>
> So this is my 2nd try at implementing Svpbmt (and the diverging D1 memory
> types) using the alternatives framework.
>
> This includes a number of changes to the alternatives mechanism itself.
> The biggest one being the move to a more central location, as I expect
> in the future, nearly every chip needing some sort of patching, be it
> either for erratas or for optional features (svpbmt or others).
>
> The dt-binding for svpbmt itself is of course not finished and is still
> using the binding introduced in previous versions, as where to put
> a svpbmt-property in the devicetree is still under dicussion.
> Atish seems to be working on a framework for extensions [0],
>
> The series also introduces support for the memory types of the D1
> which are implemented differently to svpbmt. But when patching anyway
> it's pretty clean to add the D1 variant via ALTERNATIVE_2 to the same
> location.
>
> The only slightly bigger difference is that the "normal" type is not 0
> as with svpbmt, so kernel patches for this PMA type need to be applied
> even before the MMU is brought up, so the series introduces a separate
> stage for that.
>
>
> In theory this series is 3 parts:
> - sbi cache-flush / null-ptr
> - alternatives improvements
> - svpbmt+d1
>
> So expecially patches from the first 2 areas could be applied when
> deemed ready, I just thought to keep it together to show-case where
> the end-goal is and not requiring jumping between different series.
>
>
> The sbi cache-flush patch is based on Atish's sparse-hartid patch [1],
> as it touches a similar area in mm/cacheflush.c
>
>
> I picked the recipient list from the previous version, hopefully
> I didn't forget anybody.
>
> changes in v6:
> - rebase onto 5.17-rc1
> - handle sbi null-ptr differently
> - improve commit messages
> - use riscv,mmu as property name
>
> changes in v5:
> - move to use alternatives for runtime-patching
Hi,
another choice is using static key mechanism. Pros: no need to coding
in asm, all in c.
To support new arch features, I see other arch sometimes use static
key, sometimes use alternative mechanism, so one question here would
be which mechanism is better? Any guide?
Thanks in advance
next prev parent reply other threads:[~2022-02-09 17:57 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-09 12:37 [PATCH v6 00/14] riscv: support for Svpbmt and D1 memory types Heiko Stuebner
2022-02-09 12:37 ` [PATCH v6 01/14] riscv: prevent null-pointer dereference with sbi_remote_fence_i Heiko Stuebner
2022-02-11 1:59 ` Atish Patra
2022-02-09 12:37 ` [PATCH v6 02/14] riscv: integrate alternatives better into the main architecture Heiko Stuebner
2022-02-09 12:37 ` [PATCH v6 03/14] riscv: allow different stages with alternatives Heiko Stuebner
2022-02-09 12:37 ` [PATCH v6 04/14] riscv: implement module alternatives Heiko Stuebner
2022-02-09 12:37 ` [PATCH v6 05/14] riscv: implement ALTERNATIVE_2 macro Heiko Stuebner
2022-02-09 12:37 ` [PATCH v6 06/14] riscv: extend concatenated alternatives-lines to the same length Heiko Stuebner
2022-02-09 12:37 ` [PATCH v6 07/14] riscv: prevent compressed instructions in alternatives Heiko Stuebner
2022-03-08 0:47 ` Palmer Dabbelt
2022-02-09 12:37 ` [PATCH v6 08/14] riscv: move boot alternatives to a slightly earlier position Heiko Stuebner
2022-02-10 22:42 ` Atish Patra
2022-02-11 1:11 ` Heiko Stübner
2022-02-11 1:57 ` Atish Patra
2022-02-11 9:34 ` Heiko Stübner
2022-03-08 0:47 ` Palmer Dabbelt
2022-03-23 16:51 ` Heiko Stübner
2022-02-09 12:37 ` [PATCH v6 09/14] riscv: Fix accessing pfn bits in PTEs for non-32bit variants Heiko Stuebner
2022-02-09 12:37 ` [PATCH v6 10/14] riscv: add cpufeature handling via alternatives Heiko Stuebner
2022-02-09 12:37 ` [PATCH v6 11/14] dt-bindings: riscv: add MMU Standard Extensions support for Svpbmt Heiko Stuebner
2022-02-09 18:47 ` Rob Herring
2022-02-09 12:37 ` [PATCH v6 12/14] riscv: add RISC-V Svpbmt extension support Heiko Stuebner
2022-02-09 12:37 ` [PATCH v6 13/14] riscv: remove FIXMAP_PAGE_IO and fall back to its default value Heiko Stuebner
2022-02-09 12:38 ` [PATCH v6 14/14] riscv: add memory-type errata for T-Head Heiko Stuebner
2022-02-11 0:12 ` Atish Patra
2022-02-11 9:25 ` Heiko Stübner
2022-02-12 0:27 ` Atish Patra
2022-02-11 2:01 ` Atish Patra
2022-02-14 3:42 ` Samuel Holland
2022-02-09 17:49 ` Jisheng Zhang [this message]
2022-02-09 23:44 ` [PATCH v6 00/14] riscv: support for Svpbmt and D1 memory types Heiko Stübner
2022-02-10 16:01 ` Jisheng Zhang
2022-02-11 0:25 ` Atish Patra
2022-02-11 1:48 ` Atish Patra
2022-02-11 2:04 ` Heiko Stübner
2022-02-12 0:25 ` Atish Patra
2022-02-14 20:02 ` Heiko Stübner
2022-02-14 20:25 ` Atish Patra
2022-02-14 20:37 ` Heiko Stübner
2022-03-09 7:56 ` Guo Ren
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