[RFC PATCH 0/3] Add SCMI clk support for NXP S32G2

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* [RFC PATCH 0/3] Add SCMI clk support for NXP S32G2
@ 2022-02-07 13:24 Chester Lin
  2022-02-07 13:24 ` [RFC PATCH 1/3] dt-bindings: clock: Add s32g2 clock binding Chester Lin
                   ` (2 more replies)
  0 siblings, 3 replies; 5+ messages in thread
From: Chester Lin @ 2022-02-07 13:24 UTC (permalink / raw)
  To: Rob Herring, Andreas Färber, Matthias Brugger, s32
  Cc: linux-arm-kernel, devicetree, linux-kernel, Radu Nicolae Pirea,
	Ivan T . Ivanov, Lee, Chun-Yi, Chester Lin

Hi folks,

Here I'd like to propose an upstream patchset to support clock management of
NXP S32G2 platforms based on ARM-SCMI's clock protocol (0x14). The goal is to
have simple clock settings for enabling limited functions, such as MMC and
GMAC0. Most of codes are mainly refined/refactored/redistributed from NXP's
downstream codebase on CodeAurora[1] under the original license announcements
and all SCMI clock IDs still match the implementations of NXP's downstream
TF-A[2].

For those downstream authors who implement the main/original ideas, please
forgive me that I only leave my name as "Signed-off-by" because I'm not sure
if you might agree with these changes. Please feel free to let me know if you
don't mind to be added into the list.

I roughly verified this patchset with NXP downstream firmware blobs [major ver:
bsp30 & bsp31], such as TF-A[2] and U-Boot[3] (BL33) on CodeAurora.

Thanks for your patience.

Chester

[1]: https://source.codeaurora.org/external/autobsps32/linux/
[2]: https://source.codeaurora.org/external/autobsps32/arm-trusted-firmware/
[3]: https://source.codeaurora.org/external/autobsps32/u-boot/

Chester Lin (3):
  dt-bindings: clock: Add s32g2 clock binding
  arm64: dts: s32g2: add SCMI support
  arm64: dts: s32g2: add USDHC support

 arch/arm64/boot/dts/freescale/s32g2.dtsi      | 40 +++++++++++++++++++
 .../arm64/boot/dts/freescale/s32g274a-evb.dts |  4 ++
 .../boot/dts/freescale/s32g274a-rdb2.dts      |  4 ++
 include/dt-bindings/clock/s32g2-clock.h       | 28 +++++++++++++
 4 files changed, 76 insertions(+)
 create mode 100644 include/dt-bindings/clock/s32g2-clock.h

-- 
2.33.1

^ permalink raw reply	[flat|nested] 5+ messages in thread

* [RFC PATCH 1/3] dt-bindings: clock: Add s32g2 clock binding
  2022-02-07 13:24 [RFC PATCH 0/3] Add SCMI clk support for NXP S32G2 Chester Lin
@ 2022-02-07 13:24 ` Chester Lin
  2022-02-11 16:25   ` Rob Herring
  2022-02-07 13:24 ` [RFC PATCH 2/3] arm64: dts: s32g2: add SCMI support Chester Lin
  2022-02-07 13:24 ` [RFC PATCH 3/3] arm64: dts: s32g2: add USDHC support Chester Lin
  2 siblings, 1 reply; 5+ messages in thread
From: Chester Lin @ 2022-02-07 13:24 UTC (permalink / raw)
  To: Rob Herring, Andreas Färber, Matthias Brugger, s32,
	Ghennadi Procopciuc
  Cc: linux-arm-kernel, devicetree, linux-kernel, Radu Nicolae Pirea,
	Ivan T . Ivanov, Lee, Chun-Yi, Chester Lin

Add clock binding for S32G based on SCMI Clock Management Protocol (0x14)

Signed-off-by: Chester Lin <clin@suse.com>
---
 include/dt-bindings/clock/s32g2-clock.h | 28 +++++++++++++++++++++++++
 1 file changed, 28 insertions(+)
 create mode 100644 include/dt-bindings/clock/s32g2-clock.h

diff --git a/include/dt-bindings/clock/s32g2-clock.h b/include/dt-bindings/clock/s32g2-clock.h
new file mode 100644
index 000000000000..6d8606293865
--- /dev/null
+++ b/include/dt-bindings/clock/s32g2-clock.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright 2020-2022 NXP
+ */
+#ifndef __DT_BINDINGS_SCMI_CLOCK_S32G2_H
+#define __DT_BINDINGS_SCMI_CLOCK_S32G2_H
+
+#define S32G2_SCMI_CLK_BASE_ID		0U
+#define S32G2_SCMI_CLK(N)		((N) + S32G2_SCMI_CLK_BASE_ID)
+
+/* GMAC0 - SGMII */
+#define S32G2_SCMI_CLK_GMAC0_RX_SGMII	S32G2_SCMI_CLK(16)
+#define S32G2_SCMI_CLK_GMAC0_TX_SGMII	S32G2_SCMI_CLK(17)
+/* GMAC0 - RGMII */
+#define S32G2_SCMI_CLK_GMAC0_RX_RGMII	S32G2_SCMI_CLK(19)
+#define S32G2_SCMI_CLK_GMAC0_TX_RGMII	S32G2_SCMI_CLK(20)
+/* GMAC0 - RMII */
+#define S32G2_SCMI_CLK_GMAC0_RX_RMII	S32G2_SCMI_CLK(22)
+#define S32G2_SCMI_CLK_GMAC0_TX_RMII	S32G2_SCMI_CLK(23)
+/* GMAC0 - MII */
+#define S32G2_SCMI_CLK_GMAC0_RX_MII	S32G2_SCMI_CLK(25)
+#define S32G2_SCMI_CLK_GMAC0_TX_MII	S32G2_SCMI_CLK(26)
+#define S32G2_SCMI_CLK_GMAC0_AXI	S32G2_SCMI_CLK(28)
+/* uSDHC */
+#define S32G2_SCMI_CLK_USDHC_AHB	S32G2_SCMI_CLK(35)
+#define S32G2_SCMI_CLK_USDHC_MODULE	S32G2_SCMI_CLK(36)
+#define S32G2_SCMI_CLK_USDHC_CORE	S32G2_SCMI_CLK(37)
+#endif
-- 
2.33.1


^ permalink raw reply related	[flat|nested] 5+ messages in thread

* Re: [RFC PATCH 1/3] dt-bindings: clock: Add s32g2 clock binding
  2022-02-07 13:24 ` [RFC PATCH 1/3] dt-bindings: clock: Add s32g2 clock binding Chester Lin
@ 2022-02-11 16:25   ` Rob Herring
  0 siblings, 0 replies; 5+ messages in thread
From: Rob Herring @ 2022-02-11 16:25 UTC (permalink / raw)
  To: Chester Lin
  Cc: Andreas Färber, Matthias Brugger, s32, Ghennadi Procopciuc,
	linux-arm-kernel, devicetree, linux-kernel, Radu Nicolae Pirea,
	Ivan T . Ivanov, Lee, Chun-Yi

On Mon, Feb 07, 2022 at 09:24:42PM +0800, Chester Lin wrote:
> Add clock binding for S32G based on SCMI Clock Management Protocol (0x14)
> 
> Signed-off-by: Chester Lin <clin@suse.com>
> ---
>  include/dt-bindings/clock/s32g2-clock.h | 28 +++++++++++++++++++++++++
>  1 file changed, 28 insertions(+)
>  create mode 100644 include/dt-bindings/clock/s32g2-clock.h
> 
> diff --git a/include/dt-bindings/clock/s32g2-clock.h b/include/dt-bindings/clock/s32g2-clock.h
> new file mode 100644
> index 000000000000..6d8606293865
> --- /dev/null
> +++ b/include/dt-bindings/clock/s32g2-clock.h
> @@ -0,0 +1,28 @@
> +/* SPDX-License-Identifier: BSD-3-Clause */

Dual license please.

> +/*
> + * Copyright 2020-2022 NXP
> + */
> +#ifndef __DT_BINDINGS_SCMI_CLOCK_S32G2_H
> +#define __DT_BINDINGS_SCMI_CLOCK_S32G2_H
> +
> +#define S32G2_SCMI_CLK_BASE_ID		0U
> +#define S32G2_SCMI_CLK(N)		((N) + S32G2_SCMI_CLK_BASE_ID)
> +
> +/* GMAC0 - SGMII */
> +#define S32G2_SCMI_CLK_GMAC0_RX_SGMII	S32G2_SCMI_CLK(16)
> +#define S32G2_SCMI_CLK_GMAC0_TX_SGMII	S32G2_SCMI_CLK(17)
> +/* GMAC0 - RGMII */
> +#define S32G2_SCMI_CLK_GMAC0_RX_RGMII	S32G2_SCMI_CLK(19)
> +#define S32G2_SCMI_CLK_GMAC0_TX_RGMII	S32G2_SCMI_CLK(20)
> +/* GMAC0 - RMII */
> +#define S32G2_SCMI_CLK_GMAC0_RX_RMII	S32G2_SCMI_CLK(22)
> +#define S32G2_SCMI_CLK_GMAC0_TX_RMII	S32G2_SCMI_CLK(23)
> +/* GMAC0 - MII */
> +#define S32G2_SCMI_CLK_GMAC0_RX_MII	S32G2_SCMI_CLK(25)
> +#define S32G2_SCMI_CLK_GMAC0_TX_MII	S32G2_SCMI_CLK(26)
> +#define S32G2_SCMI_CLK_GMAC0_AXI	S32G2_SCMI_CLK(28)
> +/* uSDHC */
> +#define S32G2_SCMI_CLK_USDHC_AHB	S32G2_SCMI_CLK(35)
> +#define S32G2_SCMI_CLK_USDHC_MODULE	S32G2_SCMI_CLK(36)
> +#define S32G2_SCMI_CLK_USDHC_CORE	S32G2_SCMI_CLK(37)
> +#endif
> -- 
> 2.33.1
> 
> 

^ permalink raw reply	[flat|nested] 5+ messages in thread

* [RFC PATCH 2/3] arm64: dts: s32g2: add SCMI support
  2022-02-07 13:24 [RFC PATCH 0/3] Add SCMI clk support for NXP S32G2 Chester Lin
  2022-02-07 13:24 ` [RFC PATCH 1/3] dt-bindings: clock: Add s32g2 clock binding Chester Lin
@ 2022-02-07 13:24 ` Chester Lin
  2022-02-07 13:24 ` [RFC PATCH 3/3] arm64: dts: s32g2: add USDHC support Chester Lin
  2 siblings, 0 replies; 5+ messages in thread
From: Chester Lin @ 2022-02-07 13:24 UTC (permalink / raw)
  To: Andreas Färber, Matthias Brugger, Ciprian Marian Costea,
	Ghennadi Procopciuc, s32
  Cc: Rob Herring, linux-arm-kernel, devicetree, linux-kernel,
	Radu Nicolae Pirea, Ivan T . Ivanov, Lee, Chun-Yi, Chester Lin

Add a scmi node to support SCMI protocol 0x14 on NXP S32G2 platforms.

Signed-off-by: Chester Lin <clin@suse.com>
---
 arch/arm64/boot/dts/freescale/s32g2.dtsi | 26 ++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index 59ea8a25aa4c..34652d36a9f1 100644
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -72,11 +72,37 @@ timer {
 			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 	};
 
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		scmi_shmem: memory@d0000000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0 0xd0000000 0 0x400000>; /* 4 MiB */
+			no-map;
+		};
+	};
+
 	firmware {
 		psci {
 			compatible = "arm,psci-1.0";
 			method = "smc";
 		};
+
+		scmi {
+			compatible = "arm,scmi-smc";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			shmem = <&scmi_shmem>;
+			arm,smc-id = <0xc20000fe>;
+
+			scmi_clks: protocol@14 {
+				reg = <0x14>;
+				#clock-cells = <1>;
+			};
+		};
+
 	};
 
 	soc {
-- 
2.33.1


^ permalink raw reply related	[flat|nested] 5+ messages in thread

* [RFC PATCH 3/3] arm64: dts: s32g2: add USDHC support
  2022-02-07 13:24 [RFC PATCH 0/3] Add SCMI clk support for NXP S32G2 Chester Lin
  2022-02-07 13:24 ` [RFC PATCH 1/3] dt-bindings: clock: Add s32g2 clock binding Chester Lin
  2022-02-07 13:24 ` [RFC PATCH 2/3] arm64: dts: s32g2: add SCMI support Chester Lin
@ 2022-02-07 13:24 ` Chester Lin
  2 siblings, 0 replies; 5+ messages in thread
From: Chester Lin @ 2022-02-07 13:24 UTC (permalink / raw)
  To: Andreas Färber, Matthias Brugger, Radu Nicolae Pirea,
	Costin Carabas, s32
  Cc: Rob Herring, linux-arm-kernel, devicetree, linux-kernel,
	Ivan T . Ivanov, Lee, Chun-Yi, Chester Lin

Add a mmc node to support USDHC on NXP S32G2 platforms.

Signed-off-by: Chester Lin <clin@suse.com>
---
 arch/arm64/boot/dts/freescale/s32g2.dtsi        | 14 ++++++++++++++
 arch/arm64/boot/dts/freescale/s32g274a-evb.dts  |  4 ++++
 arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts |  4 ++++
 3 files changed, 22 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index 34652d36a9f1..fd073654d6f6 100644
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -7,6 +7,7 @@
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/s32g2-clock.h>
 
 / {
 	compatible = "nxp,s32g2";
@@ -135,6 +136,19 @@ uart2: serial@402bc000 {
 			status = "disabled";
 		};
 
+		usdhc0: mmc@402f0000 {
+			compatible = "nxp,s32g2-usdhc";
+			reg = <0x402f0000 0x1000>;
+			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+			bus-width = <8>;
+			clocks = <&scmi_clks S32G2_SCMI_CLK_USDHC_MODULE>,
+				 <&scmi_clks S32G2_SCMI_CLK_USDHC_AHB>,
+				 <&scmi_clks S32G2_SCMI_CLK_USDHC_CORE>;
+			clock-names = "ipg", "ahb", "per";
+			no-1-8-v;
+			status = "disabled";
+		};
+
 		gic: interrupt-controller@50800000 {
 			compatible = "arm,gic-v3";
 			reg = <0x50800000 0x10000>,
diff --git a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
index 9118d8d2ee01..89428f1883d9 100644
--- a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
+++ b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
@@ -32,3 +32,7 @@ memory@80000000 {
 &uart0 {
 	status = "okay";
 };
+
+&usdhc0 {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
index e05ee854cdf5..30eae51121de 100644
--- a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
+++ b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
@@ -38,3 +38,7 @@ &uart0 {
 &uart1 {
 	status = "okay";
 };
+
+&usdhc0 {
+	status = "okay";
+};
-- 
2.33.1


^ permalink raw reply related	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2022-02-11 16:25 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2022-02-07 13:24 [RFC PATCH 0/3] Add SCMI clk support for NXP S32G2 Chester Lin
2022-02-07 13:24 ` [RFC PATCH 1/3] dt-bindings: clock: Add s32g2 clock binding Chester Lin
2022-02-11 16:25   ` Rob Herring
2022-02-07 13:24 ` [RFC PATCH 2/3] arm64: dts: s32g2: add SCMI support Chester Lin
2022-02-07 13:24 ` [RFC PATCH 3/3] arm64: dts: s32g2: add USDHC support Chester Lin

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