From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 871B1C4332F for ; Thu, 24 Feb 2022 03:43:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229669AbiBXDnk (ORCPT ); Wed, 23 Feb 2022 22:43:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49674 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229665AbiBXDnj (ORCPT ); Wed, 23 Feb 2022 22:43:39 -0500 Received: from mail-oi1-x22e.google.com (mail-oi1-x22e.google.com [IPv6:2607:f8b0:4864:20::22e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1D00A25A310 for ; Wed, 23 Feb 2022 19:43:09 -0800 (PST) Received: by mail-oi1-x22e.google.com with SMTP id i5so1243544oih.1 for ; Wed, 23 Feb 2022 19:43:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=LQV2Ce0Cqm3fFzgko900zEq9hMhH+dYL1BenORkgZSE=; b=cLYZ+u45ycfZDh38NHEb/21XbNgNJUZG3on3NOdklDWSJ7PYJ+mdinq7E890TK38OQ tSkQUxI/xCNA/cht+qvJAbH0cwiq7f7N3rXRxmjZbGS3GHMwWBev1n1I02+bJN7zW90S Y73yWgHuDPVmf6+iArbNDFcrS1A79n7D5oRnf5N/FJ8ywVtznp2wcRdZ9W46JWcAonIF XUk4j4BQcWTfayGWJUrM4yxLtlsHnLKU4H2WPmutQHSw3DikI6o0QvBR6/NDcFEpdp1e 5No0/Xf00aVJsSrQu/9VrUfDI9OA88oOlURFV1yzpkIuS88PD7aWFFrnlzjG3lTTSP1/ +wIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=LQV2Ce0Cqm3fFzgko900zEq9hMhH+dYL1BenORkgZSE=; b=YgpYAdEpXiGoQKkeSDihqxeZy2ovUoBOQbYEjIjRiQEVUtnHFiTCCUJ+34lQtFkL22 OJaTdUlmT3gmgv1B3iwIfKkMWfFzkKNVSJjc+QVNRmCSaKhqFSCEsRbsyc9ncpsxUiP6 chKqRrPPhWJWmyYTQWlKoyrBbR07IEcYdd0/b9xMziCyFDSuO/FMHBBGtvpX8/Dk//l7 1QjZOOqlnPM02Onli+0osdFC+IHYTsREYuzIsyDFKI0tTzf6yb9UTulKT2vdc80KKOD8 Y3SURuLMjFaRFLuP3MRp+3b/0FIxXwaD56aK+QAl46Kum8pTfEUCbWIKfuUsLLnUvSGH XiJw== X-Gm-Message-State: AOAM531FYCAUGtnmgiWGfyho6GdOJwhPFGXh96SlckCsla714Lx5qkV7 pPsnlPV0gzgBm8iDzpY74Jvgqg== X-Google-Smtp-Source: ABdhPJzgnESy4fUgWr9qkHrfCBVEALdcwUFNttweBpXgPrGC9ko/0af5qYzPPWqA86hfZugFItirDw== X-Received: by 2002:aca:32c1:0:b0:2ce:6ee7:2c9f with SMTP id y184-20020aca32c1000000b002ce6ee72c9fmr6192858oiy.205.1645674189114; Wed, 23 Feb 2022 19:43:09 -0800 (PST) Received: from builder.lan ([2600:1700:a0:3dc8:3697:f6ff:fe85:aac9]) by smtp.gmail.com with ESMTPSA id e9sm604775oos.19.2022.02.23.19.43.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Feb 2022 19:43:08 -0800 (PST) Date: Wed, 23 Feb 2022 21:43:06 -0600 From: Bjorn Andersson To: Ansuel Smith Cc: Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Taniya Das , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v4 04/16] clk: qcom: gcc-ipq806x: fix wrong naming for gcc_pxo_pll8_pll0 Message-ID: References: <20220217235703.26641-1-ansuelsmth@gmail.com> <20220217235703.26641-5-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220217235703.26641-5-ansuelsmth@gmail.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Thu 17 Feb 17:56 CST 2022, Ansuel Smith wrote: > Parent gcc_pxo_pll8_pll0 had the parent definition and parent map > swapped. Fix this naming error. > > Signed-off-by: Ansuel Smith Reviewed-by: Bjorn Andersson > --- > drivers/clk/qcom/gcc-ipq806x.c | 20 ++++++++++---------- > 1 file changed, 10 insertions(+), 10 deletions(-) > > diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c > index d6b7adb4be38..34cddf461dba 100644 > --- a/drivers/clk/qcom/gcc-ipq806x.c > +++ b/drivers/clk/qcom/gcc-ipq806x.c > @@ -291,13 +291,13 @@ static const char * const gcc_pxo_pll3[] = { > "pll3", > }; > > -static const struct parent_map gcc_pxo_pll8_pll0[] = { > +static const struct parent_map gcc_pxo_pll8_pll0_map[] = { > { P_PXO, 0 }, > { P_PLL8, 3 }, > { P_PLL0, 2 } > }; > > -static const char * const gcc_pxo_pll8_pll0_map[] = { > +static const char * const gcc_pxo_pll8_pll0[] = { > "pxo", > "pll8_vote", > "pll0_vote", > @@ -1993,7 +1993,7 @@ static struct clk_rcg usb30_master_clk_src = { > }, > .s = { > .src_sel_shift = 0, > - .parent_map = gcc_pxo_pll8_pll0, > + .parent_map = gcc_pxo_pll8_pll0_map, > }, > .freq_tbl = clk_tbl_usb30_master, > .clkr = { > @@ -2001,7 +2001,7 @@ static struct clk_rcg usb30_master_clk_src = { > .enable_mask = BIT(11), > .hw.init = &(struct clk_init_data){ > .name = "usb30_master_ref_src", > - .parent_names = gcc_pxo_pll8_pll0_map, > + .parent_names = gcc_pxo_pll8_pll0, > .num_parents = 3, > .ops = &clk_rcg_ops, > .flags = CLK_SET_RATE_GATE, > @@ -2063,7 +2063,7 @@ static struct clk_rcg usb30_utmi_clk = { > }, > .s = { > .src_sel_shift = 0, > - .parent_map = gcc_pxo_pll8_pll0, > + .parent_map = gcc_pxo_pll8_pll0_map, > }, > .freq_tbl = clk_tbl_usb30_utmi, > .clkr = { > @@ -2071,7 +2071,7 @@ static struct clk_rcg usb30_utmi_clk = { > .enable_mask = BIT(11), > .hw.init = &(struct clk_init_data){ > .name = "usb30_utmi_clk", > - .parent_names = gcc_pxo_pll8_pll0_map, > + .parent_names = gcc_pxo_pll8_pll0, > .num_parents = 3, > .ops = &clk_rcg_ops, > .flags = CLK_SET_RATE_GATE, > @@ -2133,7 +2133,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_src = { > }, > .s = { > .src_sel_shift = 0, > - .parent_map = gcc_pxo_pll8_pll0, > + .parent_map = gcc_pxo_pll8_pll0_map, > }, > .freq_tbl = clk_tbl_usb, > .clkr = { > @@ -2141,7 +2141,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_src = { > .enable_mask = BIT(11), > .hw.init = &(struct clk_init_data){ > .name = "usb_hs1_xcvr_src", > - .parent_names = gcc_pxo_pll8_pll0_map, > + .parent_names = gcc_pxo_pll8_pll0, > .num_parents = 3, > .ops = &clk_rcg_ops, > .flags = CLK_SET_RATE_GATE, > @@ -2197,7 +2197,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_src = { > }, > .s = { > .src_sel_shift = 0, > - .parent_map = gcc_pxo_pll8_pll0, > + .parent_map = gcc_pxo_pll8_pll0_map, > }, > .freq_tbl = clk_tbl_usb, > .clkr = { > @@ -2205,7 +2205,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_src = { > .enable_mask = BIT(11), > .hw.init = &(struct clk_init_data){ > .name = "usb_fs1_xcvr_src", > - .parent_names = gcc_pxo_pll8_pll0_map, > + .parent_names = gcc_pxo_pll8_pll0, > .num_parents = 3, > .ops = &clk_rcg_ops, > .flags = CLK_SET_RATE_GATE, > -- > 2.34.1 >