From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E36B7C433FE for ; Thu, 24 Feb 2022 16:28:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229528AbiBXQ3J (ORCPT ); Thu, 24 Feb 2022 11:29:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37384 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229770AbiBXQ3I (ORCPT ); Thu, 24 Feb 2022 11:29:08 -0500 Received: from mail-ot1-x331.google.com (mail-ot1-x331.google.com [IPv6:2607:f8b0:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7501C1965EE for ; Thu, 24 Feb 2022 08:28:37 -0800 (PST) Received: by mail-ot1-x331.google.com with SMTP id l25-20020a9d7a99000000b005af173a2875so1640479otn.2 for ; Thu, 24 Feb 2022 08:28:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=Tws7ZXpM+PZc0CK0cVaZrCHFV7BPRjaCWbwFJSB4uHI=; b=gGGXB3s1XU/Jl+tQ3PSSFy+TQcXe3tcSTVTuFCvZW1w9l3Jb43G/q7V/N1xagmSonu 6WxMEqoManJU5rF/K8t2gZUMW1Dh407q0MyPbikVpaZ+TXv5tvMyhYLci8r4gzuzDSD4 G3W2wOinGLKK495jA29V5Zrty4bqxytsc1WKb4UmuJ1pwLsO7ulkLme8jS+HHiOxF/ei lHS2NjjQfOG111fidmaRpuhHdCUvx2M7ZIRz/D1ssXxMsSiWhvKd3FnnUwH8NjodLnbV +Xa8x0ov1O7u6s9R9yQfQHOZrWlseViXoHMTQhXkd3uEEoR6NJGVGnHzhDxkvfKuMmO6 QKAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=Tws7ZXpM+PZc0CK0cVaZrCHFV7BPRjaCWbwFJSB4uHI=; b=X6Tpcyu9HGjoD+cUfYGhqAAoNWbgr7Oebcoh5t9DUQi2+d9DuQXZmBR6i6GcZKo7ni DTNEGZw898EOhPxllJC3yQhduwIqJD37Rdz030Hu6WnmG8pDout/w9DI/M1paEByCBFL xcFN92w3tMTEzpFezP/T2umsJgGy2G7tVKldkl1AP++/u8ujoySUfEQ2Ojr/Mvl6PPCr qQl9GDJKDJF39WpNEHxFJaFxbXTBsgwnbGT0ds4+ayM7H8fKQWfh67lCm6+oqNX0TKJl JPgKc1JHwUR0NMhjd0GcK5mKxlTc5bvFiSp4Mp7VbId8ubrstCuFc54hyjeS1no6c1b2 V7CA== X-Gm-Message-State: AOAM532Qw4yeyw1K8FoxtL7jf+SAbAZIB0SJwlOB50T8TxiPwDJ80mOT X9YVtfTP9Ux5hLRdZPXlE1TLrS9D936CsA== X-Google-Smtp-Source: ABdhPJw2WlUPhxTSbdyd1LW3KRyGcWe5GoUwG2vd4ysIqVSblKp59SBKER8m2mJkBR4Dnhwd0N1jFg== X-Received: by 2002:a9d:467:0:b0:5ac:c840:eb0c with SMTP id 94-20020a9d0467000000b005acc840eb0cmr1202877otc.228.1645719390679; Thu, 24 Feb 2022 08:16:30 -0800 (PST) Received: from ripper ([2600:1700:a0:3dc8:205:1bff:fec0:b9b3]) by smtp.gmail.com with ESMTPSA id ay42sm1662102oib.5.2022.02.24.08.16.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Feb 2022 08:16:30 -0800 (PST) Date: Thu, 24 Feb 2022 08:18:28 -0800 From: Bjorn Andersson To: Ansuel Smith Cc: Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Taniya Das , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v4 12/16] dt-bindings: clock: add ipq8064 ce5 clk define Message-ID: References: <20220217235703.26641-1-ansuelsmth@gmail.com> <20220217235703.26641-13-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Thu 24 Feb 08:01 PST 2022, Ansuel Smith wrote: > On Wed, Feb 23, 2022 at 10:01:14PM -0600, Bjorn Andersson wrote: > > On Thu 17 Feb 17:56 CST 2022, Ansuel Smith wrote: > > > > > Add ipq8064 ce5 clk define needed for CryptoEngine in gcc driver. > > > > > > > Reviewed-by: Bjorn Andersson > > > > > Signed-off-by: Ansuel Smith > > > --- > > > include/dt-bindings/clock/qcom,gcc-ipq806x.h | 5 ++++- > > > 1 file changed, 4 insertions(+), 1 deletion(-) > > > > > > diff --git a/include/dt-bindings/clock/qcom,gcc-ipq806x.h b/include/dt-bindings/clock/qcom,gcc-ipq806x.h > > > index 7deec14a6dee..02262d2ac899 100644 > > > --- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h > > > +++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h > > > @@ -240,7 +240,7 @@ > > > #define PLL14 232 > > > #define PLL14_VOTE 233 > > > #define PLL18 234 > > > -#define CE5_SRC 235 > > > +#define CE5_A_CLK 235 > > > #define CE5_H_CLK 236 > > > #define CE5_CORE_CLK 237 > > > #define CE3_SLEEP_CLK 238 > > > @@ -283,5 +283,8 @@ > > > #define EBI2_AON_CLK 281 > > > #define NSSTCM_CLK_SRC 282 > > > #define NSSTCM_CLK 283 > > > > You don't like 284? > > > > Regards, > > Bjorn > > > > In the QSDK 284 is used for a virtual clk used to scale the NSS core. > I skipped that in case we will implement it and to keep these header > similar across QSDK and linux. > Okay, let's take a look at how that virtual clock is implemented once you get there. But I'm fine with the reasoning for leaving a gap. Regards, Bjorn > > > +#define CE5_A_CLK_SRC 285 > > > +#define CE5_H_CLK_SRC 286 > > > +#define CE5_CORE_CLK_SRC 287 > > > > > > #endif > > > -- > > > 2.34.1 > > > > > -- > Ansuel