* [PATCH 1/4] dt-bindings: clock: add QCOM SM6350 display clock bindings
@ 2022-02-22 1:15 Konrad Dybcio
2022-02-22 1:15 ` [PATCH 3/4] dt-bindings: clock: add SM6350 QCOM Graphics " Konrad Dybcio
2022-02-25 19:12 ` [PATCH 1/4] dt-bindings: clock: add QCOM SM6350 display " Rob Herring
0 siblings, 2 replies; 4+ messages in thread
From: Konrad Dybcio @ 2022-02-22 1:15 UTC (permalink / raw)
To: ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Konrad Dybcio, Bjorn Andersson, Andy Gross,
Michael Turquette, Stephen Boyd, Rob Herring, linux-arm-msm,
linux-clk, devicetree, linux-kernel
Add device tree bindings for display clock controller for
Qualcomm Technology Inc's SM6350 SoC.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
.../bindings/clock/qcom,dispcc-sm6350.yaml | 86 +++++++++++++++++++
.../dt-bindings/clock/qcom,dispcc-sm6350.h | 48 +++++++++++
2 files changed, 134 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,dispcc-sm6350.yaml
create mode 100644 include/dt-bindings/clock/qcom,dispcc-sm6350.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6350.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6350.yaml
new file mode 100644
index 000000000000..e706678b353a
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6350.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6350.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display Clock & Reset Controller Binding for SM6350
+
+maintainers:
+ - Konrad Dybcio <konrad.dybcio@somainline.org>
+
+description: |
+ Qualcomm display clock control module which supports the clocks, resets and
+ power domains on SM6350.
+
+ See also dt-bindings/clock/qcom,dispcc-sm6350.h.
+
+properties:
+ compatible:
+ const: qcom,sm6350-dispcc
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: GPLL0 source from GCC
+ - description: Byte clock from DSI PHY
+ - description: Pixel clock from DSI PHY
+ - description: Link clock from DP PHY
+ - description: VCO DIV clock from DP PHY
+
+ clock-names:
+ items:
+ - const: bi_tcxo
+ - const: gcc_disp_gpll0_clk
+ - const: dsi0_phy_pll_out_byteclk
+ - const: dsi0_phy_pll_out_dsiclk
+ - const: dp_phy_pll_link_clk
+ - const: dp_phy_pll_vco_div_clk
+
+ '#clock-cells':
+ const: 1
+
+ '#reset-cells':
+ const: 1
+
+ '#power-domain-cells':
+ const: 1
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#reset-cells'
+ - '#power-domain-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-sm6350.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ clock-controller@af00000 {
+ compatible = "qcom,sm6350-dispcc";
+ reg = <0x0af00000 0x20000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_DISP_GPLL0_CLK>,
+ <&dsi_phy 0>,
+ <&dsi_phy 1>,
+ <&dp_phy 0>,
+ <&dp_phy 1>;
+ clock-names = "bi_tcxo",
+ "gcc_disp_gpll0_clk",
+ "dsi0_phy_pll_out_byteclk",
+ "dsi0_phy_pll_out_dsiclk",
+ "dp_phy_pll_link_clk",
+ "dp_phy_pll_vco_div_clk";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+...
diff --git a/include/dt-bindings/clock/qcom,dispcc-sm6350.h b/include/dt-bindings/clock/qcom,dispcc-sm6350.h
new file mode 100644
index 000000000000..cb54aae2723e
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,dispcc-sm6350.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6350_H
+#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6350_H
+
+/* DISP_CC clocks */
+#define DISP_CC_PLL0 0
+#define DISP_CC_MDSS_AHB_CLK 1
+#define DISP_CC_MDSS_AHB_CLK_SRC 2
+#define DISP_CC_MDSS_BYTE0_CLK 3
+#define DISP_CC_MDSS_BYTE0_CLK_SRC 4
+#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 5
+#define DISP_CC_MDSS_BYTE0_INTF_CLK 6
+#define DISP_CC_MDSS_DP_AUX_CLK 7
+#define DISP_CC_MDSS_DP_AUX_CLK_SRC 8
+#define DISP_CC_MDSS_DP_CRYPTO_CLK 9
+#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 10
+#define DISP_CC_MDSS_DP_LINK_CLK 11
+#define DISP_CC_MDSS_DP_LINK_CLK_SRC 12
+#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC 13
+#define DISP_CC_MDSS_DP_LINK_INTF_CLK 14
+#define DISP_CC_MDSS_DP_PIXEL_CLK 15
+#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 16
+#define DISP_CC_MDSS_ESC0_CLK 17
+#define DISP_CC_MDSS_ESC0_CLK_SRC 18
+#define DISP_CC_MDSS_MDP_CLK 19
+#define DISP_CC_MDSS_MDP_CLK_SRC 20
+#define DISP_CC_MDSS_MDP_LUT_CLK 21
+#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 22
+#define DISP_CC_MDSS_PCLK0_CLK 23
+#define DISP_CC_MDSS_PCLK0_CLK_SRC 24
+#define DISP_CC_MDSS_ROT_CLK 25
+#define DISP_CC_MDSS_ROT_CLK_SRC 26
+#define DISP_CC_MDSS_RSCC_AHB_CLK 27
+#define DISP_CC_MDSS_RSCC_VSYNC_CLK 28
+#define DISP_CC_MDSS_VSYNC_CLK 29
+#define DISP_CC_MDSS_VSYNC_CLK_SRC 30
+#define DISP_CC_SLEEP_CLK 31
+#define DISP_CC_XO_CLK 32
+
+/* GDSCs */
+#define MDSS_GDSC 0
+
+#endif
--
2.35.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 3/4] dt-bindings: clock: add SM6350 QCOM Graphics clock bindings
2022-02-22 1:15 [PATCH 1/4] dt-bindings: clock: add QCOM SM6350 display clock bindings Konrad Dybcio
@ 2022-02-22 1:15 ` Konrad Dybcio
2022-02-25 19:13 ` Rob Herring
2022-02-25 19:12 ` [PATCH 1/4] dt-bindings: clock: add QCOM SM6350 display " Rob Herring
1 sibling, 1 reply; 4+ messages in thread
From: Konrad Dybcio @ 2022-02-22 1:15 UTC (permalink / raw)
To: ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Konrad Dybcio, Bjorn Andersson, Andy Gross,
Michael Turquette, Stephen Boyd, Rob Herring, Taniya Das,
linux-arm-msm, linux-clk, devicetree, linux-kernel
Add device tree bindings for graphics clock controller for
Qualcomm Technology Inc's SM6350 SoCs.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
.../devicetree/bindings/clock/qcom,gpucc.yaml | 2 +
include/dt-bindings/clock/qcom,gpucc-sm6350.h | 37 +++++++++++++++++++
2 files changed, 39 insertions(+)
create mode 100644 include/dt-bindings/clock/qcom,gpucc-sm6350.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
index 46dff46d5760..9ebcb1943b0a 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
@@ -17,6 +17,7 @@ description: |
dt-bindings/clock/qcom,gpucc-sdm845.h
dt-bindings/clock/qcom,gpucc-sc7180.h
dt-bindings/clock/qcom,gpucc-sc7280.h
+ dt-bindings/clock/qcom,gpucc-sm6350.h
dt-bindings/clock/qcom,gpucc-sm8150.h
dt-bindings/clock/qcom,gpucc-sm8250.h
@@ -27,6 +28,7 @@ properties:
- qcom,sc7180-gpucc
- qcom,sc7280-gpucc
- qcom,sc8180x-gpucc
+ - qcom,sm6350-gpucc
- qcom,sm8150-gpucc
- qcom,sm8250-gpucc
diff --git a/include/dt-bindings/clock/qcom,gpucc-sm6350.h b/include/dt-bindings/clock/qcom,gpucc-sm6350.h
new file mode 100644
index 000000000000..68e814fc8acd
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gpucc-sm6350.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6350_H
+#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6350_H
+
+/* GPU_CC clocks */
+#define GPU_CC_PLL0 0
+#define GPU_CC_PLL1 1
+#define GPU_CC_ACD_AHB_CLK 2
+#define GPU_CC_ACD_CXO_CLK 3
+#define GPU_CC_AHB_CLK 4
+#define GPU_CC_CRC_AHB_CLK 5
+#define GPU_CC_CX_GFX3D_CLK 6
+#define GPU_CC_CX_GFX3D_SLV_CLK 7
+#define GPU_CC_CX_GMU_CLK 8
+#define GPU_CC_CX_SNOC_DVM_CLK 9
+#define GPU_CC_CXO_AON_CLK 10
+#define GPU_CC_CXO_CLK 11
+#define GPU_CC_GMU_CLK_SRC 12
+#define GPU_CC_GX_CXO_CLK 13
+#define GPU_CC_GX_GFX3D_CLK 14
+#define GPU_CC_GX_GFX3D_CLK_SRC 15
+#define GPU_CC_GX_GMU_CLK 16
+#define GPU_CC_GX_VSENSE_CLK 17
+
+/* CLK_HW */
+#define GPU_CC_CRC_DIV 0
+
+/* GDSCs */
+#define GPU_CX_GDSC 0
+#define GPU_GX_GDSC 1
+
+#endif
--
2.35.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 1/4] dt-bindings: clock: add QCOM SM6350 display clock bindings
2022-02-22 1:15 [PATCH 1/4] dt-bindings: clock: add QCOM SM6350 display clock bindings Konrad Dybcio
2022-02-22 1:15 ` [PATCH 3/4] dt-bindings: clock: add SM6350 QCOM Graphics " Konrad Dybcio
@ 2022-02-25 19:12 ` Rob Herring
1 sibling, 0 replies; 4+ messages in thread
From: Rob Herring @ 2022-02-25 19:12 UTC (permalink / raw)
To: Konrad Dybcio
Cc: marijn.suijten, devicetree, linux-kernel, Stephen Boyd,
martin.botka, linux-arm-msm, Michael Turquette, Andy Gross,
Bjorn Andersson, linux-clk, jamipkettunen,
~postmarketos/upstreaming, Rob Herring, angelogioacchino.delregno
On Tue, 22 Feb 2022 02:15:28 +0100, Konrad Dybcio wrote:
> Add device tree bindings for display clock controller for
> Qualcomm Technology Inc's SM6350 SoC.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
> ---
> .../bindings/clock/qcom,dispcc-sm6350.yaml | 86 +++++++++++++++++++
> .../dt-bindings/clock/qcom,dispcc-sm6350.h | 48 +++++++++++
> 2 files changed, 134 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/qcom,dispcc-sm6350.yaml
> create mode 100644 include/dt-bindings/clock/qcom,dispcc-sm6350.h
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 3/4] dt-bindings: clock: add SM6350 QCOM Graphics clock bindings
2022-02-22 1:15 ` [PATCH 3/4] dt-bindings: clock: add SM6350 QCOM Graphics " Konrad Dybcio
@ 2022-02-25 19:13 ` Rob Herring
0 siblings, 0 replies; 4+ messages in thread
From: Rob Herring @ 2022-02-25 19:13 UTC (permalink / raw)
To: Konrad Dybcio
Cc: ~postmarketos/upstreaming, jamipkettunen, linux-clk, Stephen Boyd,
Bjorn Andersson, Michael Turquette, Rob Herring, devicetree,
martin.botka, Andy Gross, marijn.suijten, linux-kernel,
linux-arm-msm, angelogioacchino.delregno, Taniya Das
On Tue, 22 Feb 2022 02:15:30 +0100, Konrad Dybcio wrote:
> Add device tree bindings for graphics clock controller for
> Qualcomm Technology Inc's SM6350 SoCs.
>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
> ---
> .../devicetree/bindings/clock/qcom,gpucc.yaml | 2 +
> include/dt-bindings/clock/qcom,gpucc-sm6350.h | 37 +++++++++++++++++++
> 2 files changed, 39 insertions(+)
> create mode 100644 include/dt-bindings/clock/qcom,gpucc-sm6350.h
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2022-02-25 19:13 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2022-02-22 1:15 [PATCH 1/4] dt-bindings: clock: add QCOM SM6350 display clock bindings Konrad Dybcio
2022-02-22 1:15 ` [PATCH 3/4] dt-bindings: clock: add SM6350 QCOM Graphics " Konrad Dybcio
2022-02-25 19:13 ` Rob Herring
2022-02-25 19:12 ` [PATCH 1/4] dt-bindings: clock: add QCOM SM6350 display " Rob Herring
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).