From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1C69C4332F for ; Mon, 14 Mar 2022 12:20:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240793AbiCNMVs (ORCPT ); Mon, 14 Mar 2022 08:21:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48906 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242304AbiCNMS4 (ORCPT ); Mon, 14 Mar 2022 08:18:56 -0400 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [IPv6:2001:4b98:dc2:55:216:3eff:fef7:d647]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 690464754D; Mon, 14 Mar 2022 05:13:59 -0700 (PDT) Received: from pendragon.ideasonboard.com (62-78-145-57.bb.dnainternet.fi [62.78.145.57]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 1CE3130B; Mon, 14 Mar 2022 13:13:56 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1647260036; bh=CCBbr7YW6AtHXNdUGRWrM8dwrLI+DcEe4pseQUM4RHY=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=RXYeAcOdrMmmaGhWIbNyyLP5lf08OVC6hdRP4viaoEz2/yVqxuzIqgMgFry9LZhjc AYivOazAv5K10ulztR+upt/4qxSvtLw2XYEA8Jqovmm7kHvcJYsqLKzNjseMjl7BMa s21gEzBTRUE5lpROWveHbHI8k+sG8eXrepFTjPJo= Date: Mon, 14 Mar 2022 14:13:38 +0200 From: Laurent Pinchart To: Geert Uytterhoeven Cc: Biju Das , Mauro Carvalho Chehab , Rob Herring , Kieran Bingham , "linux-media@vger.kernel.org" , "linux-renesas-soc@vger.kernel.org" , "devicetree@vger.kernel.org" , Geert Uytterhoeven , Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: Re: [PATCH v5 1/3] media: dt-bindings: media: renesas,vsp1: Document RZ/{G2L,V2L} VSPD bindings Message-ID: References: <20220312084205.31462-1-biju.das.jz@bp.renesas.com> <20220312084205.31462-2-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Geert, On Mon, Mar 14, 2022 at 10:01:14AM +0100, Geert Uytterhoeven wrote: > On Mon, Mar 14, 2022 at 9:44 AM Biju Das wrote: > > > On Sat, Mar 12, 2022 at 08:42:03AM +0000, Biju Das wrote: > > > > Document VSPD found in RZ/G2L and RZ/V2L family SoC's. VSPD block is > > > > similar to VSP2-D found on R-Car SoC's, but it does not have a version > > > > register and it has 3 clocks compared to 1 clock on vsp1 and vsp2. > > > > > > > > This patch introduces a new compatible 'renesas,rzg2l-vsp2' to handle > > > > these differences. > > > > > > > > Signed-off-by: Biju Das > > > > > index 990e9c1dbc43..2696a4582251 100644 > > > > --- a/Documentation/devicetree/bindings/media/renesas,vsp1.yaml > > > > +++ b/Documentation/devicetree/bindings/media/renesas,vsp1.yaml > > > > > + clock-names: > > > > + items: > > > > + - const: du.0 > > > > > > Similarly, I'm not sure this is a good name from the point of view of the > > > VSP. > > > > OK, will use the name 'aclk', which is Main clock for this module which is > > shared with LCDC. 'du.0' is not valid any more here as we are using different > > CRTC implementation for RZ/G2LC. > > > > > > + - const: pclk > > > > + - const: vclk > > > > > > I couldn't find those names in the documentation, where do they come from > > > > HW manual (page 312) mentions about LCDC_CLK_A, LCDC_CLK_P & LCDC_CLK_D. > > > > Detailed description is mentioned in Clock list document. Please see below. > > > > LCDC_CLK_A M0φ PLL3 200 200 LCDC Main clock > > LCDC_CLK_P ZTφ PLL3 100 100 LCDC Register Access Clock > > LCDC_CLK_D M3φ SEL_PLL5_4 148.5~5.803 LCDC Video Clock > > > > > ? Could you maybe share a DT integration example ? > > > > Please see below, > > > > > + du: display@0x10890000 { > > + compatible = "renesas,du-r9a07g044l"; > > + reg = <0 0x10890000 0 0x10000>; > > + interrupts = ; > > + clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>, > > + <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>, > > + <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>; > > + clock-names = "du.0", "pclk", "vclk"; > > + power-domains = <&cpg>; > > + resets = <&cpg R9A07G044_LCDC_RESET_N>; > > + reset-names = "du.0"; > > + renesas,vsps = <&vspd0 0>; > > Given the DU driver is no longer shared, perhaps all occurrencies of "du" > should be replaced by "lcdc"? The LCDC is the combination of the FCPVD, the VSPD and the DU. The first two are similar to the eponymous IP cores used on R-Car Gen3, while the DU is a different beast, despite sharing the same name. -- Regards, Laurent Pinchart