[PATCH V2 0/7] Add Renesas RZ/G2UL Type-1 {SoC,SMARC EVK} support

[PATCH V2 0/7] Add Renesas RZ/G2UL Type-1 {SoC,SMARC EVK} support

[Biju Das]

Hi All,

RZ/G2UL Family SoC consists of Type-1 and Type-2 SoC's.
Both these SoC's has single Core 1.0GHz CA-55 with similar
peripheral IP's to that of RZ/G2LC and RZ/G2L.

The difference between Type1 and Type2 SoC's are as follows
Function	Type1			Type2
SCIF		5ch {0,1,2,3,4}		4ch {0,1,2,3}
Ethernet	2ch {0,1}		1ch {0}
SSI		4ch {0,1,2,3}		3ch {0,1,2}
ADC		2ch {0,1}		N/A
DU		1ch Parallel I/F	N/A

RZ/G2UL Type-2 is pin compatible with RZ/G2LC, so the number of channels
for each IP matches with RZ/G2LC.
The table below shows the functional differences between RZ/G2LC and 
RZ/G2UL Type-2.
Function	RZ/G2LC			RZ/G2UL Type-2
Cortex-A55	Dual 1.2GHz		Single 1.0GHz
DU		1ch MIPI-DSI		N/A
GPT		6ch {0,3,4,5,6,7}	N/A
Mali-31		1ch			N/A

This patch series aims to add support for Renesas RZ/G2UL Type-1 SoC and
basic support for Renesas RZ/G2UL SMARC EVK (based on R9A07G043U11)
- memory
- External input clock
- SCIF
- GbEthernet

It shares the same carrier board with RZ/G2L, but the pin mapping is
different. Place holders are added in device nodes to avoid compilation
errors for the devices which have not been enabled yet on RZ/G2UL SoC.

Also disable the device nodes which is not tested and delete the
corresponding pinctrl definitions.

Test logs:-

/ # for i in machine family soc_id revision; do echo -n "$i: "; cat /sys/devices/soc0/$i;done
machine: Renesas SMARC EVK based on r9a07g043u11
family: RZ/G2UL
soc_id: r9a07g043u11
revision: 0

/ # cat /proc/cpuinfo
processor       : 0
BogoMIPS        : 48.00
Features        : fp asimd evtstrm crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp
CPU implementer : 0x41
CPU architecture: 8
CPU variant     : 0x2
CPU part        : 0xd05
CPU revision    : 0

/ # cat /proc/interrupts
           CPU0
 11:        397     GICv3  27 Level     arch_timer
 13:          0     GICv3 412 Level     1004b800.serial:rx err
 14:         11     GICv3 414 Level     1004b800.serial:rx full
 15:        333     GICv3 415 Level     1004b800.serial:tx empty
 16:          0     GICv3 413 Level     1004b800.serial:break
 17:         28     GICv3 416 Level     1004b800.serial:rx ready
 18:          0     GICv3 173 Edge      error
 19:          0     GICv3 157 Edge      11820000.dma-controller:0
 20:          0     GICv3 158 Edge      11820000.dma-controller:1
 21:          0     GICv3 159 Edge      11820000.dma-controller:2
 22:          0     GICv3 160 Edge      11820000.dma-controller:3
 23:          0     GICv3 161 Edge      11820000.dma-controller:4
 24:          0     GICv3 162 Edge      11820000.dma-controller:5
 25:          0     GICv3 163 Edge      11820000.dma-controller:6
 26:          0     GICv3 164 Edge      11820000.dma-controller:7
 27:          0     GICv3 165 Edge      11820000.dma-controller:8
 28:          0     GICv3 166 Edge      11820000.dma-controller:9
 29:          0     GICv3 167 Edge      11820000.dma-controller:10
 30:          0     GICv3 168 Edge      11820000.dma-controller:11
 31:          0     GICv3 169 Edge      11820000.dma-controller:12
 32:          0     GICv3 170 Edge      11820000.dma-controller:13
 33:          0     GICv3 171 Edge      11820000.dma-controller:14
 34:          0     GICv3 172 Edge      11820000.dma-controller:15
IPI0:         0       Rescheduling interrupts
IPI1:         0       Function call interrupts
IPI2:         0       CPU stop interrupts
IPI3:         0       CPU stop (for crash dump) interrupts
IPI4:         0       Timer broadcast interrupts
IPI5:         0       IRQ work interrupts
IPI6:         0       CPU wake-up interrupts
Err:          0

/ # cat /proc/meminfo
MemTotal:         872180 kB
MemFree:          848960 kB
MemAvailable:     816180 kB
Buffers:               0 kB
Cached:             3948 kB
SwapCached:            0 kB
Active:                4 kB
Inactive:             76 kB
Active(anon):          4 kB
Inactive(anon):       76 kB
Active(file):          0 kB
Inactive(file):        0 kB
Unevictable:        3948 kB
Mlocked:               0 kB
SwapTotal:             0 kB
SwapFree:              0 kB
Dirty:                 0 kB
Writeback:             0 kB
AnonPages:           116 kB
Mapped:             1292 kB
Shmem:                 0 kB
KReclaimable:       2024 kB
Slab:               6868 kB
SReclaimable:       2024 kB
SUnreclaim:         4844 kB
KernelStack:         908 kB
PageTables:           64 kB
NFS_Unstable:          0 kB
Bounce:                0 kB
WritebackTmp:          0 kB
CommitLimit:      436088 kB
Committed_AS:        592 kB
VmallocTotal:   133143592960 kB
VmallocUsed:        1136 kB
VmallocChunk:          0 kB
Percpu:               92 kB
HardwareCorrupted:     0 kB
AnonHugePages:         0 kB
ShmemHugePages:        0 kB
ShmemPmdMapped:        0 kB
FileHugePages:         0 kB
FilePmdMapped:         0 kB
CmaTotal:          32768 kB
CmaFree:           32384 kB
HugePages_Total:       0
HugePages_Free:        0
HugePages_Rsvd:        0
HugePages_Surp:        0
Hugepagesize:       2048 kB
Hugetlb:               0 kB

/ # mount -t debugfs none /sys/kernel/debug/
/ #  cat /sys/kernel/debug/clk/clk_summary
                                 enable  prepare  protect                                duty  hardware
   clock                          count    count    count        rate   accuracy phase  cycle    enable
-------------------------------------------------------------------------------------------------------
 audio_mclock                         0        0        0    11289600          0     0  50000         Y
 extal                                2        2        0    24000000          0     0  50000         Y
    .pll6                             0        0        0   500000000          0     0  50000         Y
    .pll5                             0        0        0  3000000000          0     0  50000         Y
    .pll3                             1        1        0  1600000000          0     0  50000         Y
       .pll3_div2                     1        1        0   800000000          0     0  50000         Y
          .pll3_div2_4                1        1        0   200000000          0     0  50000         Y
             P1                       4        4        0   200000000          0     0  50000         Y
                dmac_aclk             2        2        0   200000000          0     0  50000         Y
                ia55_clk              1        1        0   200000000          0     0  50000         Y
                gic                   1        1        0   200000000          0     0  50000         Y
                P1_DIV2               1        1        0   100000000          0     0  50000         Y
                   dmac_pclk          1        1        0   100000000          0     0  50000         Y
             .pll3_div2_4_2           0        0        0   100000000          0     0  50000         Y
                P2                    0        0        0   100000000          0     0  50000         Y
                   ia55_pclk          0        0        0   100000000          0     0  50000         N
    .pll2                             1        1        0  1600000000          0     0  50000         Y
       .pll2_div2                     1        1        0   800000000          0     0  50000         Y
          .pll2_div2_8                1        1        0   100000000          0     0  50000         Y
             P0                       1        1        0   100000000          0     0  50000         Y
                sci1                  0        0        0   100000000          0     0  50000         N
                sci0                  0        0        0   100000000          0     0  50000         N
                scif4                 0        0        0   100000000          0     0  50000         N
                scif3                 0        0        0   100000000          0     0  50000         N
                scif2                 0        0        0   100000000          0     0  50000         N
                scif1                 0        0        0   100000000          0     0  50000         N
                scif0                 2        2        0   100000000          0     0  50000         Y
    .pll1                             0        0        0  1000000000          0     0  50000         Y
       I                              0        0        0  1000000000          0     0  50000         Y
    .osc_div1000                      0        0        0       24000          0     0  50000         Y
    .osc                              0        0        0    24000000          0     0  50000         Y
 can                                  0        0        0           0          0     0  50000         Y
 audio_clk2                           0        0        0    12288000          0     0  50000         Y
 audio_clk1                           0        0        0    11289600          0     0  50000         Y
/ #

v1->v2:
 * Updated soc identification compatible from r9a07g043u->r9a07g043u11
 * Updated soc dtsi/board dts with generic compatible r9a07g043.
 * Updated the test logs with soc_id change.

Cheers,
Biju

Biju Das (7):
  dt-bindings: power: renesas,rzg2l-sysc: Document RZ/G2UL SoC
  soc: renesas: Identify RZ/G2UL SoC
  dt-bindings: clock: Add R9A07G043U CPG Clock and Reset Definitions
  dt-bindings: clock: renesas: Document RZ/G2UL SoC
  clk: renesas: Add support for RZ/G2UL SoC
  arm64: dts: renesas: Add initial DTSI for RZ/G2UL SoC
  arm64: dts: renesas: Add initial device tree for RZ/G2UL Type-1 SMARC
    EVK

 .../bindings/clock/renesas,rzg2l-cpg.yaml     |   9 +-
 .../bindings/power/renesas,rzg2l-sysc.yaml    |  11 +-
 arch/arm64/boot/dts/renesas/Makefile          |   2 +
 arch/arm64/boot/dts/renesas/r9a07g043u.dtsi   | 413 ++++++++++++++++++
 .../boot/dts/renesas/r9a07g043u11-smarc.dts   | 111 +++++
 .../boot/dts/renesas/rzg2ul-smarc-som.dtsi    |  25 ++
 drivers/clk/renesas/Kconfig                   |   7 +-
 drivers/clk/renesas/Makefile                  |   1 +
 drivers/clk/renesas/r9a07g043-cpg.c           | 157 +++++++
 drivers/clk/renesas/rzg2l-cpg.c               |   6 +
 drivers/clk/renesas/rzg2l-cpg.h               |   1 +
 drivers/soc/renesas/Kconfig                   |   6 +
 drivers/soc/renesas/renesas-soc.c             |  13 +
 include/dt-bindings/clock/r9a07g043u-cpg.h    | 186 ++++++++
 14 files changed, 938 insertions(+), 10 deletions(-)
 create mode 100644 arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
 create mode 100644 arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts
 create mode 100644 arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
 create mode 100644 drivers/clk/renesas/r9a07g043-cpg.c
 create mode 100644 include/dt-bindings/clock/r9a07g043u-cpg.h

-- 
2.17.1

[PATCH V2 1/7] dt-bindings: power: renesas,rzg2l-sysc: Document RZ/G2UL SoC

[Biju Das]

Add DT binding documentation for SYSC controller found on RZ/G2UL SoC's.
SYSC controller found on the RZ/G2UL SoC is almost identical to one found
on the RZ/G2L SoC's only difference being that the RZ/G2UL has only CA55
core0 reset vector address configuration register.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
V1->V2:
 * No change
---
 .../devicetree/bindings/power/renesas,rzg2l-sysc.yaml | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml b/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml
index bb433e75a0ee..ce372378ff97 100644
--- a/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml
+++ b/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml
@@ -4,14 +4,14 @@
 $id: "http://devicetree.org/schemas/power/renesas,rzg2l-sysc.yaml#"
 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
 
-title: Renesas RZ/{G2L,V2L} System Controller (SYSC)
+title: Renesas RZ/{G2L, G2UL, V2L} System Controller (SYSC)
 
 maintainers:
   - Geert Uytterhoeven <geert+renesas@glider.be>
 
 description:
-  The RZ/{G2L,V2L} System Controller (SYSC) performs system control of the LSI
-  and supports following functions,
+  The RZ/{G2L, G2UL, V2L} System Controller (SYSC) performs system control of
+  the LSI and supports following functions,
   - External terminal state capture function
   - 34-bit address space access function
   - Low power consumption control
@@ -20,8 +20,9 @@ description:
 properties:
   compatible:
     enum:
-      - renesas,r9a07g044-sysc # RZ/G2{L,LC}
-      - renesas,r9a07g054-sysc # RZ/V2L
+      - renesas,r9a07g043u-sysc # RZ/G2UL
+      - renesas,r9a07g044-sysc  # RZ/G2{L,LC}
+      - renesas,r9a07g054-sysc  # RZ/V2L
 
   reg:
     maxItems: 1
-- 
2.17.1

[PATCH V2 3/7] dt-bindings: clock: Add R9A07G043U CPG Clock and Reset Definitions

[Biju Das]

Define RZ/G2UL (R9A07G043U) Clock Pulse Generator Core Clock and module
clock outputs, as listed in Table 7.1.4.2 ("Clock List r0.51") and also
add Reset definitions referring to registers CPG_RST_* in Section 7.2.3
("Register configuration") of the RZ/G2UL Hardware User's Manual (Rev.
0.51, Nov. 2021).

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2:
 * No change
---
 include/dt-bindings/clock/r9a07g043u-cpg.h | 186 +++++++++++++++++++++
 1 file changed, 186 insertions(+)
 create mode 100644 include/dt-bindings/clock/r9a07g043u-cpg.h

diff --git a/include/dt-bindings/clock/r9a07g043u-cpg.h b/include/dt-bindings/clock/r9a07g043u-cpg.h
new file mode 100644
index 000000000000..447f0c2471d3
--- /dev/null
+++ b/include/dt-bindings/clock/r9a07g043u-cpg.h
@@ -0,0 +1,186 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R9A07G043U_CPG_H__
+#define __DT_BINDINGS_CLOCK_R9A07G043U_CPG_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* R9A07G043U CPG Core Clocks */
+#define R9A07G043U_CLK_I		0
+#define R9A07G043U_CLK_I2		1
+#define R9A07G043U_CLK_S0		2
+#define R9A07G043U_CLK_SPI0		3
+#define R9A07G043U_CLK_SPI1		4
+#define R9A07G043U_CLK_SD0		5
+#define R9A07G043U_CLK_SD1		6
+#define R9A07G043U_CLK_M0		7
+#define R9A07G043U_CLK_M2		8
+#define R9A07G043U_CLK_M3		9
+#define R9A07G043U_CLK_HP		10
+#define R9A07G043U_CLK_TSU		11
+#define R9A07G043U_CLK_ZT		12
+#define R9A07G043U_CLK_P0		13
+#define R9A07G043U_CLK_P1		14
+#define R9A07G043U_CLK_P2		15
+#define R9A07G043U_CLK_AT		16
+#define R9A07G043U_OSCCLK		17
+#define R9A07G043U_CLK_P0_DIV2		18
+
+/* R9A07G043U Module Clocks */
+#define R9A07G043U_CA55_SCLK		0
+#define R9A07G043U_CA55_PCLK		1
+#define R9A07G043U_CA55_ATCLK		2
+#define R9A07G043U_CA55_GICCLK		3
+#define R9A07G043U_CA55_PERICLK		4
+#define R9A07G043U_CA55_ACLK		5
+#define R9A07G043U_CA55_TSCLK		6
+#define R9A07G043U_GIC600_GICCLK	7
+#define R9A07G043U_IA55_CLK		8
+#define R9A07G043U_IA55_PCLK		9
+#define R9A07G043U_MHU_PCLK		10
+#define R9A07G043U_SYC_CNT_CLK		11
+#define R9A07G043U_DMAC_ACLK		12
+#define R9A07G043U_DMAC_PCLK		13
+#define R9A07G043U_OSTM0_PCLK		14
+#define R9A07G043U_OSTM1_PCLK		15
+#define R9A07G043U_OSTM2_PCLK		16
+#define R9A07G043U_MTU_X_MCK_MTU3	17
+#define R9A07G043U_POE3_CLKM_POE	18
+#define R9A07G043U_WDT0_PCLK		19
+#define R9A07G043U_WDT0_CLK		20
+#define R9A07G043U_WDT2_PCLK		21
+#define R9A07G043U_WDT2_CLK		22
+#define R9A07G043U_SPI_CLK2		23
+#define R9A07G043U_SPI_CLK		24
+#define R9A07G043U_SDHI0_IMCLK		25
+#define R9A07G043U_SDHI0_IMCLK2		26
+#define R9A07G043U_SDHI0_CLK_HS		27
+#define R9A07G043U_SDHI0_ACLK		28
+#define R9A07G043U_SDHI1_IMCLK		29
+#define R9A07G043U_SDHI1_IMCLK2		30
+#define R9A07G043U_SDHI1_CLK_HS		31
+#define R9A07G043U_SDHI1_ACLK		32
+#define R9A07G043U_ISU_ACLK		33
+#define R9A07G043U_ISU_PCLK		34
+#define R9A07G043U_CRU_SYSCLK		35
+#define R9A07G043U_CRU_VCLK		36
+#define R9A07G043U_CRU_PCLK		37
+#define R9A07G043U_CRU_ACLK		38
+#define R9A07G043U_LCDC_CLK_A		39
+#define R9A07G043U_LCDC_CLK_P		40
+#define R9A07G043U_LCDC_CLK_D		41
+#define R9A07G043U_SSI0_PCLK2		42
+#define R9A07G043U_SSI0_PCLK_SFR	43
+#define R9A07G043U_SSI1_PCLK2		44
+#define R9A07G043U_SSI1_PCLK_SFR	45
+#define R9A07G043U_SSI2_PCLK2		46
+#define R9A07G043U_SSI2_PCLK_SFR	47
+#define R9A07G043U_SSI3_PCLK2		48
+#define R9A07G043U_SSI3_PCLK_SFR	49
+#define R9A07G043U_SRC_CLKP		50
+#define R9A07G043U_USB_U2H0_HCLK	51
+#define R9A07G043U_USB_U2H1_HCLK	52
+#define R9A07G043U_USB_U2P_EXR_CPUCLK	53
+#define R9A07G043U_USB_PCLK		54
+#define R9A07G043U_ETH0_CLK_AXI		55
+#define R9A07G043U_ETH0_CLK_CHI		56
+#define R9A07G043U_ETH1_CLK_AXI		57
+#define R9A07G043U_ETH1_CLK_CHI		58
+#define R9A07G043U_I2C0_PCLK		59
+#define R9A07G043U_I2C1_PCLK		60
+#define R9A07G043U_I2C2_PCLK		61
+#define R9A07G043U_I2C3_PCLK		62
+#define R9A07G043U_SCIF0_CLK_PCK	63
+#define R9A07G043U_SCIF1_CLK_PCK	64
+#define R9A07G043U_SCIF2_CLK_PCK	65
+#define R9A07G043U_SCIF3_CLK_PCK	66
+#define R9A07G043U_SCIF4_CLK_PCK	67
+#define R9A07G043U_SCI0_CLKP		68
+#define R9A07G043U_SCI1_CLKP		69
+#define R9A07G043U_IRDA_CLKP		70
+#define R9A07G043U_RSPI0_CLKB		71
+#define R9A07G043U_RSPI1_CLKB		72
+#define R9A07G043U_RSPI2_CLKB		73
+#define R9A07G043U_CANFD_PCLK		74
+#define R9A07G043U_GPIO_HCLK		75
+#define R9A07G043U_ADC_ADCLK		76
+#define R9A07G043U_ADC_PCLK		77
+#define R9A07G043U_TSU_PCLK		78
+
+/* R9A07G043U Resets */
+#define R9A07G043U_CA55_RST_1_0			0
+#define R9A07G043U_CA55_RST_1_1			1
+#define R9A07G043U_CA55_RST_3_0			2
+#define R9A07G043U_CA55_RST_3_1			3
+#define R9A07G043U_CA55_RST_4			4
+#define R9A07G043U_CA55_RST_5			5
+#define R9A07G043U_CA55_RST_6			6
+#define R9A07G043U_CA55_RST_7			7
+#define R9A07G043U_CA55_RST_8			8
+#define R9A07G043U_CA55_RST_9			9
+#define R9A07G043U_CA55_RST_10			10
+#define R9A07G043U_CA55_RST_11			11
+#define R9A07G043U_CA55_RST_12			12
+#define R9A07G043U_GIC600_GICRESET_N		13
+#define R9A07G043U_GIC600_DBG_GICRESET_N	14
+#define R9A07G043U_IA55_RESETN			15
+#define R9A07G043U_MHU_RESETN			16
+#define R9A07G043U_DMAC_ARESETN			17
+#define R9A07G043U_DMAC_RST_ASYNC		18
+#define R9A07G043U_SYC_RESETN			19
+#define R9A07G043U_OSTM0_PRESETZ		20
+#define R9A07G043U_OSTM1_PRESETZ		21
+#define R9A07G043U_OSTM2_PRESETZ		22
+#define R9A07G043U_MTU_X_PRESET_MTU3		23
+#define R9A07G043U_POE3_RST_M_REG		24
+#define R9A07G043U_WDT0_PRESETN			25
+#define R9A07G043U_WDT2_PRESETN			26
+#define R9A07G043U_SPI_RST			27
+#define R9A07G043U_SDHI0_IXRST			28
+#define R9A07G043U_SDHI1_IXRST			29
+#define R9A07G043U_ISU_ARESETN			30
+#define R9A07G043U_ISU_PRESETN			31
+#define R9A07G043U_CRU_CMN_RSTB			32
+#define R9A07G043U_CRU_PRESETN			33
+#define R9A07G043U_CRU_ARESETN			34
+#define R9A07G043U_SRC_RST			35
+#define R9A07G043U_USB_U2H0_HRESETN		36
+#define R9A07G043U_USB_U2H1_HRESETN		37
+#define R9A07G043U_USB_U2P_EXL_SYSRST		38
+#define R9A07G043U_USB_PRESETN			39
+#define R9A07G043U_I2C0_MRST			40
+#define R9A07G043U_I2C1_MRST			41
+#define R9A07G043U_I2C2_MRST			42
+#define R9A07G043U_I2C3_MRST			43
+#define R9A07G043U_SCI0_RST			44
+#define R9A07G043U_SCI1_RST			45
+#define R9A07G043U_IRDA_RST			46
+#define R9A07G043U_RSPI0_RST			46
+#define R9A07G043U_RSPI1_RST			48
+#define R9A07G043U_RSPI2_RST			49
+#define R9A07G043U_CANFD_RSTP_N			50
+#define R9A07G043U_CANFD_RSTC_N			51
+#define R9A07G043U_GPIO_RSTN			52
+#define R9A07G043U_GPIO_PORT_RESETN		53
+#define R9A07G043U_GPIO_SPARE_RESETN		54
+#define R9A07G043U_TSU_PRESETN			55
+#define R9A07G043U_SSI0_RST_M2_REG		56
+#define R9A07G043U_SSI1_RST_M2_REG		57
+#define R9A07G043U_SSI2_RST_M2_REG		58
+#define R9A07G043U_ETH0_RST_HW_N		59
+#define R9A07G043U_SCIF0_RST_SYSTEM_N		60
+#define R9A07G043U_SCIF1_RST_SYSTEM_N		61
+#define R9A07G043U_SCIF2_RST_SYSTEM_N		62
+#define R9A07G043U_SCIF3_RST_SYSTEM_N		63
+
+/* Type-1 Specific */
+#define R9A07G043U_SSI3_RST_M2_REG		64
+#define R9A07G043U_ETH1_RST_HW_N		65
+#define R9A07G043U_SCIF4_RST_SYSTEM_N		66
+#define R9A07G043U_ADC_PRESETN			67
+#define R9A07G043U_ADC_ADRST_N			68
+#define R9A07G043U_LCDC_RESET_N			69
+
+#endif /* __DT_BINDINGS_CLOCK_R9A07G043U_CPG_H__ */
-- 
2.17.1

[PATCH V2 4/7] dt-bindings: clock: renesas: Document RZ/G2UL SoC

[Biju Das]

Document the device tree binding for the Renesas RZ/G2UL Type-1
and Type-2 SoC. RZ/G2UL Type-2 has fewer clocks than RZ/G2UL Type-1
SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2:
 * No change
---
 .../devicetree/bindings/clock/renesas,rzg2l-cpg.yaml     | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
index bd3af8fc616b..256258025c26 100644
--- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
+++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
@@ -4,13 +4,13 @@
 $id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#"
 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
 
-title: Renesas RZ/{G2L,V2L} Clock Pulse Generator / Module Standby Mode
+title: Renesas RZ/{G2L,G2UL,V2L} Clock Pulse Generator / Module Standby Mode
 
 maintainers:
   - Geert Uytterhoeven <geert+renesas@glider.be>
 
 description: |
-  On Renesas RZ/{G2L,V2L} SoC, the CPG (Clock Pulse Generator) and Module
+  On Renesas RZ/{G2L,G2UL,V2L} SoC, the CPG (Clock Pulse Generator) and Module
   Standby Mode share the same register block.
 
   They provide the following functionalities:
@@ -23,8 +23,9 @@ description: |
 properties:
   compatible:
     enum:
-      - renesas,r9a07g044-cpg  # RZ/G2{L,LC}
-      - renesas,r9a07g054-cpg  # RZ/V2L
+      - renesas,r9a07g043u-cpg  # RZ/G2UL{Type-1,Type-2}
+      - renesas,r9a07g044-cpg   # RZ/G2{L,LC}
+      - renesas,r9a07g054-cpg   # RZ/V2L
 
   reg:
     maxItems: 1
-- 
2.17.1

[PATCH V2 6/7] arm64: dts: renesas: Add initial DTSI for RZ/G2UL SoC

[Biju Das]

Add initial DTSI for RZ/G2UL SoC.

Both RZ/G2L and RZ/G2UL uses the same SMARC EVK. Therefore they share
the common dtsi (rz-smarc.dtsi) file. Place holders are added in
device nodes to avoid compilation errors for the devices which have
not been enabled yet on RZ/G2UL SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2:
 * Changed soc compatible from r9a07g043u->r9a07g043.
---
 arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 413 ++++++++++++++++++++
 1 file changed, 413 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r9a07g043u.dtsi

diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
new file mode 100644
index 000000000000..b162cc74becd
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
@@ -0,0 +1,413 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2UL SoC
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/r9a07g043u-cpg.h>
+
+/ {
+	compatible = "renesas,r9a07g043";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	audio_clk1: audio_clk1 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by boards that provide it */
+		clock-frequency = <0>;
+	};
+
+	audio_clk2: audio_clk2 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by boards that provide it */
+		clock-frequency = <0>;
+	};
+
+	/* External CAN clock - to be overridden by boards that provide it */
+	can_clk: can {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <0>;
+	};
+
+	/* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
+	extal_clk: extal {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-a55";
+			reg = <0>;
+			device_type = "cpu";
+			next-level-cache = <&L3_CA55>;
+			enable-method = "psci";
+			clocks = <&cpg CPG_CORE R9A07G043U_CLK_I>;
+		};
+
+		L3_CA55: cache-controller-0 {
+			compatible = "cache";
+			cache-unified;
+			cache-size = <0x40000>;
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-1.0", "arm,psci-0.2";
+		method = "smc";
+	};
+
+	soc: soc {
+		compatible = "simple-bus";
+		interrupt-parent = <&gic>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		ssi0: ssi@10049c00 {
+			reg = <0 0x10049c00 0 0x400>;
+			#sound-dai-cells = <0>;
+			/* place holder */
+		};
+
+		spi1: spi@1004b000 {
+			reg = <0 0x1004b000 0 0x400>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			/* place holder */
+		};
+
+		scif0: serial@1004b800 {
+			compatible = "renesas,scif-r9a07g043",
+				     "renesas,scif-r9a07g044";
+			reg = <0 0x1004b800 0 0x400>;
+			interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi",
+					  "bri", "dri", "tei";
+			clocks = <&cpg CPG_MOD R9A07G043U_SCIF0_CLK_PCK>;
+			clock-names = "fck";
+			power-domains = <&cpg>;
+			resets = <&cpg R9A07G043U_SCIF0_RST_SYSTEM_N>;
+			status = "disabled";
+		};
+
+		scif1: serial@1004bc00 {
+			compatible = "renesas,scif-r9a07g043",
+				     "renesas,scif-r9a07g044";
+			reg = <0 0x1004bc00 0 0x400>;
+			interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi",
+					  "bri", "dri", "tei";
+			clocks = <&cpg CPG_MOD R9A07G043U_SCIF1_CLK_PCK>;
+			clock-names = "fck";
+			power-domains = <&cpg>;
+			resets = <&cpg R9A07G043U_SCIF1_RST_SYSTEM_N>;
+			status = "disabled";
+		};
+
+		scif2: serial@1004c000 {
+			compatible = "renesas,scif-r9a07g043",
+				     "renesas,scif-r9a07g044";
+			reg = <0 0x1004c000 0 0x400>;
+			interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi",
+					  "bri", "dri", "tei";
+			clocks = <&cpg CPG_MOD R9A07G043U_SCIF2_CLK_PCK>;
+			clock-names = "fck";
+			power-domains = <&cpg>;
+			resets = <&cpg R9A07G043U_SCIF2_RST_SYSTEM_N>;
+			status = "disabled";
+		};
+
+		scif3: serial@1004c400 {
+			compatible = "renesas,scif-r9a07g043",
+				     "renesas,scif-r9a07g044";
+			reg = <0 0x1004c400 0 0x400>;
+			interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi",
+					  "bri", "dri", "tei";
+			clocks = <&cpg CPG_MOD R9A07G043U_SCIF3_CLK_PCK>;
+			clock-names = "fck";
+			power-domains = <&cpg>;
+			resets = <&cpg R9A07G043U_SCIF3_RST_SYSTEM_N>;
+			status = "disabled";
+		};
+
+		scif4: serial@1004c800 {
+			compatible = "renesas,scif-r9a07g043",
+				     "renesas,scif-r9a07g044";
+			reg = <0 0x1004c800 0 0x400>;
+			interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi",
+					  "bri", "dri", "tei";
+			clocks = <&cpg CPG_MOD R9A07G043U_SCIF4_CLK_PCK>;
+			clock-names = "fck";
+			power-domains = <&cpg>;
+			resets = <&cpg R9A07G043U_SCIF4_RST_SYSTEM_N>;
+			status = "disabled";
+		};
+
+		sci0: serial@1004d000 {
+			compatible = "renesas,r9a07g043-sci", "renesas,sci";
+			reg = <0 0x1004d000 0 0x400>;
+			interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			clocks = <&cpg CPG_MOD R9A07G043U_SCI0_CLKP>;
+			clock-names = "fck";
+			power-domains = <&cpg>;
+			resets = <&cpg R9A07G043U_SCI0_RST>;
+			status = "disabled";
+		};
+
+		sci1: serial@1004d400 {
+			compatible = "renesas,r9a07g043-sci", "renesas,sci";
+			reg = <0 0x1004d400 0 0x400>;
+			interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			clocks = <&cpg CPG_MOD R9A07G043U_SCI1_CLKP>;
+			clock-names = "fck";
+			power-domains = <&cpg>;
+			resets = <&cpg R9A07G043U_SCI1_RST>;
+			status = "disabled";
+		};
+
+		canfd: can@10050000 {
+			reg = <0 0x10050000 0 0x8000>;
+			/* place holder */
+		};
+
+		i2c0: i2c@10058000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0 0x10058000 0 0x400>;
+			/* place holder */
+		};
+
+		i2c1: i2c@10058400 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0 0x10058400 0 0x400>;
+			/* place holder */
+		};
+
+		i2c3: i2c@10058c00 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0 0x10058c00 0 0x400>;
+			/* place holder */
+		};
+
+		adc: adc@10059000 {
+			reg = <0 0x10059000 0 0x400>;
+			/* place holder */
+		};
+
+		sbc: spi@10060000 {
+			reg = <0 0x10060000 0 0x10000>,
+			      <0 0x20000000 0 0x10000000>,
+			      <0 0x10070000 0 0x10000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			/* place holder */
+		};
+
+		cpg: clock-controller@11010000 {
+			compatible = "renesas,r9a07g043u-cpg";
+			reg = <0 0x11010000 0 0x10000>;
+			clocks = <&extal_clk>;
+			clock-names = "extal";
+			#clock-cells = <2>;
+			#reset-cells = <1>;
+			#power-domain-cells = <0>;
+		};
+
+		sysc: system-controller@11020000 {
+			compatible = "renesas,r9a07g043u-sysc";
+			reg = <0 0x11020000 0 0x10000>;
+			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "lpm_int", "ca55stbydone_int",
+					  "cm33stbyr_int", "ca55_deny";
+			status = "disabled";
+		};
+
+		pinctrl: pinctrl@11030000 {
+			reg = <0 0x11030000 0 0x10000>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			/* place holder */
+		};
+
+		dmac: dma-controller@11820000 {
+			compatible = "renesas,r9a07g043-dmac",
+				     "renesas,rz-dmac";
+			reg = <0 0x11820000 0 0x10000>,
+			      <0 0x11830000 0 0x10000>;
+			interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "error",
+					  "ch0", "ch1", "ch2", "ch3",
+					  "ch4", "ch5", "ch6", "ch7",
+					  "ch8", "ch9", "ch10", "ch11",
+					  "ch12", "ch13", "ch14", "ch15";
+			clocks = <&cpg CPG_MOD R9A07G043U_DMAC_ACLK>,
+				 <&cpg CPG_MOD R9A07G043U_DMAC_PCLK>;
+			power-domains = <&cpg>;
+			resets = <&cpg R9A07G043U_DMAC_ARESETN>,
+				 <&cpg R9A07G043U_DMAC_RST_ASYNC>;
+			#dma-cells = <1>;
+			dma-channels = <16>;
+		};
+
+		gic: interrupt-controller@11900000 {
+			compatible = "arm,gic-v3";
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+			interrupt-controller;
+			reg = <0x0 0x11900000 0 0x40000>,
+			      <0x0 0x11940000 0 0x60000>;
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+		};
+
+		sdhi0: mmc@11c00000  {
+			reg = <0x0 0x11c00000 0 0x10000>;
+			/* place holder */
+		};
+
+		sdhi1: mmc@11c10000 {
+			reg = <0x0 0x11c10000 0 0x10000>;
+			/* place holder */
+		};
+
+		phyrst: usbphy-ctrl@11c40000 {
+			reg = <0 0x11c40000 0 0x10000>;
+			/* place holder */
+		};
+
+		ohci0: usb@11c50000 {
+			reg = <0 0x11c50000 0 0x100>;
+			/* place holder */
+		};
+
+		ohci1: usb@11c70000 {
+			reg = <0 0x11c70000 0 0x100>;
+			/* place holder */
+		};
+
+		ehci0: usb@11c50100 {
+			reg = <0 0x11c50100 0 0x100>;
+			/* place holder */
+		};
+
+		ehci1: usb@11c70100 {
+			reg = <0 0x11c70100 0 0x100>;
+			/* place holder */
+		};
+
+		usb2_phy0: usb-phy@11c50200 {
+			reg = <0 0x11c50200 0 0x700>;
+			/* place holder */
+		};
+
+		usb2_phy1: usb-phy@11c70200 {
+			reg = <0 0x11c70200 0 0x700>;
+			/* place holder */
+		};
+
+		hsusb: usb@11c60000 {
+			reg = <0 0x11c60000 0 0x10000>;
+			/* place holder */
+		};
+
+		wdt0: watchdog@12800800 {
+			reg = <0 0x12800800 0 0x400>;
+			/* place holder */
+		};
+
+		wdt2: watchdog@12800400 {
+			reg = <0 0x12800400 0 0x400>;
+			/* place holder */
+		};
+
+		ostm0: timer@12801000 {
+			reg = <0x0 0x12801000 0x0 0x400>;
+			/* place holder */
+		};
+
+		ostm1: timer@12801400 {
+			reg = <0x0 0x12801400 0x0 0x400>;
+			/* place holder */
+		};
+
+		ostm2: timer@12801800 {
+			reg = <0x0 0x12801800 0x0 0x400>;
+			/* place holder */
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+};
-- 
2.17.1

[PATCH V2 7/7] arm64: dts: renesas: Add initial device tree for RZ/G2UL Type-1 SMARC EVK

[Biju Das]

Add basic support for RZ/G2UL SMARC EVK (based on R9A07G043U11):
- memory
- External input clock
- CPG
- DMA
- SCIF

It shares the same carrier board with RZ/G2L, but the pin mapping is
different. Disable the device nodes which are not tested and delete the
corresponding pinctrl definitions.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2:
 * Changed soc compatible from r9a07g043u->r9a07g043.
---
 arch/arm64/boot/dts/renesas/Makefile          |   2 +
 .../boot/dts/renesas/r9a07g043u11-smarc.dts   | 111 ++++++++++++++++++
 .../boot/dts/renesas/rzg2ul-smarc-som.dtsi    |  25 ++++
 3 files changed, 138 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts
 create mode 100644 arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi

diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index d000f6b131dc..a1217df9cd10 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -75,6 +75,8 @@ dtb-$(CONFIG_ARCH_R8A77961) += r8a779m3-ulcb-kf.dtb
 
 dtb-$(CONFIG_ARCH_R8A77965) += r8a779m5-salvator-xs.dtb
 
+dtb-$(CONFIG_ARCH_R9A07G043U) += r9a07g043u11-smarc.dtb
+
 dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc.dtb
 dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb
 
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts
new file mode 100644
index 000000000000..762bf26d679b
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2UL Type-1 SMARC EVK board
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r9a07g043u.dtsi"
+#include "rzg2ul-smarc-som.dtsi"
+#include "rz-smarc-common.dtsi"
+
+/ {
+	model = "Renesas SMARC EVK based on r9a07g043u11";
+	compatible = "renesas,smarc-evk", "renesas,r9a07g043u11", "renesas,r9a07g043";
+};
+
+&canfd {
+	/delete-property/ pinctrl-0;
+	/delete-property/ pinctrl-names;
+	status = "disabled";
+};
+
+&ehci0 {
+	/delete-property/ pinctrl-0;
+	/delete-property/ pinctrl-names;
+	status = "disabled";
+};
+
+&ehci1 {
+	/delete-property/ pinctrl-0;
+	/delete-property/ pinctrl-names;
+	status = "disabled";
+};
+
+&hsusb {
+	/delete-property/ pinctrl-0;
+	/delete-property/ pinctrl-names;
+	status = "disabled";
+};
+
+&i2c0 {
+	/delete-property/ pinctrl-0;
+	/delete-property/ pinctrl-names;
+	status = "disabled";
+};
+
+&i2c1 {
+	/delete-property/ pinctrl-0;
+	/delete-property/ pinctrl-names;
+	status = "disabled";
+
+	wm8978: codec@1a {
+		compatible = "wlf,wm8978";
+		#sound-dai-cells = <0>;
+		reg = <0x1a>;
+	};
+};
+
+&ohci0 {
+	/delete-property/ pinctrl-0;
+	/delete-property/ pinctrl-names;
+	status = "disabled";
+};
+
+&ohci1 {
+	/delete-property/ pinctrl-0;
+	/delete-property/ pinctrl-names;
+	status = "disabled";
+};
+
+&phyrst {
+	status = "disabled";
+};
+
+&scif0 {
+	/delete-property/ pinctrl-0;
+	/delete-property/ pinctrl-names;
+};
+
+&sdhi1 {
+	/delete-property/ pinctrl-0;
+	/delete-property/ pinctrl-1;
+	/delete-property/ pinctrl-names;
+	/delete-property/ vmmc-supply;
+	status = "disabled";
+};
+
+&spi1 {
+	/delete-property/ pinctrl-0;
+	/delete-property/ pinctrl-names;
+	status = "disabled";
+};
+
+&ssi0 {
+	/delete-property/ pinctrl-0;
+	/delete-property/ pinctrl-names;
+	status = "disabled";
+};
+
+&usb2_phy0 {
+	/delete-property/ pinctrl-0;
+	/delete-property/ pinctrl-names;
+	status = "disabled";
+};
+
+&usb2_phy1 {
+	/delete-property/ pinctrl-0;
+	/delete-property/ pinctrl-names;
+	status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
new file mode 100644
index 000000000000..3bbb8fcd604c
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2UL SMARC SOM common parts
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+
+/ {
+	chosen {
+		bootargs = "ignore_loglevel";
+	};
+
+	memory@48000000 {
+		device_type = "memory";
+		/* first 128MB is reserved for secure area. */
+		reg = <0x0 0x48000000 0x0 0x38000000>;
+	};
+};
+
+&extal_clk {
+	clock-frequency = <24000000>;
+};
-- 
2.17.1

Re: [PATCH V2 3/7] dt-bindings: clock: Add R9A07G043U CPG Clock and Reset Definitions

[Geert Uytterhoeven]

Hi Biju,

On Thu, Mar 3, 2022 at 5:26 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Define RZ/G2UL (R9A07G043U) Clock Pulse Generator Core Clock and module
> clock outputs, as listed in Table 7.1.4.2 ("Clock List r0.51") and also
> add Reset definitions referring to registers CPG_RST_* in Section 7.2.3
> ("Register configuration") of the RZ/G2UL Hardware User's Manual (Rev.
> 0.51, Nov. 2021).
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Thanks for your patch!

> --- /dev/null
> +++ b/include/dt-bindings/clock/r9a07g043u-cpg.h
> @@ -0,0 +1,186 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> + *
> + * Copyright (C) 2022 Renesas Electronics Corp.
> + */
> +#ifndef __DT_BINDINGS_CLOCK_R9A07G043U_CPG_H__
> +#define __DT_BINDINGS_CLOCK_R9A07G043U_CPG_H__
> +
> +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> +
> +/* R9A07G043U CPG Core Clocks */
> +#define R9A07G043U_CLK_I               0

Likewise, please drop the trailing (upper/lower case) "u".

Unfortunately I cannot comment on the list of clocks, as I don't have
access to that part of the documentation yet.

I think it would be good to compare the RZ/G2UL and RZ/Five clock
lists, so we know if we can handle them in a common driver, possibly
even sharing binding definitions, or need to differentiate.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH V2 1/7] dt-bindings: power: renesas,rzg2l-sysc: Document RZ/G2UL SoC

[Rob Herring]

On Thu, 03 Mar 2022 16:26:28 +0000, Biju Das wrote:
> Add DT binding documentation for SYSC controller found on RZ/G2UL SoC's.
> SYSC controller found on the RZ/G2UL SoC is almost identical to one found
> on the RZ/G2L SoC's only difference being that the RZ/G2UL has only CA55
> core0 reset vector address configuration register.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> V1->V2:
>  * No change
> ---
>  .../devicetree/bindings/power/renesas,rzg2l-sysc.yaml | 11 ++++++-----
>  1 file changed, 6 insertions(+), 5 deletions(-)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

Re: [PATCH V2 4/7] dt-bindings: clock: renesas: Document RZ/G2UL SoC

[Rob Herring]

On Thu, 03 Mar 2022 16:26:31 +0000, Biju Das wrote:
> Document the device tree binding for the Renesas RZ/G2UL Type-1
> and Type-2 SoC. RZ/G2UL Type-2 has fewer clocks than RZ/G2UL Type-1
> SoC.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v1->v2:
>  * No change
> ---
>  .../devicetree/bindings/clock/renesas,rzg2l-cpg.yaml     | 9 +++++----
>  1 file changed, 5 insertions(+), 4 deletions(-)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

RE: [PATCH V2 3/7] dt-bindings: clock: Add R9A07G043U CPG Clock and Reset Definitions

[Biju Das]

Hi Geert,

Thanks for the feedback.

@bp.renesas.com>; Linux-
> Renesas <linux-renesas-soc@vger.kernel.org>
> Subject: Re: [PATCH V2 3/7] dt-bindings: clock: Add R9A07G043U CPG Clock
> and Reset Definitions
> 
> Hi Biju,
> 
> On Thu, Mar 3, 2022 at 5:26 PM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > Define RZ/G2UL (R9A07G043U) Clock Pulse Generator Core Clock and
> > module clock outputs, as listed in Table 7.1.4.2 ("Clock List r0.51")
> > and also add Reset definitions referring to registers CPG_RST_* in
> > Section 7.2.3 ("Register configuration") of the RZ/G2UL Hardware User's
> Manual (Rev.
> > 0.51, Nov. 2021).
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Thanks for your patch!
> 
> > --- /dev/null
> > +++ b/include/dt-bindings/clock/r9a07g043u-cpg.h
> > @@ -0,0 +1,186 @@
> > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > + *
> > + * Copyright (C) 2022 Renesas Electronics Corp.
> > + */
> > +#ifndef __DT_BINDINGS_CLOCK_R9A07G043U_CPG_H__
> > +#define __DT_BINDINGS_CLOCK_R9A07G043U_CPG_H__
> > +
> > +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> > +
> > +/* R9A07G043U CPG Core Clocks */
> > +#define R9A07G043U_CLK_I               0
> 
> Likewise, please drop the trailing (upper/lower case) "u".
> 
OK.

> Unfortunately I cannot comment on the list of clocks, as I don't have
> access to that part of the documentation yet.
> 
> I think it would be good to compare the RZ/G2UL and RZ/Five clock lists,
> so we know if we can handle them in a common driver, possibly even sharing
> binding definitions, or need to differentiate.
> 

OK, I will prepare the patch with 

1) Module Clocks/resets common to RZ/G2UL and RZ/Five
2) Module Clocks/resets specifics to RZ/G2UL

Later when we add RZ/Five, will add Module Clocks/resets specifics to RZ/Five.
Is it ok?

Cheers,
Biju