From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C332C433EF for ; Tue, 15 Mar 2022 16:19:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349970AbiCOQUM (ORCPT ); Tue, 15 Mar 2022 12:20:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46734 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242237AbiCOQUL (ORCPT ); Tue, 15 Mar 2022 12:20:11 -0400 Received: from mail-oi1-x232.google.com (mail-oi1-x232.google.com [IPv6:2607:f8b0:4864:20::232]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 168AD13D1C for ; Tue, 15 Mar 2022 09:18:56 -0700 (PDT) Received: by mail-oi1-x232.google.com with SMTP id o64so21342795oib.7 for ; Tue, 15 Mar 2022 09:18:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=Em5xMVZQLrR/NiGDTVcPyJrzArjc9v1y2RjbKDoAxeE=; b=r/KHFxIQ9cNwkwMWJ3NuTgoaVO3mOgYvQuaisHpfb+9E3mGbiubIEz2IVbo+LFoLtS op1qcF0AwXhIawa188FdjIDE26JCkFsJvex0bVM89bNv3ayaIjXwi7pTWODS0E7J0mda 2vwR43HJFUbRGC+HoEYnD1vRMUnyURRY1lUa04PAYjKuAv95jne7O8HeyDqvufZaoHcB WlxlQdC3WKzhNH8aOsAoWfPge6/uEAHRgbPdB7C3lFwJ+XlodgG6KEWpl/UZJ4FDLBEI mXdnmzJuBtLtiH2XvtXl/dIuib00ZJBPojHDsd7YjmhTEyhpb9O2MugMyXeAXpN4rxfS 4gBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=Em5xMVZQLrR/NiGDTVcPyJrzArjc9v1y2RjbKDoAxeE=; b=zF9Myn4hCcmIsodOvrtf5qmnJxv91g0mEszJB+5ZOlFEn8DCjsPZh2JAYVy61jY4k8 VeYWpAWoEiDLPy2AcIfb490fiSuo4bC5PCJLj0jF0lEPkzG6IdyiTdEgCfBiCdKttOls 71Td3gMtrC3ARseZX6YGvbrCrZz61SKNxKw+KD+aMZPwZ6sMzQ1G3pcQ2WHy3m9oMPCj ISSnUrhXVGOWCl0aCmkqibAYkDn8S2H0altrNTNs4BytfxQr+ltMh4r1BkV59F662M0p jfvv9aFYe5zxClIPkew7cqwGdFWuDtaoNpLUQYBfvkmVPgRvvzLj48OqhrK48436AIOW teKw== X-Gm-Message-State: AOAM531ZuWhh+0+hb92uqS04/ax1KptqOAdmQH7Bf1ebgw4ObTn5WdNW E5xNMwxdwG2BELEKDu7ghI5I9w== X-Google-Smtp-Source: ABdhPJyhH0FJKDNG5YJgwlpKc0zXAThsoAg9TgnVRbKIaK5fAgXk6gNRuZtozK0JSwjPv6FTm8Frgg== X-Received: by 2002:aca:2110:0:b0:2ec:b1cf:2dda with SMTP id 16-20020aca2110000000b002ecb1cf2ddamr2105902oiz.143.1647361135489; Tue, 15 Mar 2022 09:18:55 -0700 (PDT) Received: from builder.lan ([2600:1700:a0:3dc8:3697:f6ff:fe85:aac9]) by smtp.gmail.com with ESMTPSA id 37-20020a9d0328000000b005b2265711fcsm9276523otv.16.2022.03.15.09.18.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Mar 2022 09:18:54 -0700 (PDT) Date: Tue, 15 Mar 2022 11:18:53 -0500 From: Bjorn Andersson To: Bhupesh Sharma Cc: linux-arm-msm@vger.kernel.org, bhupesh.linux@gmail.com, agross@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, maz@kernel.org, quic_mkshah@quicinc.com, linux-gpio@vger.kernel.org, linus.walleij@linaro.org, robh+dt@kernel.org, Vinod Koul , Rob Herring Subject: Re: [PATCH v2 3/4] arm64: dts: qcom: sm8150: Add pdc interrupt controller node Message-ID: References: <20220226184028.111566-1-bhupesh.sharma@linaro.org> <20220226184028.111566-4-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220226184028.111566-4-bhupesh.sharma@linaro.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Sat 26 Feb 12:40 CST 2022, Bhupesh Sharma wrote: > Add pdc interrupt controller for sm8150. > > Cc: Maulik Shah > Cc: Bjorn Andersson > Cc: Vinod Koul > Cc: Rob Herring > Signed-off-by: Bhupesh Sharma > --- > arch/arm64/boot/dts/qcom/sm8150.dtsi | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi > index 6012322a5984..aaeacd379460 100644 > --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi > @@ -1626,6 +1626,16 @@ system-cache-controller@9200000 { > interrupts = ; > }; > > + pdc: interrupt-controller@b220000 { > + compatible = "qcom,sm8150-pdc", "qcom,pdc"; > + reg = <0 0x0b220000 0 0x400>; > + qcom,pdc-ranges = <0 480 94>, <94 609 31>, > + <125 63 1>; When I look at the platform documentation I get the impression that this should be: <0 480 94>, <94 609 32>; Can you confirm that the last signal is correctly described? Regards, Bjorn > + #interrupt-cells = <2>; > + interrupt-parent = <&intc>; > + interrupt-controller; > + }; > + > ufs_mem_hc: ufshc@1d84000 { > compatible = "qcom,sm8150-ufshc", "qcom,ufshc", > "jedec,ufs-2.0"; > -- > 2.35.1 >