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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id w8-20020a056830410800b005b25e8430basm8054284ott.6.2022.03.21.16.44.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Mar 2022 16:44:43 -0700 (PDT) Received: (nullmailer pid 766907 invoked by uid 1000); Mon, 21 Mar 2022 23:44:42 -0000 Date: Mon, 21 Mar 2022 18:44:42 -0500 From: Rob Herring To: Radhey Shyam Pandey Cc: Andy Chiu , "robert.hancock@calian.com" , Michal Simek , "davem@davemloft.net" , "kuba@kernel.org" , "pabeni@redhat.com" , "linux@armlinux.org.uk" , "andrew@lunn.ch" , "netdev@vger.kernel.org" , "devicetree@vger.kernel.org" , Greentime Hu , Harini Katakam Subject: Re: [PATCH v4 3/4] dt-bindings: net: xilinx_axienet: add pcs-handle attribute Message-ID: References: <20220321152515.287119-1-andy.chiu@sifive.com> <20220321152515.287119-3-andy.chiu@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Mon, Mar 21, 2022 at 03:42:52PM +0000, Radhey Shyam Pandey wrote: > > -----Original Message----- > > From: Andy Chiu > > Sent: Monday, March 21, 2022 8:55 PM > > To: Radhey Shyam Pandey ; robert.hancock@calian.com; > > Michal Simek > > Cc: davem@davemloft.net; kuba@kernel.org; pabeni@redhat.com; > > robh+dt@kernel.org; linux@armlinux.org.uk; andrew@lunn.ch; > > netdev@vger.kernel.org; devicetree@vger.kernel.org; Andy Chiu > > ; Greentime Hu > > Subject: [PATCH v4 3/4] dt-bindings: net: xilinx_axienet: add pcs-handle > > attribute > > > > Document the new pcs-handle attribute to support connecting to an external > > PHY in SGMII or 1000Base-X modes through the internal PCS/PMA PHY. > > > > Signed-off-by: Andy Chiu > > Reviewed-by: Greentime Hu > > --- > > Documentation/devicetree/bindings/net/xilinx_axienet.txt | 8 +++++++- > > 1 file changed, 7 insertions(+), 1 deletion(-) > > > > diff --git a/Documentation/devicetree/bindings/net/xilinx_axienet.txt > > b/Documentation/devicetree/bindings/net/xilinx_axienet.txt > > index b8e4894bc634..ba720a2ea5fc 100644 > > --- a/Documentation/devicetree/bindings/net/xilinx_axienet.txt > > +++ b/Documentation/devicetree/bindings/net/xilinx_axienet.txt > > @@ -26,7 +26,8 @@ Required properties: > > specified, the TX/RX DMA interrupts should be on that node > > instead, and only the Ethernet core interrupt is optionally > > specified here. > > -- phy-handle : Should point to the external phy device. > > +- phy-handle : Should point to the external phy device if exists. Pointing > > + this to the PCS/PMA PHY is deprecated and should be > > avoided. > > See ethernet.txt file in the same directory. > > - xlnx,rxmem : Set to allocated memory buffer for Rx/Tx in the hardware > > > > @@ -68,6 +69,11 @@ Optional properties: > > required through the core's MDIO interface (i.e. always, > > unless the PHY is accessed through a different bus). > > > > + - pcs-handle: Phandle to the internal PCS/PMA PHY in SGMII or 1000Base-X > > + modes, where "pcs-handle" should be preferably used to > > point > > + to the PCS/PMA PHY, and "phy-handle" should point to an > > + external PHY if exists. > > I would like to have Rob feedback on this pcs-handle DT property. > > The use case is generic i.e. require separate handle to internal SGMII > and external Phy so would prefer this new DT convention is > standardized or we discuss possible approaches on how to handle > both phys and not add it as vendor specific property in the first > place. IMO, you should use 'phys' for the internal PCS phy. That's aligned with other uses like PCIe, SATA, etc. (there is phy h/w that will do PCS, PCIe, SATA). 'phy-handle' is for the ethernet PHY. Rob