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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id 15-20020a056870118f00b000de58283559sm273166oau.36.2022.03.23.11.17.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Mar 2022 11:17:24 -0700 (PDT) Received: (nullmailer pid 196157 invoked by uid 1000); Wed, 23 Mar 2022 18:17:23 -0000 Date: Wed, 23 Mar 2022 13:17:23 -0500 From: Rob Herring To: Biju Das Cc: David Airlie , Daniel Vetter , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, Geert Uytterhoeven , Chris Paterson , Biju Das , Prabhakar Mahadev Lad , linux-renesas-soc@vger.kernel.org Subject: Re: [PATCH 1/2] dt-bindings: display: bridge: Document RZ/G2L MIPI DSI TX bindings Message-ID: References: <20220314161004.14765-1-biju.das.jz@bp.renesas.com> <20220314161004.14765-2-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220314161004.14765-2-biju.das.jz@bp.renesas.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Mon, Mar 14, 2022 at 04:10:02PM +0000, Biju Das wrote: > The RZ/G2L MIPI DSI TX is embedded in the Renesas RZ/G2L family SoC's. It > can operate in DSI mode, with up to four data lanes. > > Signed-off-by: Biju Das > --- > RFC->v1: > * Added a ref to dsi-controller.yaml. > RFC:- > * https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-22-biju.das.jz@bp.renesas.com/ > --- > .../bindings/display/bridge/renesas,dsi.yaml | 146 ++++++++++++++++++ > 1 file changed, 146 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml > > diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml > new file mode 100644 > index 000000000000..74bc3782d230 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml > @@ -0,0 +1,146 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/bridge/renesas,dsi.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Renesas RZ/G2L MIPI DSI Encoder > + > +maintainers: > + - Biju Das > + > +description: | > + This binding describes the MIPI DSI encoder embedded in the Renesas > + RZ/G2L family of SoC's. The encoder can operate in DSI mode with up > + to four data lanes. > + > +allOf: > + - $ref: ../dsi-controller.yaml# Full path preferred: /schemas/display/dsi-controller.yaml# > + > +properties: > + compatible: > + enum: > + - renesas,rzg2l-mipi-dsi # RZ/G2L and RZ/V2L > + > + reg: > + items: > + - description: Link register > + - description: D-PHY register D-PHY is not a separate block? > + > + clocks: > + items: > + - description: DSI D-PHY PLL multiplied clock > + - description: DSI D-PHY system clock > + - description: DSI AXI bus clock > + - description: DSI Register access clock > + - description: DSI Video clock > + - description: DSI D_PHY Escape mode Receive clock D-PHY > + > + clock-names: > + items: > + - const: pllclk > + - const: sysclk > + - const: aclk > + - const: pclk > + - const: vclk > + - const: lpclk > + > + power-domains: > + maxItems: 1 > + > + resets: > + items: > + - description: MIPI_DSI_CMN_RSTB > + - description: MIPI_DSI_ARESET_N > + - description: MIPI_DSI_PRESET_N > + > + reset-names: > + items: > + - const: rst > + - const: arst > + - const: prst > + > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + > + properties: > + port@0: > + $ref: /schemas/graph.yaml#/properties/port > + description: Parallel input port > + > + port@1: > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + description: DSI output port > + > + properties: > + endpoint: > + $ref: /schemas/media/video-interfaces.yaml# > + unevaluatedProperties: false > + > + properties: > + data-lanes: > + minItems: 1 > + maxItems: 4 > + > + required: > + - data-lanes > + > + required: > + - port@0 > + - port@1 > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - power-domains > + - resets > + - reset-names > + - ports > + > +additionalProperties: false > + > +examples: > + - | > + #include > + > + dsi0: dsi@10860000 { > + compatible = "renesas,rzg2l-mipi-dsi"; > + reg = <0x10860000 0x10000>, > + <0x10850000 0x10000>; > + power-domains = <&cpg>; > + clocks = <&cpg CPG_MOD R9A07G044_MIPI_DSI_PLLCLK>, > + <&cpg CPG_MOD R9A07G044_MIPI_DSI_SYSCLK>, > + <&cpg CPG_MOD R9A07G044_MIPI_DSI_ACLK>, > + <&cpg CPG_MOD R9A07G044_MIPI_DSI_PCLK>, > + <&cpg CPG_MOD R9A07G044_MIPI_DSI_VCLK>, > + <&cpg CPG_MOD R9A07G044_MIPI_DSI_LPCLK>; > + clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk"; > + resets = <&cpg R9A07G044_MIPI_DSI_CMN_RSTB>, > + <&cpg R9A07G044_MIPI_DSI_ARESET_N>, > + <&cpg R9A07G044_MIPI_DSI_PRESET_N>; > + reset-names = "rst", "arst", "prst"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dsi0_in: endpoint { > + remote-endpoint = <&du_out_dsi0>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + dsi0_out: endpoint { > + data-lanes = <1 2 3 4>; > + remote-endpoint = <&adv7535_in>; > + }; > + }; > + }; > + }; > +... > -- > 2.17.1 > >