From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B53AC433F5 for ; Thu, 24 Mar 2022 22:19:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241989AbiCXWVK (ORCPT ); Thu, 24 Mar 2022 18:21:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33350 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242692AbiCXWVJ (ORCPT ); Thu, 24 Mar 2022 18:21:09 -0400 Received: from vps0.lunn.ch (vps0.lunn.ch [185.16.172.187]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D43818FE61 for ; Thu, 24 Mar 2022 15:19:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Disposition:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:From:Sender:Reply-To:Subject: Date:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding: Content-ID:Content-Description:Content-Disposition:In-Reply-To:References; bh=uIfPofyuq9jXCiykRc3r/F358w9m2+gmmcJgChLDMcM=; b=djg9eGvYk/K0/p61r7PkgDJa72 /o8Sai6SCbybHaem/4AvvP097eTdf15TxS8ktc63Nf1nSLvMbWbEfKgr0iWjP7hPtlyleOasmDUFO Trr2gi9oZ9WMov8BV0YEwrxyoOdM4DD4SynTuqOtLr/PErt+Ti2ttqTPeMkbd6beulcw=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1nXVnj-00CVzH-84; Thu, 24 Mar 2022 23:19:27 +0100 Date: Thu, 24 Mar 2022 23:19:27 +0100 From: Andrew Lunn To: Jae Hyun Yoo Cc: Rob Herring , Joel Stanley , Andrew Jeffery , Jamie Iles , Graeme Gregory , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org Subject: Re: [PATCH] ARM: dts: aspeed: add Nuvia DC-SCM BMC Message-ID: References: <20220324164551.359570-1-quic_jaehyoo@quicinc.com> <88849423-c4a5-0a68-1900-72196395704e@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <88849423-c4a5-0a68-1900-72196395704e@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Thu, Mar 24, 2022 at 02:27:34PM -0700, Jae Hyun Yoo wrote: > Hi Andrew, > > On 3/24/2022 2:23 PM, Andrew Lunn wrote: > > On Thu, Mar 24, 2022 at 09:45:51AM -0700, Jae Hyun Yoo wrote: > > > From: Graeme Gregory > > > > > > +&mac2 { > > > + status = "okay"; > > > + > > > + phy-mode = "rgmii"; > > > > Are you sure about this? That PHY are you using? It is more normal to > > use rgmii-id. > > Yes, I'm sure. PHY works with rgmii on my board. I picked a different > clock delay setting too. Do you know who is inserting the delay? It looks like rgmii will be passed to the PHY. So there are few possibilities here: The MAC is adding the delay. Not recommended, but does work. In that case, your DT is correct. The bootloader or strapping configures the PHY to insert the delay. The PHY driver then ignores 'rgmii' and leaves the configuration alone. This will break sometime in the future when somebody fixes the PHY driver to actually set the PHY to rgmii as requested. In this case, both the PHY driver and your DT is broken. The board itself inserts the delays by having long tracks. In this case, your DT is correct. It would be good to understand this, just in case it is the second condition. Andrew