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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id v24-20020a9d5a18000000b005ad458facbdsm11728168oth.27.2022.03.30.17.53.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Mar 2022 17:53:45 -0700 (PDT) Received: (nullmailer pid 3988522 invoked by uid 1000); Thu, 31 Mar 2022 00:53:44 -0000 Date: Wed, 30 Mar 2022 19:53:44 -0500 From: Rob Herring To: Sumit Gupta Cc: rafael@kernel.org, viresh.kumar@linaro.org, krzk+dt@kernel.org, treding@nvidia.com, jonathanh@nvidia.com, linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ksitaraman@nvidia.com, sanjayc@nvidia.com, bbasu@nvidia.com Subject: Re: [Patch v2 2/4] dt-bindings: arm: tegra: Add bindins for nvidia,tegra-ccplex-cluster Message-ID: References: <20220330143819.27476-1-sumitg@nvidia.com> <20220330143819.27476-3-sumitg@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220330143819.27476-3-sumitg@nvidia.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Wed, Mar 30, 2022 at 08:08:17PM +0530, Sumit Gupta wrote: > The Tegra CCPLEX_CLUSTER area contains memory-mapped > registers that initiate CPU frequency/voltage transitions. > > Signed-off-by: Sumit Gupta > --- > .../tegra/nvidia,tegra-ccplex-cluster.yaml | 52 +++++++++++++++++++ > 1 file changed, 52 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml > > diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml > new file mode 100644 > index 000000000000..74afa06f695e > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml > @@ -0,0 +1,52 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra-ccplex-cluster.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: NVIDIA Tegra CPU_CLUSTER area device tree bindings > + > +maintainers: > + - Sumit Gupta > + - Mikko Perttunen > + - Jon Hunter > + - Thierry Reding > + > +description: |+ > + The Tegra CCPLEX_CLUSTER area contains memory-mapped > + registers that initiate CPU frequency/voltage transitions. > + > +properties: > + $nodename: > + pattern: "ccplex@([0-9a-f]+)$" > + > + compatible: > + enum: > + - nvidia,tegra186-ccplex-cluster > + - nvidia,tegra234-ccplex-cluster > + > + reg: > + maxItems: 1 > + > + nvidia,bpmp: > + $ref: '/schemas/types.yaml#/definitions/phandle' > + description: | > + Specifies the bpmp node that needs to be queried to get > + operating point data for all CPUs. > + > +additionalProperties: true > + > +required: > + - compatible > + - reg > + - nvidia,bpmp > + - status status is never required. > + > +examples: > + - | > + ccplex@e000000 { > + compatible = "nvidia,tegra234-ccplex-cluster"; > + reg = <0x0 0x0e000000 0x0 0x5ffff>; > + nvidia,bpmp = <&bpmp>; > + status = "okay"; Nor should it be in examples. > + }; > -- > 2.17.1 > >