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From: Rob Herring <robh@kernel.org>
To: Sumit Gupta <sumitg@nvidia.com>
Cc: rafael@kernel.org, viresh.kumar@linaro.org, krzk+dt@kernel.org,
	treding@nvidia.com, jonathanh@nvidia.com,
	linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	ksitaraman@nvidia.com, sanjayc@nvidia.com, bbasu@nvidia.com
Subject: Re: [Patch v3 1/4] dt-bindings: Document Tegra CCPLEX Cluster
Date: Mon, 4 Apr 2022 11:21:05 -0500	[thread overview]
Message-ID: <Yksa8cvCvB2Zn7tn@robh.at.kernel.org> (raw)
In-Reply-To: <20220404121713.22461-2-sumitg@nvidia.com>

On Mon, Apr 04, 2022 at 05:47:10PM +0530, Sumit Gupta wrote:
> The Tegra CPU COMPLEX CLUSTER area contains memory-mapped
> registers that initiate CPU frequency/voltage transitions.
> 
> Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
> ---

Changes from v2? None perhaps because you ignored my comments there.

>  .../tegra/nvidia,tegra-ccplex-cluster.yaml    | 52 +++++++++++++++++++
>  1 file changed, 52 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml
> 
> diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml
> new file mode 100644
> index 000000000000..d89457e0bd7d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml
> @@ -0,0 +1,52 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra-ccplex-cluster.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: NVIDIA Tegra CPU COMPLEX CLUSTER area device tree bindings
> +
> +maintainers:
> +  - Sumit Gupta <sumitg@nvidia.com>
> +  - Mikko Perttunen <mperttunen@nvidia.com>
> +  - Jon Hunter <jonathanh@nvidia.com>
> +  - Thierry Reding <thierry.reding@gmail.com>
> +
> +description: |+
> +  The Tegra CPU COMPLEX CLUSTER area contains memory-mapped
> +  registers that initiate CPU frequency/voltage transitions.
> +
> +properties:
> +  $nodename:
> +    pattern: "ccplex@([0-9a-f]+)$"
> +
> +  compatible:
> +    enum:
> +      - nvidia,tegra186-ccplex-cluster
> +      - nvidia,tegra234-ccplex-cluster
> +
> +  reg:
> +    maxItems: 1
> +
> +  nvidia,bpmp:
> +    $ref: '/schemas/types.yaml#/definitions/phandle'
> +    description: |
> +      Specifies the BPMP node that needs to be queried to get
> +      operating point data for all CPUs.
> +
> +additionalProperties: true

Additionally, true is only allowed for incomplete, common bindings which 
this is not.

> +
> +required:
> +  - compatible
> +  - reg
> +  - nvidia,bpmp
> +  - status
> +
> +examples:
> +  - |
> +    ccplex@e000000 {
> +      compatible = "nvidia,tegra234-ccplex-cluster";
> +      reg = <0x0 0x0e000000 0x0 0x5ffff>;
> +      nvidia,bpmp = <&bpmp>;
> +      status = "okay";
> +    };
> -- 
> 2.17.1
> 
> 

  parent reply	other threads:[~2022-04-04 21:17 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-04 12:17 [Patch v3 0/4] Tegra234 cpufreq driver support Sumit Gupta
2022-04-04 12:17 ` [Patch v3 1/4] dt-bindings: Document Tegra CCPLEX Cluster Sumit Gupta
2022-04-04 16:08   ` Rob Herring
2022-04-05  8:16     ` Sumit Gupta
2022-04-04 16:21   ` Rob Herring [this message]
2022-04-05  8:20     ` Sumit Gupta
2022-04-04 12:17 ` [Patch v3 2/4] cpufreq: tegra194: add soc data to support multiple soc Sumit Gupta
2022-04-04 12:17 ` [Patch v3 3/4] cpufreq: tegra194: Add support for Tegra234 Sumit Gupta
2022-04-04 12:17 ` [Patch v3 4/4] arm64: tegra: add node for tegra234 cpufreq Sumit Gupta

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