From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5FB59C41535 for ; Tue, 5 Apr 2022 23:02:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1448608AbiDEWvL (ORCPT ); Tue, 5 Apr 2022 18:51:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34864 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1458173AbiDERNK (ORCPT ); Tue, 5 Apr 2022 13:13:10 -0400 Received: from mail-ot1-x32e.google.com (mail-ot1-x32e.google.com [IPv6:2607:f8b0:4864:20::32e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0540E52E2A for ; Tue, 5 Apr 2022 10:11:10 -0700 (PDT) Received: by mail-ot1-x32e.google.com with SMTP id i11-20020a9d4a8b000000b005cda3b9754aso9782352otf.12 for ; Tue, 05 Apr 2022 10:11:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=2aY58p3Eu08i1zvroIKdthxIFG+lHzOcPDP1Vod5UdQ=; b=BJlLixmapZXG3Z12MRft8f1o+ERnrNsMEOuO+htxHtOkkXNoC4g+Fj1hvUrrz2eiR4 bbLh9uCYeNiIVW87oZB/Hf2zirGPhRhZs4MZFYQKP0lT5uFogrweIdBUU638/F+vk8MM 1XdUXhdAsAizdg4UAkuu6oeBzHDIdwhMxz+vGg+2NqOPoCUyUnwMUPKELdYC0y2EEVnx l302qabGpKEelNd6fdET2izAcrhjx6ZXdty+FKfxGQhRT1RWJZTm6vZ6qscVeEq76dyX QL55dLz7mFEFaoJpPbnuJnPj9hVDedGHH2VDGUnoO0snxp7Lh/xCE0QEunJnYaWLh0gi 0wsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=2aY58p3Eu08i1zvroIKdthxIFG+lHzOcPDP1Vod5UdQ=; b=z+LMUk3+qzMMnq5wAvhI+HkRrHM7hL1giJcfBm+a2JdjBqaJ22bIBAT2fd1NAuGH+S fWrX2blcRr/vKzYKsKPhne4N5tvPUSsOzWeonsxC0RQAnoEA2sEtxQn4cBQWYFzpY4r9 Mwu5gm8+UnjNcxqw9gKeYLEat7bSFR/hxkTgJp3+K44qbsfx75UpbmeKm2KptNyaOZd+ USJICVCeRzamVfqnB+84eA8/O+pbQHwuUtItdkHb/Rn5cAe8llZZW8iZK+g2EfK19Q1H 6BisbroAdwKbnd3F2fp5YSY6kvxizw2I7i4+QH1rdfgyWaHfyfjm2cAvD3loOsU+4Tn1 8+bQ== X-Gm-Message-State: AOAM530vgqNfAdCyaZs5Ie0fmkqBcVAiSeoHJJGjvZMxloUiJXWV9Yyl ZDGnHGYcKUvgvaf6RJbmiIVq4w== X-Google-Smtp-Source: ABdhPJw3Dog+Ye6joupCF1nJ1gu6mLF/8uu2LULDI3pj1f67IYGzNXfMwLJXsBStJIdXMshXWyQ+wg== X-Received: by 2002:a9d:6442:0:b0:5b2:3851:597 with SMTP id m2-20020a9d6442000000b005b238510597mr1566869otl.247.1649178669314; Tue, 05 Apr 2022 10:11:09 -0700 (PDT) Received: from ripper ([2600:1700:a0:3dc8:205:1bff:fec0:b9b3]) by smtp.gmail.com with ESMTPSA id e4-20020a056808148400b002d9be41b179sm5680214oiw.50.2022.04.05.10.11.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Apr 2022 10:11:08 -0700 (PDT) Date: Tue, 5 Apr 2022 10:13:31 -0700 From: Bjorn Andersson To: Dmitry Baryshkov Cc: Krzysztof Kozlowski , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Alim Akhtar , Avri Altman , "James E.J. Bottomley" , "Martin K. Petersen" , Bean Huo , Bart Van Assche , Srinivas Kandagatla , Taniya Das , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org Subject: Re: [RFC PATCH 3/4] arm64: dts: qcom: sdm845: control RPMHPD performance states with UFS Message-ID: References: <20220401145820.1003826-1-krzysztof.kozlowski@linaro.org> <20220401145820.1003826-4-krzysztof.kozlowski@linaro.org> <0da0b229-3493-967d-c14d-60d3246b07b2@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <0da0b229-3493-967d-c14d-60d3246b07b2@linaro.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Sun 03 Apr 17:02 PDT 2022, Dmitry Baryshkov wrote: > On 01/04/2022 17:58, Krzysztof Kozlowski wrote: > > UFS, when scaling gears, should choose appropriate performance state of > > RPMHPD power domain controller. Since UFS belongs to UFS_PHY_GDSC power > > domain, add necessary parent power domain to GCC. > > This will cause all gcc GDSCs to be rooted in the CX. Are we sure that this > is an expected (and correct) change? > Per the last part of Rajendra's reply in [1], this should be fine. Naturally we might have to come up with some way to bind gdscs to one of multiple power-domains if that changes. [1] https://lore.kernel.org/all/5e572c50-d6fe-5a21-d09f-f11a072538c5@codeaurora.org/ Regards, Bjorn > > > > Signed-off-by: Krzysztof Kozlowski > > --- > > arch/arm64/boot/dts/qcom/sdm845.dtsi | 17 ++++++++++++++++- > > 1 file changed, 16 insertions(+), 1 deletion(-) > > > > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi > > index b31bf62e8680..c999b41c2605 100644 > > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi > > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi > > @@ -1078,6 +1078,7 @@ gcc: clock-controller@100000 { > > #clock-cells = <1>; > > #reset-cells = <1>; > > #power-domain-cells = <1>; > > + power-domains = <&rpmhpd SDM845_CX>; > > }; > > qfprom@784000 { > > @@ -2336,8 +2337,22 @@ ufs_mem_hc: ufshc@1d84000 { > > <0 0>, > > <0 0>, > > <0 300000000>; > > - > > + operating-points-v2 = <&ufs_opp_table>; > > status = "disabled"; > > + > > + ufs_opp_table: opp-table { > > + compatible = "operating-points-v2"; > > + > > + opp-50000000 { > > + opp-hz = /bits/ 64 <50000000>; > > + required-opps = <&rpmhpd_opp_svs>; > > + }; > > + > > + opp-200000000 { > > + opp-hz = /bits/ 64 <200000000>; > > + required-opps = <&rpmhpd_opp_nom>; > > + }; > > + }; > > }; > > ufs_mem_phy: phy@1d87000 { > > > -- > With best wishes > Dmitry