From: Rob Herring <robh@kernel.org>
To: Niklas Cassel <niklas.cassel@wdc.com>
Cc: Albert Ou <aou@eecs.berkeley.edu>,
Palmer Dabbelt <palmer@dabbelt.com>,
devicetree@vger.kernel.org,
Paul Walmsley <paul.walmsley@sifive.com>,
linux-riscv@lists.infradead.org,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Subject: Re: [PATCH] dt-bindings: riscv: Add mmu-type riscv,sv57
Date: Tue, 19 Apr 2022 13:15:05 -0500 [thread overview]
Message-ID: <Yl78KUfJcu40U5Fj@robh.at.kernel.org> (raw)
In-Reply-To: <20220414151639.1359969-1-niklas.cassel@wdc.com>
On Thu, 14 Apr 2022 17:16:38 +0200, Niklas Cassel wrote:
> sv57 is defined in the RISC-V Privileged Specification document.
>
> Additionally, commit 011f09d12052 ("riscv: mm: Set sv57 on defaultly")
> changed the default MMU mode to sv57, if supported by current hardware.
>
> Add riscv,sv57 to the list of valid mmu-type values.
>
> Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
prev parent reply other threads:[~2022-04-19 18:23 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-14 15:16 [PATCH] dt-bindings: riscv: Add mmu-type riscv,sv57 Niklas Cassel
2022-04-14 15:39 ` Niklas Cassel
2022-04-19 18:15 ` Rob Herring [this message]
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