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Mon, 11 Apr 2022 19:06:24 -0700 (PDT) Received: from builder.lan ([2600:1700:a0:3dc8:3697:f6ff:fe85:aac9]) by smtp.gmail.com with ESMTPSA id x20-20020a4ac594000000b00329a02f2f34sm4925186oop.16.2022.04.11.19.06.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Apr 2022 19:06:23 -0700 (PDT) Date: Mon, 11 Apr 2022 21:06:22 -0500 From: Bjorn Andersson To: Bryan O'Donoghue Cc: agross@kernel.org, robh+dt@kernel.org, krzk+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dmitry.baryshkov@linaro.org, jonathan@marek.ca, hfink@snap.com, jgrahsl@snap.com Subject: Re: [PATCH 4/4] arm64: dts: qcom: sm8250: camss: Add CCI definitions Message-ID: References: <20220409164556.2832782-1-bryan.odonoghue@linaro.org> <20220409164556.2832782-5-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220409164556.2832782-5-bryan.odonoghue@linaro.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Sat 09 Apr 11:45 CDT 2022, Bryan O'Donoghue wrote: > sm8250 has two CCI busses with two I2C busses apiece. > > Co-developed-by: Julian Grahsl > Signed-off-by: Julian Grahsl > Signed-off-by: Bryan O'Donoghue > --- > arch/arm64/boot/dts/qcom/sm8250.dtsi | 82 ++++++++++++++++++++++++++++ > 1 file changed, 82 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi > index 91ed079edbf7..98e96527702b 100644 > --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi > @@ -3150,6 +3150,88 @@ videocc: clock-controller@abf0000 { > #power-domain-cells = <1>; > }; > > + cci0: cci@ac4f000 { > + compatible = "qcom,sm8250-cci"; > + #address-cells = <1>; > + #size-cells = <0>; > + > + reg = <0 0x0ac4f000 0 0x1000>; > + interrupts = ; > + power-domains = <&camcc TITAN_TOP_GDSC>; > + > + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, > + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, > + <&camcc CAM_CC_CPAS_AHB_CLK>, > + <&camcc CAM_CC_CCI_0_CLK>, > + <&camcc CAM_CC_CCI_0_CLK_SRC>; > + clock-names = "camnoc_axi", > + "slow_ahb_src", > + "cpas_ahb", > + "cci", > + "cci_src"; > + > + pinctrl-names = "default", "sleep"; > + pinctrl-0 = <&cci0_default &cci1_default>; > + pinctrl-1 = <&cci0_sleep &cci1_sleep>; I would prefer that you include these in the same patch. > + > + status = "disabled"; > + > + cci_i2c0: i2c-bus@0 { > + reg = <0>; > + clock-frequency = <1000000>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + cci_i2c1: i2c-bus@1 { > + reg = <1>; > + clock-frequency = <1000000>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + }; > + > + cci1: cci@ac50000 { > + compatible = "qcom,sm8250-cci"; > + #address-cells = <1>; > + #size-cells = <0>; > + > + reg = <0 0x0ac50000 0 0x1000>; > + interrupts = ; > + power-domains = <&camcc TITAN_TOP_GDSC>; > + > + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, > + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, > + <&camcc CAM_CC_CPAS_AHB_CLK>, > + <&camcc CAM_CC_CCI_1_CLK>, > + <&camcc CAM_CC_CCI_1_CLK_SRC>; > + clock-names = "camnoc_axi", > + "slow_ahb_src", > + "cpas_ahb", > + "cci", > + "cci_src"; > + > + pinctrl-names = "default", "sleep"; > + pinctrl-0 = <&cci2_default &cci3_default>; > + pinctrl-1 = <&cci2_sleep &cci3_sleep>; > + > + status = "disabled"; > + > + cci_i2c2: i2c-bus@0 { Are these names (the label) used somewhere in the schematics? How about cci0_i2c0 and cci1_i2c0 instead (unless these names are defined by some documentation)? Regards, Bjorn > + reg = <0>; > + clock-frequency = <1000000>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + cci_i2c3: i2c-bus@1 { > + reg = <1>; > + clock-frequency = <1000000>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + }; > + > camss: camss@ac6a000 { > compatible = "qcom,sm8250-camss"; > status = "disabled"; > -- > 2.35.1 >