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From: Vinod Koul <vkoul@kernel.org>
To: Liu Ying <victor.liu@nxp.com>
Cc: linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org,
	linux-arm-kernel@lists.infradead.org, kishon@ti.com,
	robh+dt@kernel.org, andrzej.hajda@intel.com,
	narmstrong@baylibre.com, Laurent.pinchart@ideasonboard.com,
	jonas@kwiboo.se, jernej.skrabec@gmail.com, airlied@linux.ie,
	daniel@ffwll.ch, shawnguo@kernel.org, s.hauer@pengutronix.de,
	kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com,
	agx@sigxcpu.org, robert.chiras@nxp.com,
	martin.kepplinger@puri.sm, robert.foss@linaro.org
Subject: Re: [PATCH v6 resend 2/5] phy: Add LVDS configuration options
Date: Thu, 14 Apr 2022 11:07:44 +0530	[thread overview]
Message-ID: <YlezKAw+W8HOa322@matsya> (raw)
In-Reply-To: <a2731b2d77f9bf2adf36f0c05cb5e3b14a5a91a9.camel@nxp.com>

On 13-04-22, 20:39, Liu Ying wrote:
> On Wed, 2022-04-13 at 16:19 +0530, Vinod Koul wrote:
> > On 13-04-22, 18:04, Liu Ying wrote:
> > > Hi Vinod,
> > > 
> > > On Wed, 2022-04-13 at 11:41 +0530, Vinod Koul wrote:
> > > > On 02-04-22, 13:24, Liu Ying wrote:
> > > > > This patch allows LVDS PHYs to be configured through
> > > > > the generic functions and through a custom structure
> > > > > added to the generic union.
> > > > > 
> > > > > The parameters added here are based on common LVDS PHY
> > > > > implementation practices.  The set of parameters
> > > > > should cover all potential users.
> > > > > 
> > > > > Cc: Kishon Vijay Abraham I <kishon@ti.com>
> > > > > Cc: Vinod Koul <vkoul@kernel.org>
> > > > > Cc: NXP Linux Team <linux-imx@nxp.com>
> > > > > Signed-off-by: Liu Ying <victor.liu@nxp.com>
> > > > > ---
> 
> [...]
> 
> > > > > + */
> > > > > +
> > > > > +#ifndef __PHY_LVDS_H_
> > > > > +#define __PHY_LVDS_H_
> > > > > +
> > > > > +/**
> > > > > + * struct phy_configure_opts_lvds - LVDS configuration set
> > > > > + * @bits_per_lane_and_dclk_cycle:	Number of bits per data
> > > > > lane
> > > > > and
> > > > > + *					differential clock
> > > > > cycle.
> > > > 
> > > > What does it mean by bits per data lane and differential clock
> > > > cycle?
> > > 
> > > Please check
> > > Documentation/devicetree/bindings/display/panel/lvds.yaml.
> > > lvds.yaml metions slot.  'bits_per_lane_and_dclk_cycle' means the
> > > number of slots.  But, I don't find the word 'slot' in my lvds
> > > relevant
> > > specs which mentioned in lvds.yaml, so 'slots' is probably not a
> > > generic name(lvds.yaml is for display panel).  So, I use
> > > 'bits_per_lane_and_dclk_cycle' as the name tells what it means.
> > 
> > variable name is fine, explanation for bit per lane and differential
> > clock cycle didnt help, maybe add better explanation of what this
> > variable means
> 
> I may add an example diagram as below...

Not really a diagram, you can add if you like.. But something which
explains in a sentence or few about the variable.

bits per lane per differential clock cycle ?

-- 
~Vinod

  reply	other threads:[~2022-04-14  5:37 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-02  5:24 [PATCH v6 0/5] phy: phy-fsl-imx8-mipi-dphy: Add i.MX8qxp LVDS PHY mode support Liu Ying
2022-04-02  5:24 ` [PATCH v6 resend 1/5] drm/bridge: nwl-dsi: Set PHY mode in nwl_dsi_mode_set() Liu Ying
2022-04-02  5:24 ` [PATCH v6 resend 2/5] phy: Add LVDS configuration options Liu Ying
2022-04-13  6:11   ` Vinod Koul
2022-04-13 10:04     ` Liu Ying
2022-04-13 10:49       ` Vinod Koul
2022-04-13 12:39         ` Liu Ying
2022-04-14  5:37           ` Vinod Koul [this message]
2022-04-14  6:35             ` Liu Ying
2022-04-02  5:24 ` [PATCH v6 resend 3/5] dt-bindings: phy: Convert mixel,mipi-dsi-phy to json-schema Liu Ying
2022-04-02  5:24 ` [PATCH v6 resend 4/5] dt-bindings: phy: mixel: mipi-dsi-phy: Add Mixel combo PHY support for i.MX8qxp Liu Ying
2022-04-02  5:24 ` [PATCH v6 resend 5/5] phy: freescale: phy-fsl-imx8-mipi-dphy: Add i.MX8qxp LVDS PHY mode support Liu Ying
2022-04-13  6:21   ` Vinod Koul
2022-04-13 10:16     ` Liu Ying

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