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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id r19-20020a056830121300b005cdb11a7b85sm301131otp.29.2022.04.14.11.20.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Apr 2022 11:20:50 -0700 (PDT) Received: (nullmailer pid 2387691 invoked by uid 1000); Thu, 14 Apr 2022 18:20:49 -0000 Date: Thu, 14 Apr 2022 13:20:49 -0500 From: Rob Herring To: Kartik Cc: daniel.lezcano@linaro.org, tglx@linutronix.de, krzk+dt@kernel.org, thierry.reding@gmail.com, jonathanh@nvidia.com, spujar@nvidia.com, akhilrajeev@nvidia.com, rgumasta@nvidia.com, pshete@nvidia.com, vidyas@nvidia.com, mperttunen@nvidia.com, mkumard@nvidia.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org Subject: Re: [PATCH 1/6] dt-bindings: timer: Add Tegra186 & Tegra234 Timer Message-ID: References: <1649924738-17990-1-git-send-email-kkartik@nvidia.com> <1649924738-17990-2-git-send-email-kkartik@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1649924738-17990-2-git-send-email-kkartik@nvidia.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Thu, Apr 14, 2022 at 01:55:33PM +0530, Kartik wrote: > The Tegra186 timer provides ten 29-bit timer counters and one 32-bit > timestamp counter. The Tegra234 timer provides sixteen 29-bit timer > counters and one 32-bit timestamp counter. Each NV timer selects its > timing reference signal from the 1 MHz reference generated by USEC, > TSC or either clk_m or OSC. Each TMR can be programmed to generate > one-shot, periodic, or watchdog interrupts. > > Signed-off-by: Kartik Full name please. > --- > .../bindings/timer/nvidia,tegra186-timer.yaml | 116 ++++++++++++++++++ > 1 file changed, 116 insertions(+) > create mode 100644 Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml > > diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml b/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml > new file mode 100644 > index 000000000000..7841a68d19f3 > --- /dev/null > +++ b/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml > @@ -0,0 +1,116 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/timer/nvidia,tegra186-timer.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: NVIDIA Tegra186 timer > + > +maintainers: > + - Thierry Reding > + > +allOf: > + - if: > + properties: > + compatible: > + contains: > + const: nvidia,tegra186-timer > + then: > + properties: > + interrupts: > + # Either a single combined interrupt or up to 14 individual interrupts This can be part of 'description' > + minItems: 1 > + maxItems: 10 > + description: > > + A list of 10 interrupts; one per each timer channels 0 through 9. Is it 10 or 14? I'm confused. > + > + - if: > + properties: > + compatible: > + contains: > + const: nvidia,tegra234-timer > + then: > + properties: > + interrupts: > + # Either a single combined interrupt or up to 16 individual interrupts > + minItems: 1 > + maxItems: 16 > + description: > > + A list of 16 interrupts; one per each timer channels 0 through 15. > + > +properties: > + compatible: > + oneOf: > + - const: nvidia,tegra186-timer > + description: > > + The Tegra186 timer provides ten 29-bit timer counters and one 32-bit > + timestamp counter. Each NV timer selects its timing reference signal > + from the 1 MHz reference generated by USEC, TSC or either clk_m or > + OSC. Each TMR can be programmed to generate one-shot, periodic, or > + watchdog interrupts. > + - const: nvidia,tegra234-timer > + description: > > + The Tegra234 timer provides sixteen 29-bit timer counters and one 32-bit > + timestamp counter. Each NV timer selects its timing reference signal > + from the 1 MHz reference generated by USEC, TSC or either clk_m or > + OSC. Each TMR can be programmed to generate one-shot, periodic, or > + watchdog interrupts. Move all this description to top-level description leaving out the exact number of counters (as the schema defines that). > + > + reg: > + maxItems: 1 > + > + interrupts: true > + > +required: > + - compatible > + - reg > + - interrupts > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + > + timer@3010000 { > + compatible = "nvidia,tegra186-timer"; > + reg = <0x03010000 0x000e0000>; > + interrupts = , > + , > + , > + , > + , > + , > + , > + , > + , > + ; > + status = "disabled"; Drop status. > + }; > + > + - | > + #include > + #include > + > + timer@2080000 { > + compatible = "nvidia,tegra234-timer"; > + reg = <0x02080000 0x00121000>; > + interrupts = , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + ; > + status = "disabled"; > + }; > -- > 2.17.1 > >