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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id x2-20020a4a2a42000000b0033a3c4392c3sm4066899oox.26.2022.04.20.12.56.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Apr 2022 12:56:36 -0700 (PDT) Received: (nullmailer pid 1749528 invoked by uid 1000); Wed, 20 Apr 2022 19:56:35 -0000 Date: Wed, 20 Apr 2022 14:56:35 -0500 From: Rob Herring To: Sergey Shtylyov Cc: Herve Codina , Marek Vasut , Yoshihiro Shimoda , Bjorn Helgaas , Krzysztof Kozlowski , Geert Uytterhoeven , Magnus Damm , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Clement Leger , Miquel Raynal Subject: Re: [PATCH v2 6/8] ARM: dts: r9a06g032: Add internal PCI bridge node Message-ID: References: <20220414074011.500533-1-herve.codina@bootlin.com> <20220414074011.500533-7-herve.codina@bootlin.com> <05c96b4d-313b-1aad-0ee5-61e54672765e@omp.ru> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <05c96b4d-313b-1aad-0ee5-61e54672765e@omp.ru> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Mon, Apr 18, 2022 at 12:02:52PM +0300, Sergey Shtylyov wrote: > Hello! > > On 4/14/22 10:40 AM, Herve Codina wrote: > > > Add the device node for the r9a06g032 internal PCI bridge device. > > > > Signed-off-by: Herve Codina > > --- > > arch/arm/boot/dts/r9a06g032.dtsi | 28 ++++++++++++++++++++++++++++ > > 1 file changed, 28 insertions(+) > > > > diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi > > index 636a6ab31c58..848dc034bb8c 100644 > > --- a/arch/arm/boot/dts/r9a06g032.dtsi > > +++ b/arch/arm/boot/dts/r9a06g032.dtsi > > @@ -211,6 +211,34 @@ gic: interrupt-controller@44101000 { > > interrupts = > > ; > > }; > > + > > + pci_usb: pci@40030000 { > > + compatible = "renesas,pci-r9a06g032", "renesas,pci-rzn1"; > > + device_type = "pci"; > > + clocks = <&sysctrl R9A06G032_HCLK_USBH>, > > + <&sysctrl R9A06G032_HCLK_USBPM>, > > + <&sysctrl R9A06G032_CLK_PCI_USB>; > > + clock-names = "hclk_usbh", "hclk_usbpm", "clk_pci_usb"; > > + reg = <0x40030000 0xc00>, > > + <0x40020000 0x1100>; > > + interrupts = ; > > + status = "disabled"; > > + > > + bus-range = <0 0>; > > + #address-cells = <3>; > > + #size-cells = <2>; > > + #interrupt-cells = <1>; > > Really? I don't think this PCI bridge is also an interrupt controller... 'interrupt-map' depends on '#interrupt-cells'. > > > + ranges = <0x02000000 0 0x40020000 0x40020000 0 0x00010000>; > > + /* Should map all possible DDR as inbound ranges, but > > + * the IP only supports a 256MB, 512MB, or 1GB window. > > + * flags, PCI addr (64-bit), CPU addr, PCI size (64-bit) > > + */ > > + dma-ranges = <0x42000000 0 0x80000000 0x80000000 0 0x40000000>; > > + interrupt-map-mask = <0xf800 0 0 0x7>; > > + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH > > + 0x0800 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH > > + 0x1000 0 0 2 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; > > + }; > > }; > > > > timer { > > MBR, Sergey