From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2B770C4332F for ; Tue, 3 May 2022 18:59:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241524AbiECTCh (ORCPT ); Tue, 3 May 2022 15:02:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56920 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239391AbiECTCg (ORCPT ); Tue, 3 May 2022 15:02:36 -0400 Received: from mail-pf1-x435.google.com (mail-pf1-x435.google.com [IPv6:2607:f8b0:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1B8723F8A6 for ; Tue, 3 May 2022 11:58:58 -0700 (PDT) Received: by mail-pf1-x435.google.com with SMTP id i24so15461177pfa.7 for ; Tue, 03 May 2022 11:58:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=dmdX5LwPiBBCHde6cuK9t05Y+cNd+V8HNLqn6OThmnY=; b=XgCWLsjWT2ACUBzrKhk9kEVSUGsJ0/T8/mNVKpqknrJ30VXd+roYiGMeFe3jc3ir9I hlqI+F/o2xulOtQZhUTTnMGLDPS/DCGJx8YJixgh51pWxXpX5I21NGxf0NVE6r26qena 5Qcm4wXadIk4GEgBmnRJbXjmy37c56u5jPtD8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=dmdX5LwPiBBCHde6cuK9t05Y+cNd+V8HNLqn6OThmnY=; b=1iy8BGqc+zkCWpt72wbWoZ1xIEr8XZg3FOO9NN8P+THFJUkgvNQWjAxH9eqBI8kbUT Rvasv73rWV7J9Efbyv2gv28JIPB9HXgyxyPBcpkrlSYMejVjyxrPew/hVgxje0btXagI jlN599+cI7BuD/SymnMXEJhVHtvjTyrJHfSyp3R3Eg0Aipcdxv0CUy7uAjjPvrpnKyEU r/kCOEtNjfZ6g6cQCD5EkJVmSHjo0/vxvbKM9HuWX8pKCNhhkHrThpeFREouSK4Nx0hD EhfY7DPY7W907LoUTvFtmtsumEZHyXWZYkF3eOiS82WSecnI0I8GmUqR1kx2FA18BRBa J7Fw== X-Gm-Message-State: AOAM53279QkFn4WWcwuO07Z0zygna7QKwxZJhhokf6XwNlK9JAqYggym Cv7My9/I/Thvi2eHGPGP7JPS1w== X-Google-Smtp-Source: ABdhPJzp9CxulKdYJY5YGKDcyq8wWINTaTB5UbuAR7+hIZGqH2QYBkpFvayfcpr6/D8NsCfLTEaPaw== X-Received: by 2002:a65:6a4e:0:b0:3aa:38d7:78e8 with SMTP id o14-20020a656a4e000000b003aa38d778e8mr14697974pgu.528.1651604337504; Tue, 03 May 2022 11:58:57 -0700 (PDT) Received: from localhost ([2620:15c:202:201:1e1a:955c:a9ca:e550]) by smtp.gmail.com with UTF8SMTPSA id v1-20020a170902ca8100b0015e8d4eb1c7sm6658713pld.17.2022.05.03.11.58.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 03 May 2022 11:58:56 -0700 (PDT) Date: Tue, 3 May 2022 11:58:55 -0700 From: Matthias Kaehlcke To: Taniya Das Cc: Rob Herring , Bjorn Andersson , Douglas Anderson , Stephen Boyd , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v4] arm64: dts: qcom: sc7280: Add lpasscore & lpassaudio clock controllers Message-ID: References: <20220503113246.13857-1-quic_tdas@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20220503113246.13857-1-quic_tdas@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Tue, May 03, 2022 at 05:02:46PM +0530, Taniya Das wrote: > Add the low pass audio clock controller device nodes. Keep the lpasscc > clock node disabled and enabled for lpass pil based devices. > > Signed-off-by: Taniya Das > --- > [v4] > * Mark lpasscc[lpasscc@3000000] device node as "disabled". > > [v3] > * Fix unwanted extra spaces in reg property. > * Fix lpass_aon node clock phandle <&lpasscc> to <&lpasscore> > > arch/arm64/boot/dts/qcom/sc7280.dtsi | 44 ++++++++++++++++++++++++++++ > 1 file changed, 44 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi > index f0b64be63c21..477a754741a1 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -8,6 +8,8 @@ > #include > #include > #include > +#include > +#include > #include > #include > #include > @@ -1978,6 +1980,48 @@ > clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; > clock-names = "iface"; > #clock-cells = <1>; > + status = "disabled"; > + }; > + > + lpass_audiocc: clock-controller@3300000 { > + compatible = "qcom,sc7280-lpassaudiocc"; > + reg = <0 0x03300000 0 0x30000>; > + clocks = <&rpmhcc RPMH_CXO_CLK>, > + <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; > + clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; > + power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; > + #clock-cells = <1>; > + #power-domain-cells = <1>; > + }; > + > + lpass_aon: clock-controller@3380000 { > + compatible = "qcom,sc7280-lpassaoncc"; > + reg = <0 0x03380000 0 0x30000>; > + clocks = <&rpmhcc RPMH_CXO_CLK>, > + <&rpmhcc RPMH_CXO_CLK_A>, > + <&lpasscore LPASS_CORE_CC_CORE_CLK>; > + clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; > + #clock-cells = <1>; > + #power-domain-cells = <1>; > + }; > + > + lpasscore: clock-controller@3900000 { nit: lpass_core? The other labels have an underscore, it wouldn't hurt to be consistent. > + compatible = "qcom,sc7280-lpasscorecc"; > + reg = <0 0x03900000 0 0x50000>; > + clocks = <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "bi_tcxo"; > + power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; > + #clock-cells = <1>; > + #power-domain-cells = <1>; > + }; > + > + lpass_hm: clock-controller@3c00000 { > + compatible = "qcom,sc7280-lpasshm"; > + reg = <0 0x3c00000 0 0x28>; > + clocks = <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "bi_tcxo"; > + #clock-cells = <1>; > + #power-domain-cells = <1>; > }; > > lpass_ag_noc: interconnect@3c40000 { > -- > Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member > of the Code Aurora Forum, hosted by the Linux Foundation. >