* [PATCH v1 1/3] dt-bindings: clock: Add resets for LPASS audio clock controller for SC7280
2022-05-03 16:46 [PATCH v1 0/3] Add support for audio clock gating resets for SC7280 Taniya Das
@ 2022-05-03 16:46 ` Taniya Das
2022-05-04 15:02 ` Rob Herring
2022-05-03 16:46 ` [PATCH v1 2/3] dt-bindings: clock: Add support for external MCLKs for LPASS on SC7280 Taniya Das
2022-05-03 16:46 ` [PATCH v1 3/3] clk: qcom: lpass: Add support for resets & external mclk for SC7280 Taniya Das
2 siblings, 1 reply; 5+ messages in thread
From: Taniya Das @ 2022-05-03 16:46 UTC (permalink / raw)
To: Stephen Boyd, Michael Turquette
Cc: Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk, linux-kernel,
devicetree, robh, robh+dt, Taniya Das
Add support for LPASS audio clock gating for RX/TX/SWA core bus clocks
for SC7280. Update reg property min/max items in YAML schema.
Fixes: 57405b795504 ("dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7280").
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
---
.../bindings/clock/qcom,sc7280-lpasscorecc.yaml | 10 ++++++++--
include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h | 5 +++++
2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml
index bad9135489de..f74d9c1cb11d 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml
@@ -38,8 +38,12 @@ properties:
'#power-domain-cells':
const: 1
+ '#reset-cells':
+ const: 1
+
reg:
- maxItems: 1
+ minItems: 1
+ maxItems: 2
required:
- compatible
@@ -116,13 +120,15 @@ examples:
#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
lpass_audiocc: clock-controller@3300000 {
compatible = "qcom,sc7280-lpassaudiocc";
- reg = <0x3300000 0x30000>;
+ reg = <0x3300000 0x30000>,
+ <0x32a9000 0x1000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>;
clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src";
power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
#clock-cells = <1>;
#power-domain-cells = <1>;
+ #reset-cells = <1>;
};
- |
diff --git a/include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h b/include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h
index 20ef2ea673f3..22dcd47d4513 100644
--- a/include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h
+++ b/include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h
@@ -24,6 +24,11 @@
#define LPASS_AUDIO_CC_RX_MCLK_CLK 14
#define LPASS_AUDIO_CC_RX_MCLK_CLK_SRC 15
+/* LPASS AUDIO CC CSR */
+#define LPASS_AUDIO_SWR_RX_CGCR 0
+#define LPASS_AUDIO_SWR_TX_CGCR 1
+#define LPASS_AUDIO_SWR_WSA_CGCR 2
+
/* LPASS_AON_CC clocks */
#define LPASS_AON_CC_PLL 0
#define LPASS_AON_CC_PLL_OUT_EVEN 1
--
2.17.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH v1 3/3] clk: qcom: lpass: Add support for resets & external mclk for SC7280
2022-05-03 16:46 [PATCH v1 0/3] Add support for audio clock gating resets for SC7280 Taniya Das
2022-05-03 16:46 ` [PATCH v1 1/3] dt-bindings: clock: Add resets for LPASS audio clock controller " Taniya Das
2022-05-03 16:46 ` [PATCH v1 2/3] dt-bindings: clock: Add support for external MCLKs for LPASS on SC7280 Taniya Das
@ 2022-05-03 16:46 ` Taniya Das
2 siblings, 0 replies; 5+ messages in thread
From: Taniya Das @ 2022-05-03 16:46 UTC (permalink / raw)
To: Stephen Boyd, Michael Turquette
Cc: Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk, linux-kernel,
devicetree, robh, robh+dt, Taniya Das
The clock gating control for TX/RX/WSA core bus clocks would be required
to be reset(moved from hardware control) from audio core driver. Thus
add the support for the reset clocks.
Also add the external mclk to interface external MI2S.
Fixes: 2b75e142523e ("clk: qcom: lpass: Add support for LPASS clock controller for SC7280").
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
---
drivers/clk/qcom/lpassaudiocc-sc7280.c | 17 ++++++++++++-
drivers/clk/qcom/lpasscorecc-sc7280.c | 33 ++++++++++++++++++++++++++
2 files changed, 49 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/lpassaudiocc-sc7280.c b/drivers/clk/qcom/lpassaudiocc-sc7280.c
index 6ab6e5a34c72..536509b78341 100644
--- a/drivers/clk/qcom/lpassaudiocc-sc7280.c
+++ b/drivers/clk/qcom/lpassaudiocc-sc7280.c
@@ -22,6 +22,7 @@
#include "clk-regmap-mux.h"
#include "common.h"
#include "gdsc.h"
+#include "reset.h"
enum {
P_BI_TCXO,
@@ -221,7 +222,7 @@ static struct clk_rcg2 lpass_aon_cc_main_rcg_clk_src = {
.parent_data = lpass_aon_cc_parent_data_0,
.num_parents = ARRAY_SIZE(lpass_aon_cc_parent_data_0),
.flags = CLK_OPS_PARENT_ENABLE,
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};
@@ -665,6 +666,18 @@ static const struct qcom_cc_desc lpass_audio_cc_sc7280_desc = {
.num_clks = ARRAY_SIZE(lpass_audio_cc_sc7280_clocks),
};
+static const struct qcom_reset_map lpass_audio_cc_sc7280_resets[] = {
+ [LPASS_AUDIO_SWR_RX_CGCR] = { 0xa0, 1 },
+ [LPASS_AUDIO_SWR_TX_CGCR] = { 0xa8, 1 },
+ [LPASS_AUDIO_SWR_WSA_CGCR] = { 0xb0, 1 },
+};
+
+static const struct qcom_cc_desc lpass_audio_cc_reset_sc7280_desc = {
+ .config = &lpass_audio_cc_sc7280_regmap_config,
+ .resets = lpass_audio_cc_sc7280_resets,
+ .num_resets = ARRAY_SIZE(lpass_audio_cc_sc7280_resets),
+};
+
static const struct of_device_id lpass_audio_cc_sc7280_match_table[] = {
{ .compatible = "qcom,sc7280-lpassaudiocc" },
{ }
@@ -741,6 +754,8 @@ static int lpass_audio_cc_sc7280_probe(struct platform_device *pdev)
return ret;
}
+ ret = qcom_cc_probe_by_index(pdev, 1, &lpass_audio_cc_reset_sc7280_desc);
+
pm_runtime_mark_last_busy(&pdev->dev);
pm_runtime_put_autosuspend(&pdev->dev);
pm_runtime_put_sync(&pdev->dev);
diff --git a/drivers/clk/qcom/lpasscorecc-sc7280.c b/drivers/clk/qcom/lpasscorecc-sc7280.c
index 1f1f1bd1b68e..6ad19b06b1ce 100644
--- a/drivers/clk/qcom/lpasscorecc-sc7280.c
+++ b/drivers/clk/qcom/lpasscorecc-sc7280.c
@@ -190,6 +190,19 @@ static struct clk_rcg2 lpass_core_cc_ext_if1_clk_src = {
},
};
+static struct clk_rcg2 lpass_core_cc_ext_mclk0_clk_src = {
+ .cmd_rcgr = 0x20000,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = lpass_core_cc_parent_map_0,
+ .freq_tbl = ftbl_lpass_core_cc_ext_if0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "lpass_core_cc_ext_mclk0_clk_src",
+ .parent_data = lpass_core_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(lpass_core_cc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+ },
+};
static struct clk_branch lpass_core_cc_core_clk = {
.halt_reg = 0x1f000,
@@ -283,6 +296,24 @@ static struct clk_branch lpass_core_cc_lpm_mem0_core_clk = {
},
};
+static struct clk_branch lpass_core_cc_ext_mclk0_clk = {
+ .halt_reg = 0x20014,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x20014,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "lpass_core_cc_ext_mclk0_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &lpass_core_cc_ext_mclk0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct clk_branch lpass_core_cc_sysnoc_mport_core_clk = {
.halt_reg = 0x23000,
.halt_check = BRANCH_HALT_VOTED,
@@ -326,6 +357,8 @@ static struct clk_regmap *lpass_core_cc_sc7280_clocks[] = {
[LPASS_CORE_CC_LPM_CORE_CLK] = &lpass_core_cc_lpm_core_clk.clkr,
[LPASS_CORE_CC_LPM_MEM0_CORE_CLK] = &lpass_core_cc_lpm_mem0_core_clk.clkr,
[LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK] = &lpass_core_cc_sysnoc_mport_core_clk.clkr,
+ [LPASS_CORE_CC_EXT_MCLK0_CLK] = &lpass_core_cc_ext_mclk0_clk.clkr,
+ [LPASS_CORE_CC_EXT_MCLK0_CLK_SRC] = &lpass_core_cc_ext_mclk0_clk_src.clkr,
};
static struct regmap_config lpass_core_cc_sc7280_regmap_config = {
--
2.17.1
^ permalink raw reply related [flat|nested] 5+ messages in thread