From: Rob Herring <robh@kernel.org>
To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Krzysztof Kozlowski <krzk@kernel.org>,
Jingoo Han <jingoohan1@gmail.com>,
Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Stanimir Varbanov <svarbanov@mm-sol.com>,
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
Vinod Koul <vkoul@kernel.org>,
linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org
Subject: Re: [PATCH v7 5/7] PCI: qcom: Handle MSIs routed to multiple GIC interrupts
Date: Thu, 5 May 2022 16:26:23 -0500 [thread overview]
Message-ID: <YnRA//LbCW+IVi3o@robh.at.kernel.org> (raw)
In-Reply-To: <20220505135407.1352382-6-dmitry.baryshkov@linaro.org>
On Thu, May 05, 2022 at 04:54:05PM +0300, Dmitry Baryshkov wrote:
> On some of Qualcomm platforms each group of 32 MSI vectors is routed to the
> separate GIC interrupt. Thus to receive higher MSI vectors properly,
> add separate msi_host_init()/msi_host_deinit() handling additional host
> IRQs.
msi_host_init() has 1 user (keystone) as it doesn't use the DWC MSI
controller. But QCom does given the access to PCIE_MSI_INTR0_STATUS,
so mutiple MSI IRQ outputs must have been added in newer versions of the
DWC IP. If so, it's only a matter of time for another platform to
do the same thing. Maybe someone from Synopsys could confirm?
Therefore this should all be handled in the DWC core. In general, I
don't want to see more users nor more ops if we don't have to. Let's not
create ops for what can be handled as data. AFAICT, this is just number
of MSIs and # of MSIs per IRQ. It seems plausible another platform could
do something similar and supporting it in the core code wouldn't
negatively impact other platforms.
Rob
next prev parent reply other threads:[~2022-05-05 21:26 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-05 13:54 [PATCH v7 0/7] PCI: qcom: Fix higher MSI vectors handling Dmitry Baryshkov
2022-05-05 13:54 ` [PATCH v7 1/7] PCI: qcom: Revert "PCI: qcom: Add support for handling MSIs from 8 endpoints" Dmitry Baryshkov
2022-05-05 20:12 ` Rob Herring
2022-05-05 13:54 ` [PATCH v7 2/7] PCI: dwc: Correct msi_irq condition in dw_pcie_free_msi() Dmitry Baryshkov
2022-05-05 20:11 ` Rob Herring
2022-05-05 13:54 ` [PATCH v7 3/7] PCI: dwc: Add msi_host_deinit callback Dmitry Baryshkov
2022-05-05 13:54 ` [PATCH v7 4/7] PCI: dwc: Export several functions useful for MSI implentations Dmitry Baryshkov
2022-05-05 13:54 ` [PATCH v7 5/7] PCI: qcom: Handle MSIs routed to multiple GIC interrupts Dmitry Baryshkov
2022-05-05 21:26 ` Rob Herring [this message]
2022-05-06 7:40 ` Dmitry Baryshkov
2022-05-09 21:00 ` Rob Herring
2022-05-05 13:54 ` [PATCH v7 6/7] dt-bindings: PCI: qcom: Support additional MSI interrupts Dmitry Baryshkov
2022-05-05 21:30 ` Rob Herring
2022-05-11 14:50 ` Dmitry Baryshkov
2022-05-05 13:54 ` [PATCH v7 7/7] arm64: dts: qcom: sm8250: provide " Dmitry Baryshkov
2022-05-05 15:37 ` [PATCH v7 0/7] PCI: qcom: Fix higher MSI vectors handling Stanimir Varbanov
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