[PATCH v2 0/2] riscv mmu-type minor fixes

[PATCH v2 0/2] riscv mmu-type minor fixes

[Niklas Cassel]

Hello there,


Here are some minor riscv mmu-type related fixes.

The first patch simply adds "riscv,sv57" to the list of valid mmu-type
values.

The second patch fixes the "mmu:" print in /proc/cpuinfo on nommu systems.

Please review.


Kind regards,
Niklas

Changes since v1:
-Picked up tag from Rob Herring on patch 1/1.
-Send both patches as a series, since they are relate to mmu-type.

Niklas Cassel (2):
  dt-bindings: riscv: Add mmu-type riscv,sv57
  riscv: Don't output a bogus mmu-type on a no MMU kernel

 Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
 arch/riscv/kernel/cpu.c                           | 4 ++++
 2 files changed, 5 insertions(+)

-- 
2.35.1

[PATCH v2 1/2] dt-bindings: riscv: Add mmu-type riscv,sv57

[Niklas Cassel]

sv57 is defined in the RISC-V Privileged Specification document.

Additionally, commit 011f09d12052 ("riscv: mm: Set sv57 on defaultly")
changed the default MMU mode to sv57, if supported by current hardware.

Add riscv,sv57 to the list of valid mmu-type values.

Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
Acked-by: Rob Herring <robh@kernel.org>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index d632ac76532e..3100fa233ca4 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -61,6 +61,7 @@ properties:
       - riscv,sv32
       - riscv,sv39
       - riscv,sv48
+      - riscv,sv57
       - riscv,none
 
   riscv,isa:
-- 
2.35.1

Re: [PATCH v2 1/2] dt-bindings: riscv: Add mmu-type riscv,sv57

[Anup Patel]

On Mon, May 2, 2022 at 6:20 PM Niklas Cassel <niklas.cassel@wdc.com> wrote:
>
> sv57 is defined in the RISC-V Privileged Specification document.
>
> Additionally, commit 011f09d12052 ("riscv: mm: Set sv57 on defaultly")
> changed the default MMU mode to sv57, if supported by current hardware.
>
> Add riscv,sv57 to the list of valid mmu-type values.
>
> Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
> Acked-by: Rob Herring <robh@kernel.org>

Looks good to me.

Reviewed-by: Anup Patel <anup@brainfault.org>

Regards,
Anup

> ---
>  Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index d632ac76532e..3100fa233ca4 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -61,6 +61,7 @@ properties:
>        - riscv,sv32
>        - riscv,sv39
>        - riscv,sv48
> +      - riscv,sv57
>        - riscv,none
>
>    riscv,isa:
> --
> 2.35.1
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH v2 0/2] riscv mmu-type minor fixes

[Niklas Cassel]

On Mon, May 02, 2022 at 02:50:12PM +0200, Niklas Cassel wrote:
> Hello there,
> 
> 
> Here are some minor riscv mmu-type related fixes.
> 
> The first patch simply adds "riscv,sv57" to the list of valid mmu-type
> values.
> 
> The second patch fixes the "mmu:" print in /proc/cpuinfo on nommu systems.
> 
> Please review.
> 
> 
> Kind regards,
> Niklas
> 
> Changes since v1:
> -Picked up tag from Rob Herring on patch 1/1.
> -Send both patches as a series, since they are relate to mmu-type.
> 
> Niklas Cassel (2):
>   dt-bindings: riscv: Add mmu-type riscv,sv57
>   riscv: Don't output a bogus mmu-type on a no MMU kernel
> 
>  Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
>  arch/riscv/kernel/cpu.c                           | 4 ++++
>  2 files changed, 5 insertions(+)
> 
> -- 
> 2.35.1
> 

Hello Palmer,

A gentle ping.
Any chance of this getting picked up?


Kind regards,
Niklas