* [PATCH v2 1/5] dt-bindings: phy: qcom,qmp: Add compatible for SC8280XP USB phys
2022-06-07 21:35 [PATCH v2 0/5] phy: qcom: Add SC8280XP UNI and COMBO USB phys Bjorn Andersson
@ 2022-06-07 21:35 ` Bjorn Andersson
2022-06-08 7:58 ` Krzysztof Kozlowski
2022-06-07 21:35 ` [PATCH v2 2/5] phy: qcom-qmp: Add USB3 5NM QMP UNI registers Bjorn Andersson
` (4 subsequent siblings)
5 siblings, 1 reply; 16+ messages in thread
From: Bjorn Andersson @ 2022-06-07 21:35 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Rob Herring,
Krzysztof Kozlowski, Manu Gautam
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel
The SC8280XP platform has a pair of 5nm USB3 UNI phys and a pair of
5nm USB4/3/DP combo PHYs, add a compatible for these.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
Changes since v1:
- Added compatible for selection of properties for the uni phy
- Added combo phy in the same patch
Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 2 ++
Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml | 1 +
2 files changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
index 8b850c5ab116..777bc1a48aa8 100644
--- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
@@ -33,6 +33,7 @@ properties:
- qcom,sc8180x-qmp-ufs-phy
- qcom,sc8180x-qmp-usb3-phy
- qcom,sc8280xp-qmp-ufs-phy
+ - qcom,sc8280xp-qmp-usb3-uni-phy
- qcom,sdm845-qhp-pcie-phy
- qcom,sdm845-qmp-pcie-phy
- qcom,sdm845-qmp-ufs-phy
@@ -377,6 +378,7 @@ allOf:
- qcom,sm8150-qmp-usb3-uni-phy
- qcom,sm8250-qmp-usb3-uni-phy
- qcom,sm8350-qmp-usb3-uni-phy
+ - qcom,sc8280xp-qmp-usb3-uni-phy
then:
properties:
clocks:
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml
index 60dc27834e1d..32b1e5b67275 100644
--- a/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml
@@ -16,6 +16,7 @@ properties:
- qcom,sc7180-qmp-usb3-dp-phy
- qcom,sc7280-qmp-usb3-dp-phy
- qcom,sc8180x-qmp-usb3-dp-phy
+ - qcom,sc8280xp-qmp-usb43dp-phy
- qcom,sdm845-qmp-usb3-dp-phy
- qcom,sm8250-qmp-usb3-dp-phy
reg:
--
2.35.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v2 1/5] dt-bindings: phy: qcom,qmp: Add compatible for SC8280XP USB phys
2022-06-07 21:35 ` [PATCH v2 1/5] dt-bindings: phy: qcom,qmp: Add compatible for SC8280XP " Bjorn Andersson
@ 2022-06-08 7:58 ` Krzysztof Kozlowski
0 siblings, 0 replies; 16+ messages in thread
From: Krzysztof Kozlowski @ 2022-06-08 7:58 UTC (permalink / raw)
To: Bjorn Andersson, Kishon Vijay Abraham I, Vinod Koul, Rob Herring,
Krzysztof Kozlowski, Manu Gautam
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel
On 07/06/2022 23:35, Bjorn Andersson wrote:
> The SC8280XP platform has a pair of 5nm USB3 UNI phys and a pair of
> 5nm USB4/3/DP combo PHYs, add a compatible for these.
>
> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v2 2/5] phy: qcom-qmp: Add USB3 5NM QMP UNI registers
2022-06-07 21:35 [PATCH v2 0/5] phy: qcom: Add SC8280XP UNI and COMBO USB phys Bjorn Andersson
2022-06-07 21:35 ` [PATCH v2 1/5] dt-bindings: phy: qcom,qmp: Add compatible for SC8280XP " Bjorn Andersson
@ 2022-06-07 21:35 ` Bjorn Andersson
2022-06-07 21:58 ` Dmitry Baryshkov
2022-06-07 21:35 ` [PATCH v2 3/5] phy: qcom-qmp: Add USB4 5NM QMP combo PHY registers Bjorn Andersson
` (3 subsequent siblings)
5 siblings, 1 reply; 16+ messages in thread
From: Bjorn Andersson @ 2022-06-07 21:35 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Manu Gautam
Cc: Rob Herring, Krzysztof Kozlowski, linux-arm-msm, linux-phy,
devicetree, linux-kernel
Add all registers defines from qcom,usb3-5nm-qmp-uni.h of the msm-5.4
kernel. Offsets are adjusted to be relative to each sub-block, as we
describe the individual pieces in the upstream kernel and "V5_5NM" is
injected in the defines to avoid colliding with existing and future
constants.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
Changes since v1:
- Added "V5" to the defines, per discussion with Vinod.
.../phy/qualcomm/phy-qcom-usb3-5nm-qmp-uni.h | 617 ++++++++++++++++++
1 file changed, 617 insertions(+)
create mode 100644 drivers/phy/qualcomm/phy-qcom-usb3-5nm-qmp-uni.h
diff --git a/drivers/phy/qualcomm/phy-qcom-usb3-5nm-qmp-uni.h b/drivers/phy/qualcomm/phy-qcom-usb3-5nm-qmp-uni.h
new file mode 100644
index 000000000000..304c21167388
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-usb3-5nm-qmp-uni.h
@@ -0,0 +1,617 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef PHY_QCOM_USB3_V5_5NM_QMP_UNI_H_
+#define PHY_QCOM_USB3_V5_5NM_QMP_UNI_H_
+
+/* Module: USB3_UNI_PHY_QSERDES_COM_QSERDES_COM_PCIE_USB3_UNI_QMP_PLL */
+#define USB3_V5_5NM_UNI_QSERDES_COM_ATB_SEL1 0x000
+#define USB3_V5_5NM_UNI_QSERDES_COM_ATB_SEL2 0x004
+#define USB3_V5_5NM_UNI_QSERDES_COM_FREQ_UPDATE 0x008
+#define USB3_V5_5NM_UNI_QSERDES_COM_BG_TIMER 0x00c
+#define USB3_V5_5NM_UNI_QSERDES_COM_SSC_EN_CENTER 0x010
+#define USB3_V5_5NM_UNI_QSERDES_COM_SSC_ADJ_PER1 0x014
+#define USB3_V5_5NM_UNI_QSERDES_COM_SSC_ADJ_PER2 0x018
+#define USB3_V5_5NM_UNI_QSERDES_COM_SSC_PER1 0x01c
+#define USB3_V5_5NM_UNI_QSERDES_COM_SSC_PER2 0x020
+#define USB3_V5_5NM_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0x024
+#define USB3_V5_5NM_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x028
+#define USB3_V5_5NM_UNI_QSERDES_COM_SSC_STEP_SIZE3_MODE0 0x02c
+#define USB3_V5_5NM_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0x030
+#define USB3_V5_5NM_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x034
+#define USB3_V5_5NM_UNI_QSERDES_COM_SSC_STEP_SIZE3_MODE1 0x038
+#define USB3_V5_5NM_UNI_QSERDES_COM_POST_DIV 0x03c
+#define USB3_V5_5NM_UNI_QSERDES_COM_POST_DIV_MUX 0x040
+#define USB3_V5_5NM_UNI_QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x044
+#define USB3_V5_5NM_UNI_QSERDES_COM_CLK_ENABLE1 0x048
+#define USB3_V5_5NM_UNI_QSERDES_COM_SYS_CLK_CTRL 0x04c
+#define USB3_V5_5NM_UNI_QSERDES_COM_SYSCLK_BUF_ENABLE 0x050
+#define USB3_V5_5NM_UNI_QSERDES_COM_PLL_EN 0x054
+#define USB3_V5_5NM_UNI_QSERDES_COM_PLL_IVCO 0x058
+#define USB3_V5_5NM_UNI_QSERDES_COM_CMN_IETRIM 0x05c
+#define USB3_V5_5NM_UNI_QSERDES_COM_CMN_IPTRIM 0x060
+#define USB3_V5_5NM_UNI_QSERDES_COM_EP_CLOCK_DETECT_CTRL 0x064
+#define USB3_V5_5NM_UNI_QSERDES_COM_SYSCLK_DET_COMP_STATUS 0x068
+#define USB3_V5_5NM_UNI_QSERDES_COM_CLK_EP_DIV_MODE0 0x06c
+#define USB3_V5_5NM_UNI_QSERDES_COM_CLK_EP_DIV_MODE1 0x070
+#define USB3_V5_5NM_UNI_QSERDES_COM_CP_CTRL_MODE0 0x074
+#define USB3_V5_5NM_UNI_QSERDES_COM_CP_CTRL_MODE1 0x078
+#define USB3_V5_5NM_UNI_QSERDES_COM_PLL_RCTRL_MODE0 0x07c
+#define USB3_V5_5NM_UNI_QSERDES_COM_PLL_RCTRL_MODE1 0x080
+#define USB3_V5_5NM_UNI_QSERDES_COM_PLL_CCTRL_MODE0 0x084
+#define USB3_V5_5NM_UNI_QSERDES_COM_PLL_CCTRL_MODE1 0x088
+#define USB3_V5_5NM_UNI_QSERDES_COM_PLL_CNTRL 0x08c
+#define USB3_V5_5NM_UNI_QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x090
+#define USB3_V5_5NM_UNI_QSERDES_COM_SYSCLK_EN_SEL 0x094
+#define USB3_V5_5NM_UNI_QSERDES_COM_CML_SYSCLK_SEL 0x098
+#define USB3_V5_5NM_UNI_QSERDES_COM_RESETSM_CNTRL 0x09c
+#define USB3_V5_5NM_UNI_QSERDES_COM_RESETSM_CNTRL2 0x0a0
+#define USB3_V5_5NM_UNI_QSERDES_COM_LOCK_CMP_EN 0x0a4
+#define USB3_V5_5NM_UNI_QSERDES_COM_LOCK_CMP_CFG 0x0a8
+#define USB3_V5_5NM_UNI_QSERDES_COM_LOCK_CMP1_MODE0 0x0ac
+#define USB3_V5_5NM_UNI_QSERDES_COM_LOCK_CMP2_MODE0 0x0b0
+#define USB3_V5_5NM_UNI_QSERDES_COM_LOCK_CMP1_MODE1 0x0b4
+#define USB3_V5_5NM_UNI_QSERDES_COM_LOCK_CMP2_MODE1 0x0b8
+#define USB3_V5_5NM_UNI_QSERDES_COM_DEC_START_MODE0 0x0bc
+#define USB3_V5_5NM_UNI_QSERDES_COM_DEC_START_MSB_MODE0 0x0c0
+#define USB3_V5_5NM_UNI_QSERDES_COM_DEC_START_MODE1 0x0c4
+#define USB3_V5_5NM_UNI_QSERDES_COM_DEC_START_MSB_MODE1 0x0c8
+#define USB3_V5_5NM_UNI_QSERDES_COM_DIV_FRAC_START1_MODE0 0x0cc
+#define USB3_V5_5NM_UNI_QSERDES_COM_DIV_FRAC_START2_MODE0 0x0d0
+#define USB3_V5_5NM_UNI_QSERDES_COM_DIV_FRAC_START3_MODE0 0x0d4
+#define USB3_V5_5NM_UNI_QSERDES_COM_DIV_FRAC_START1_MODE1 0x0d8
+#define USB3_V5_5NM_UNI_QSERDES_COM_DIV_FRAC_START2_MODE1 0x0dc
+#define USB3_V5_5NM_UNI_QSERDES_COM_DIV_FRAC_START3_MODE1 0x0e0
+#define USB3_V5_5NM_UNI_QSERDES_COM_INTEGLOOP_INITVAL 0x0e4
+#define USB3_V5_5NM_UNI_QSERDES_COM_INTEGLOOP_EN 0x0e8
+#define USB3_V5_5NM_UNI_QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x0ec
+#define USB3_V5_5NM_UNI_QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x0f0
+#define USB3_V5_5NM_UNI_QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x0f4
+#define USB3_V5_5NM_UNI_QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x0f8
+#define USB3_V5_5NM_UNI_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0 0x0fc
+#define USB3_V5_5NM_UNI_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1 0x100
+#define USB3_V5_5NM_UNI_QSERDES_COM_VCOCAL_DEADMAN_CTRL 0x104
+#define USB3_V5_5NM_UNI_QSERDES_COM_VCO_TUNE_CTRL 0x108
+#define USB3_V5_5NM_UNI_QSERDES_COM_VCO_TUNE_MAP 0x10c
+#define USB3_V5_5NM_UNI_QSERDES_COM_VCO_TUNE1_MODE0 0x110
+#define USB3_V5_5NM_UNI_QSERDES_COM_VCO_TUNE2_MODE0 0x114
+#define USB3_V5_5NM_UNI_QSERDES_COM_VCO_TUNE1_MODE1 0x118
+#define USB3_V5_5NM_UNI_QSERDES_COM_VCO_TUNE2_MODE1 0x11c
+#define USB3_V5_5NM_UNI_QSERDES_COM_VCO_TUNE_INITVAL1 0x120
+#define USB3_V5_5NM_UNI_QSERDES_COM_VCO_TUNE_INITVAL2 0x124
+#define USB3_V5_5NM_UNI_QSERDES_COM_VCO_TUNE_MINVAL1 0x128
+#define USB3_V5_5NM_UNI_QSERDES_COM_VCO_TUNE_MINVAL2 0x12c
+#define USB3_V5_5NM_UNI_QSERDES_COM_VCO_TUNE_MAXVAL1 0x130
+#define USB3_V5_5NM_UNI_QSERDES_COM_VCO_TUNE_MAXVAL2 0x134
+#define USB3_V5_5NM_UNI_QSERDES_COM_VCO_TUNE_TIMER1 0x138
+#define USB3_V5_5NM_UNI_QSERDES_COM_VCO_TUNE_TIMER2 0x13c
+#define USB3_V5_5NM_UNI_QSERDES_COM_CMN_STATUS 0x140
+#define USB3_V5_5NM_UNI_QSERDES_COM_RESET_SM_STATUS 0x144
+#define USB3_V5_5NM_UNI_QSERDES_COM_RESTRIM_CODE_STATUS 0x148
+#define USB3_V5_5NM_UNI_QSERDES_COM_PLLCAL_CODE1_STATUS 0x14c
+#define USB3_V5_5NM_UNI_QSERDES_COM_PLLCAL_CODE2_STATUS 0x150
+#define USB3_V5_5NM_UNI_QSERDES_COM_CLK_SELECT 0x154
+#define USB3_V5_5NM_UNI_QSERDES_COM_HSCLK_SEL 0x158
+#define USB3_V5_5NM_UNI_QSERDES_COM_HSCLK_HS_SWITCH_SEL 0x15c
+#define USB3_V5_5NM_UNI_QSERDES_COM_INTEGLOOP_BINCODE_STATUS 0x160
+#define USB3_V5_5NM_UNI_QSERDES_COM_PLL_ANALOG 0x164
+#define USB3_V5_5NM_UNI_QSERDES_COM_CORECLK_DIV_MODE0 0x168
+#define USB3_V5_5NM_UNI_QSERDES_COM_CORECLK_DIV_MODE1 0x16c
+#define USB3_V5_5NM_UNI_QSERDES_COM_SW_RESET 0x170
+#define USB3_V5_5NM_UNI_QSERDES_COM_CORE_CLK_EN 0x174
+#define USB3_V5_5NM_UNI_QSERDES_COM_C_READY_STATUS 0x178
+#define USB3_V5_5NM_UNI_QSERDES_COM_CMN_CONFIG 0x17c
+#define USB3_V5_5NM_UNI_QSERDES_COM_CMN_RATE_OVERRIDE 0x180
+#define USB3_V5_5NM_UNI_QSERDES_COM_SVS_MODE_CLK_SEL 0x184
+#define USB3_V5_5NM_UNI_QSERDES_COM_DEBUG_BUS0 0x188
+#define USB3_V5_5NM_UNI_QSERDES_COM_DEBUG_BUS1 0x18c
+#define USB3_V5_5NM_UNI_QSERDES_COM_DEBUG_BUS2 0x190
+#define USB3_V5_5NM_UNI_QSERDES_COM_DEBUG_BUS3 0x194
+#define USB3_V5_5NM_UNI_QSERDES_COM_DEBUG_BUS_SEL 0x198
+#define USB3_V5_5NM_UNI_QSERDES_COM_CMN_MISC1 0x19c
+#define USB3_V5_5NM_UNI_QSERDES_COM_CMN_MODE 0x1a0
+#define USB3_V5_5NM_UNI_QSERDES_COM_CMN_MODE_CONTD 0x1a4
+#define USB3_V5_5NM_UNI_QSERDES_COM_VCO_DC_LEVEL_CTRL 0x1a8
+#define USB3_V5_5NM_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac
+#define USB3_V5_5NM_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0
+#define USB3_V5_5NM_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4
+#define USB3_V5_5NM_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8
+#define USB3_V5_5NM_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc
+#define USB3_V5_5NM_UNI_QSERDES_COM_RESERVED_1 0x1c0
+#define USB3_V5_5NM_UNI_QSERDES_COM_MODE_OPERATION_STATUS 0x1c4
+
+/* Module: USB3_UNI_PHY_QSERDES_TX_PCIE_USB3_UNI_QMP_TX */
+#define USB3_V5_5NM_UNI_QSERDES_TX_BIST_MODE_LANENO 0x000
+#define USB3_V5_5NM_UNI_QSERDES_TX_BIST_INVERT 0x004
+#define USB3_V5_5NM_UNI_QSERDES_TX_CLKBUF_ENABLE 0x008
+#define USB3_V5_5NM_UNI_QSERDES_TX_TX_EMP_POST1_LVL 0x00c
+#define USB3_V5_5NM_UNI_QSERDES_TX_TX_IDLE_LVL_LARGE_AMP 0x010
+#define USB3_V5_5NM_UNI_QSERDES_TX_TX_DRV_LVL 0x014
+#define USB3_V5_5NM_UNI_QSERDES_TX_TX_DRV_LVL_OFFSET 0x018
+#define USB3_V5_5NM_UNI_QSERDES_TX_RESET_TSYNC_EN 0x01c
+#define USB3_V5_5NM_UNI_QSERDES_TX_PRE_STALL_LDO_BOOST_EN 0x020
+#define USB3_V5_5NM_UNI_QSERDES_TX_TX_BAND 0x024
+#define USB3_V5_5NM_UNI_QSERDES_TX_SLEW_CNTL 0x028
+#define USB3_V5_5NM_UNI_QSERDES_TX_INTERFACE_SELECT 0x02c
+#define USB3_V5_5NM_UNI_QSERDES_TX_LPB_EN 0x030
+#define USB3_V5_5NM_UNI_QSERDES_TX_RES_CODE_LANE_TX 0x034
+#define USB3_V5_5NM_UNI_QSERDES_TX_RES_CODE_LANE_RX 0x038
+#define USB3_V5_5NM_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x03c
+#define USB3_V5_5NM_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_RX 0x040
+#define USB3_V5_5NM_UNI_QSERDES_TX_PERL_LENGTH1 0x044
+#define USB3_V5_5NM_UNI_QSERDES_TX_PERL_LENGTH2 0x048
+#define USB3_V5_5NM_UNI_QSERDES_TX_SERDES_BYP_EN_OUT 0x04c
+#define USB3_V5_5NM_UNI_QSERDES_TX_DEBUG_BUS_SEL 0x050
+#define USB3_V5_5NM_UNI_QSERDES_TX_TRANSCEIVER_BIAS_EN 0x054
+#define USB3_V5_5NM_UNI_QSERDES_TX_HIGHZ_DRVR_EN 0x058
+#define USB3_V5_5NM_UNI_QSERDES_TX_TX_POL_INV 0x05c
+#define USB3_V5_5NM_UNI_QSERDES_TX_PARRATE_REC_DETECT_IDLE_EN 0x060
+#define USB3_V5_5NM_UNI_QSERDES_TX_BIST_PATTERN1 0x064
+#define USB3_V5_5NM_UNI_QSERDES_TX_BIST_PATTERN2 0x068
+#define USB3_V5_5NM_UNI_QSERDES_TX_BIST_PATTERN3 0x06c
+#define USB3_V5_5NM_UNI_QSERDES_TX_BIST_PATTERN4 0x070
+#define USB3_V5_5NM_UNI_QSERDES_TX_BIST_PATTERN5 0x074
+#define USB3_V5_5NM_UNI_QSERDES_TX_BIST_PATTERN6 0x078
+#define USB3_V5_5NM_UNI_QSERDES_TX_BIST_PATTERN7 0x07c
+#define USB3_V5_5NM_UNI_QSERDES_TX_BIST_PATTERN8 0x080
+#define USB3_V5_5NM_UNI_QSERDES_TX_LANE_MODE_1 0x084
+#define USB3_V5_5NM_UNI_QSERDES_TX_LANE_MODE_2 0x088
+#define USB3_V5_5NM_UNI_QSERDES_TX_LANE_MODE_3 0x08c
+#define USB3_V5_5NM_UNI_QSERDES_TX_LANE_MODE_4 0x090
+#define USB3_V5_5NM_UNI_QSERDES_TX_LANE_MODE_5 0x094
+#define USB3_V5_5NM_UNI_QSERDES_TX_ATB_SEL1 0x098
+#define USB3_V5_5NM_UNI_QSERDES_TX_ATB_SEL2 0x09c
+#define USB3_V5_5NM_UNI_QSERDES_TX_RCV_DETECT_LVL 0x0a0
+#define USB3_V5_5NM_UNI_QSERDES_TX_RCV_DETECT_LVL_2 0x0a4
+#define USB3_V5_5NM_UNI_QSERDES_TX_PRBS_SEED1 0x0a8
+#define USB3_V5_5NM_UNI_QSERDES_TX_PRBS_SEED2 0x0ac
+#define USB3_V5_5NM_UNI_QSERDES_TX_PRBS_SEED3 0x0b0
+#define USB3_V5_5NM_UNI_QSERDES_TX_PRBS_SEED4 0x0b4
+#define USB3_V5_5NM_UNI_QSERDES_TX_RESET_GEN 0x0b8
+#define USB3_V5_5NM_UNI_QSERDES_TX_RESET_GEN_MUXES 0x0bc
+#define USB3_V5_5NM_UNI_QSERDES_TX_TRAN_DRVR_EMP_EN 0x0c0
+#define USB3_V5_5NM_UNI_QSERDES_TX_TX_INTERFACE_MODE 0x0c4
+#define USB3_V5_5NM_UNI_QSERDES_TX_VMODE_CTRL1 0x0c8
+#define USB3_V5_5NM_UNI_QSERDES_TX_ALOG_OBSV_BUS_CTRL_1 0x0cc
+#define USB3_V5_5NM_UNI_QSERDES_TX_BIST_STATUS 0x0d0
+#define USB3_V5_5NM_UNI_QSERDES_TX_BIST_ERROR_COUNT1 0x0d4
+#define USB3_V5_5NM_UNI_QSERDES_TX_BIST_ERROR_COUNT2 0x0d8
+#define USB3_V5_5NM_UNI_QSERDES_TX_ALOG_OBSV_BUS_STATUS_1 0x0dc
+#define USB3_V5_5NM_UNI_QSERDES_TX_LANE_DIG_CONFIG 0x0e0
+#define USB3_V5_5NM_UNI_QSERDES_TX_PI_QEC_CTRL 0x0e4
+#define USB3_V5_5NM_UNI_QSERDES_TX_PRE_EMPH 0x0e8
+#define USB3_V5_5NM_UNI_QSERDES_TX_SW_RESET 0x0ec
+#define USB3_V5_5NM_UNI_QSERDES_TX_DCC_OFFSET 0x0f0
+#define USB3_V5_5NM_UNI_QSERDES_TX_DCC_CMUX_POSTCAL_OFFSET 0x0f4
+#define USB3_V5_5NM_UNI_QSERDES_TX_DCC_CMUX_CAL_CTRL1 0x0f8
+#define USB3_V5_5NM_UNI_QSERDES_TX_DCC_CMUX_CAL_CTRL2 0x0fc
+#define USB3_V5_5NM_UNI_QSERDES_TX_DIG_BKUP_CTRL 0x100
+#define USB3_V5_5NM_UNI_QSERDES_TX_DEBUG_BUS0 0x104
+#define USB3_V5_5NM_UNI_QSERDES_TX_DEBUG_BUS1 0x108
+#define USB3_V5_5NM_UNI_QSERDES_TX_DEBUG_BUS2 0x10c
+#define USB3_V5_5NM_UNI_QSERDES_TX_DEBUG_BUS3 0x110
+#define USB3_V5_5NM_UNI_QSERDES_TX_READ_EQCODE 0x114
+#define USB3_V5_5NM_UNI_QSERDES_TX_READ_OFFSETCODE 0x118
+#define USB3_V5_5NM_UNI_QSERDES_TX_IA_ERROR_COUNTER_LOW 0x11c
+#define USB3_V5_5NM_UNI_QSERDES_TX_IA_ERROR_COUNTER_HIGH 0x120
+#define USB3_V5_5NM_UNI_QSERDES_TX_VGA_READ_CODE 0x124
+#define USB3_V5_5NM_UNI_QSERDES_TX_VTH_READ_CODE 0x128
+#define USB3_V5_5NM_UNI_QSERDES_TX_DFE_TAP1_READ_CODE 0x12c
+#define USB3_V5_5NM_UNI_QSERDES_TX_DFE_TAP2_READ_CODE 0x130
+#define USB3_V5_5NM_UNI_QSERDES_TX_IDAC_STATUS_I 0x134
+#define USB3_V5_5NM_UNI_QSERDES_TX_IDAC_STATUS_IBAR 0x138
+#define USB3_V5_5NM_UNI_QSERDES_TX_IDAC_STATUS_Q 0x13c
+#define USB3_V5_5NM_UNI_QSERDES_TX_IDAC_STATUS_QBAR 0x140
+#define USB3_V5_5NM_UNI_QSERDES_TX_IDAC_STATUS_A 0x144
+#define USB3_V5_5NM_UNI_QSERDES_TX_IDAC_STATUS_ABAR 0x148
+#define USB3_V5_5NM_UNI_QSERDES_TX_IDAC_STATUS_SM_ON 0x14c
+#define USB3_V5_5NM_UNI_QSERDES_TX_IDAC_STATUS_CAL_DONE 0x150
+#define USB3_V5_5NM_UNI_QSERDES_TX_IDAC_STATUS_SIGNERROR 0x154
+#define USB3_V5_5NM_UNI_QSERDES_TX_DCC_CAL_STATUS 0x158
+#define USB3_V5_5NM_UNI_QSERDES_TX_DCC_READ_CODE_STATUS 0x15c
+
+/* Module: USB3_UNI_PHY_QSERDES_RX_QSERDES_RX_PCIE_USB3_UNI_QMP_RX */
+#define USB3_V5_5NM_UNI_QSERDES_RX_UCDR_FO_GAIN_HALF 0x000
+#define USB3_V5_5NM_UNI_QSERDES_RX_UCDR_FO_GAIN_QUARTER 0x004
+#define USB3_V5_5NM_UNI_QSERDES_RX_UCDR_FO_GAIN 0x008
+#define USB3_V5_5NM_UNI_QSERDES_RX_UCDR_SO_GAIN_HALF 0x00c
+#define USB3_V5_5NM_UNI_QSERDES_RX_UCDR_SO_GAIN_QUARTER 0x010
+#define USB3_V5_5NM_UNI_QSERDES_RX_UCDR_SO_GAIN 0x014
+#define USB3_V5_5NM_UNI_QSERDES_RX_UCDR_SVS_FO_GAIN_HALF 0x018
+#define USB3_V5_5NM_UNI_QSERDES_RX_UCDR_SVS_FO_GAIN_QUARTER 0x01c
+#define USB3_V5_5NM_UNI_QSERDES_RX_UCDR_SVS_FO_GAIN 0x020
+#define USB3_V5_5NM_UNI_QSERDES_RX_UCDR_SVS_SO_GAIN_HALF 0x024
+#define USB3_V5_5NM_UNI_QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER 0x028
+#define USB3_V5_5NM_UNI_QSERDES_RX_UCDR_SVS_SO_GAIN 0x02c
+#define USB3_V5_5NM_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x030
+#define USB3_V5_5NM_UNI_QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034
+#define USB3_V5_5NM_UNI_QSERDES_RX_UCDR_FO_TO_SO_DELAY 0x038
+#define USB3_V5_5NM_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c
+#define USB3_V5_5NM_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040
+#define USB3_V5_5NM_UNI_QSERDES_RX_UCDR_PI_CONTROLS 0x044
+#define USB3_V5_5NM_UNI_QSERDES_RX_UCDR_PI_CTRL2 0x048
+#define USB3_V5_5NM_UNI_QSERDES_RX_UCDR_SB2_THRESH1 0x04c
+#define USB3_V5_5NM_UNI_QSERDES_RX_UCDR_SB2_THRESH2 0x050
+#define USB3_V5_5NM_UNI_QSERDES_RX_UCDR_SB2_GAIN1 0x054
+#define USB3_V5_5NM_UNI_QSERDES_RX_UCDR_SB2_GAIN2 0x058
+#define USB3_V5_5NM_UNI_QSERDES_RX_AUX_CONTROL 0x05c
+#define USB3_V5_5NM_UNI_QSERDES_RX_AUX_DATA_TCOARSE_TFINE 0x060
+#define USB3_V5_5NM_UNI_QSERDES_RX_RCLK_AUXDATA_SEL 0x064
+#define USB3_V5_5NM_UNI_QSERDES_RX_AC_JTAG_ENABLE 0x068
+#define USB3_V5_5NM_UNI_QSERDES_RX_AC_JTAG_INITP 0x06c
+#define USB3_V5_5NM_UNI_QSERDES_RX_AC_JTAG_INITN 0x070
+#define USB3_V5_5NM_UNI_QSERDES_RX_AC_JTAG_LVL 0x074
+#define USB3_V5_5NM_UNI_QSERDES_RX_AC_JTAG_MODE 0x078
+#define USB3_V5_5NM_UNI_QSERDES_RX_AC_JTAG_RESET 0x07c
+#define USB3_V5_5NM_UNI_QSERDES_RX_RX_TERM_BW 0x080
+#define USB3_V5_5NM_UNI_QSERDES_RX_RX_RCVR_IQ_EN 0x084
+#define USB3_V5_5NM_UNI_QSERDES_RX_RX_IDAC_I_DC_OFFSETS 0x088
+#define USB3_V5_5NM_UNI_QSERDES_RX_RX_IDAC_IBAR_DC_OFFSETS 0x08c
+#define USB3_V5_5NM_UNI_QSERDES_RX_RX_IDAC_Q_DC_OFFSETS 0x090
+#define USB3_V5_5NM_UNI_QSERDES_RX_RX_IDAC_QBAR_DC_OFFSETS 0x094
+#define USB3_V5_5NM_UNI_QSERDES_RX_RX_IDAC_A_DC_OFFSETS 0x098
+#define USB3_V5_5NM_UNI_QSERDES_RX_RX_IDAC_ABAR_DC_OFFSETS 0x09c
+#define USB3_V5_5NM_UNI_QSERDES_RX_RX_IDAC_EN 0x0a0
+#define USB3_V5_5NM_UNI_QSERDES_RX_RX_IDAC_ENABLES 0x0a4
+#define USB3_V5_5NM_UNI_QSERDES_RX_RX_IDAC_SIGN 0x0a8
+#define USB3_V5_5NM_UNI_QSERDES_RX_RX_HIGHZ_HIGHRATE 0x0ac
+#define USB3_V5_5NM_UNI_QSERDES_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x0b0
+#define USB3_V5_5NM_UNI_QSERDES_RX_DFE_1 0x0b4
+#define USB3_V5_5NM_UNI_QSERDES_RX_DFE_2 0x0b8
+#define USB3_V5_5NM_UNI_QSERDES_RX_DFE_3 0x0bc
+#define USB3_V5_5NM_UNI_QSERDES_RX_DFE_4 0x0c0
+#define USB3_V5_5NM_UNI_QSERDES_RX_TX_ADAPT_PRE_THRESH1 0x0c4
+#define USB3_V5_5NM_UNI_QSERDES_RX_TX_ADAPT_PRE_THRESH2 0x0c8
+#define USB3_V5_5NM_UNI_QSERDES_RX_TX_ADAPT_POST_THRESH 0x0cc
+#define USB3_V5_5NM_UNI_QSERDES_RX_TX_ADAPT_MAIN_THRESH 0x0d0
+#define USB3_V5_5NM_UNI_QSERDES_RX_VGA_CAL_CNTRL1 0x0d4
+#define USB3_V5_5NM_UNI_QSERDES_RX_VGA_CAL_CNTRL2 0x0d8
+#define USB3_V5_5NM_UNI_QSERDES_RX_GM_CAL 0x0dc
+#define USB3_V5_5NM_UNI_QSERDES_RX_RX_VGA_GAIN2_LSB 0x0e0
+#define USB3_V5_5NM_UNI_QSERDES_RX_RX_VGA_GAIN2_MSB 0x0e4
+#define USB3_V5_5NM_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8
+#define USB3_V5_5NM_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec
+#define USB3_V5_5NM_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0
+#define USB3_V5_5NM_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4
+#define USB3_V5_5NM_UNI_QSERDES_RX_RX_IDAC_TSETTLE_LOW 0x0f8
+#define USB3_V5_5NM_UNI_QSERDES_RX_RX_IDAC_TSETTLE_HIGH 0x0fc
+#define USB3_V5_5NM_UNI_QSERDES_RX_RX_IDAC_MEASURE_TIME 0x100
+#define USB3_V5_5NM_UNI_QSERDES_RX_RX_IDAC_ACCUMULATOR 0x104
+#define USB3_V5_5NM_UNI_QSERDES_RX_RX_EQ_OFFSET_LSB 0x108
+#define USB3_V5_5NM_UNI_QSERDES_RX_RX_EQ_OFFSET_MSB 0x10c
+#define USB3_V5_5NM_UNI_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110
+#define USB3_V5_5NM_UNI_QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114
+#define USB3_V5_5NM_UNI_QSERDES_RX_SIGDET_ENABLES 0x118
+#define USB3_V5_5NM_UNI_QSERDES_RX_SIGDET_CNTRL 0x11c
+#define USB3_V5_5NM_UNI_QSERDES_RX_SIGDET_LVL 0x120
+#define USB3_V5_5NM_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x124
+#define USB3_V5_5NM_UNI_QSERDES_RX_RX_BAND 0x128
+#define USB3_V5_5NM_UNI_QSERDES_RX_CDR_FREEZE_UP_DN 0x12c
+#define USB3_V5_5NM_UNI_QSERDES_RX_CDR_RESET_OVERRIDE 0x130
+#define USB3_V5_5NM_UNI_QSERDES_RX_RX_INTERFACE_MODE 0x134
+#define USB3_V5_5NM_UNI_QSERDES_RX_JITTER_GEN_MODE 0x138
+#define USB3_V5_5NM_UNI_QSERDES_RX_SJ_AMP1 0x13c
+#define USB3_V5_5NM_UNI_QSERDES_RX_SJ_AMP2 0x140
+#define USB3_V5_5NM_UNI_QSERDES_RX_SJ_PER1 0x144
+#define USB3_V5_5NM_UNI_QSERDES_RX_SJ_PER2 0x148
+#define USB3_V5_5NM_UNI_QSERDES_RX_PPM_OFFSET1 0x14c
+#define USB3_V5_5NM_UNI_QSERDES_RX_PPM_OFFSET2 0x150
+#define USB3_V5_5NM_UNI_QSERDES_RX_SIGN_PPM_PERIOD1 0x154
+#define USB3_V5_5NM_UNI_QSERDES_RX_SIGN_PPM_PERIOD2 0x158
+#define USB3_V5_5NM_UNI_QSERDES_RX_RX_MODE_00_LOW 0x15c
+#define USB3_V5_5NM_UNI_QSERDES_RX_RX_MODE_00_HIGH 0x160
+#define USB3_V5_5NM_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0x164
+#define USB3_V5_5NM_UNI_QSERDES_RX_RX_MODE_00_HIGH3 0x168
+#define USB3_V5_5NM_UNI_QSERDES_RX_RX_MODE_00_HIGH4 0x16c
+#define USB3_V5_5NM_UNI_QSERDES_RX_RX_MODE_01_LOW 0x170
+#define USB3_V5_5NM_UNI_QSERDES_RX_RX_MODE_01_HIGH 0x174
+#define USB3_V5_5NM_UNI_QSERDES_RX_RX_MODE_01_HIGH2 0x178
+#define USB3_V5_5NM_UNI_QSERDES_RX_RX_MODE_01_HIGH3 0x17c
+#define USB3_V5_5NM_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0x180
+#define USB3_V5_5NM_UNI_QSERDES_RX_RX_MODE_10_LOW 0x184
+#define USB3_V5_5NM_UNI_QSERDES_RX_RX_MODE_10_HIGH 0x188
+#define USB3_V5_5NM_UNI_QSERDES_RX_RX_MODE_10_HIGH2 0x18c
+#define USB3_V5_5NM_UNI_QSERDES_RX_RX_MODE_10_HIGH3 0x190
+#define USB3_V5_5NM_UNI_QSERDES_RX_RX_MODE_10_HIGH4 0x194
+#define USB3_V5_5NM_UNI_QSERDES_RX_PHPRE_CTRL 0x198
+#define USB3_V5_5NM_UNI_QSERDES_RX_PHPRE_INITVAL 0x19c
+#define USB3_V5_5NM_UNI_QSERDES_RX_DFE_EN_TIMER 0x1a0
+#define USB3_V5_5NM_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4
+#define USB3_V5_5NM_UNI_QSERDES_RX_DCC_CTRL1 0x1a8
+#define USB3_V5_5NM_UNI_QSERDES_RX_DCC_CTRL2 0x1ac
+#define USB3_V5_5NM_UNI_QSERDES_RX_VTH_CODE 0x1b0
+#define USB3_V5_5NM_UNI_QSERDES_RX_VTH_MIN_THRESH 0x1b4
+#define USB3_V5_5NM_UNI_QSERDES_RX_VTH_MAX_THRESH 0x1b8
+#define USB3_V5_5NM_UNI_QSERDES_RX_ALOG_OBSV_BUS_CTRL_1 0x1bc
+#define USB3_V5_5NM_UNI_QSERDES_RX_PI_CTRL1 0x1c0
+#define USB3_V5_5NM_UNI_QSERDES_RX_PI_CTRL2 0x1c4
+#define USB3_V5_5NM_UNI_QSERDES_RX_PI_QUAD 0x1c8
+#define USB3_V5_5NM_UNI_QSERDES_RX_IDATA1 0x1cc
+#define USB3_V5_5NM_UNI_QSERDES_RX_IDATA2 0x1d0
+#define USB3_V5_5NM_UNI_QSERDES_RX_AUX_DATA1 0x1d4
+#define USB3_V5_5NM_UNI_QSERDES_RX_AUX_DATA2 0x1d8
+#define USB3_V5_5NM_UNI_QSERDES_RX_AC_JTAG_OUTP 0x1dc
+#define USB3_V5_5NM_UNI_QSERDES_RX_AC_JTAG_OUTN 0x1e0
+#define USB3_V5_5NM_UNI_QSERDES_RX_RX_SIGDET 0x1e4
+#define USB3_V5_5NM_UNI_QSERDES_RX_ALOG_OBSV_BUS_STATUS_1 0x1e8
+
+/* Module: USB3_UNI_PCS_LN_PCIE_USB3_UNI_PCS_LANE */
+#define USB3_V5_5NM_UNI_PCS_LN_PCS_STATUS1 0x00
+#define USB3_V5_5NM_UNI_PCS_LN_PCS_STATUS2 0x04
+#define USB3_V5_5NM_UNI_PCS_LN_PCS_STATUS2_CLEAR 0x08
+#define USB3_V5_5NM_UNI_PCS_LN_PCS_STATUS3 0x0c
+#define USB3_V5_5NM_UNI_PCS_LN_BIST_CHK_ERR_CNT_L_STATUS 0x10
+#define USB3_V5_5NM_UNI_PCS_LN_BIST_CHK_ERR_CNT_H_STATUS 0x14
+#define USB3_V5_5NM_UNI_PCS_LN_BIST_CHK_STATUS 0x18
+#define USB3_V5_5NM_UNI_PCS_LN_INSIG_SW_CTRL1 0x1c
+#define USB3_V5_5NM_UNI_PCS_LN_INSIG_MX_CTRL1 0x20
+#define USB3_V5_5NM_UNI_PCS_LN_OUTSIG_SW_CTRL1 0x24
+#define USB3_V5_5NM_UNI_PCS_LN_OUTSIG_MX_CTRL1 0x28
+#define USB3_V5_5NM_UNI_PCS_LN_TEST_CONTROL1 0x2c
+#define USB3_V5_5NM_UNI_PCS_LN_BIST_CTRL 0x30
+#define USB3_V5_5NM_UNI_PCS_LN_PRBS_SEED0 0x34
+#define USB3_V5_5NM_UNI_PCS_LN_PRBS_SEED1 0x38
+#define USB3_V5_5NM_UNI_PCS_LN_FIXED_PAT_CTRL 0x3c
+#define USB3_V5_5NM_UNI_PCS_LN_EQ_CONFIG 0x40
+#define USB3_V5_5NM_UNI_PCS_LN_TEST_CONTROL2 0x44
+#define USB3_V5_5NM_UNI_PCS_LN_TEST_CONTROL3 0x48
+
+/* Module: USB3_UNI_PCS_PCIE_LN_PCIE_USB3_UNI_PCS_PCIE_LANE */
+#define USB3_V5_5NM_UNI_PCS_PCIE_LN_PRESET_OVERRIDE_PRE_POST 0x00
+#define USB3_V5_5NM_UNI_PCS_PCIE_LN_PRESET_OVERRIDE_PRE_POST_RS 0x04
+#define USB3_V5_5NM_UNI_PCS_PCIE_LN_PRESET_OVERRIDE_EN 0x08
+#define USB3_V5_5NM_UNI_PCS_PCIE_LN_PRESET_DSBL_L 0x0c
+#define USB3_V5_5NM_UNI_PCS_PCIE_LN_PRESET_DSBL_H 0x10
+#define USB3_V5_5NM_UNI_PCS_PCIE_LN_LANE_OFF_CONFIG 0x14
+#define USB3_V5_5NM_UNI_PCS_PCIE_LN_RXEQ_DONE_CONFIG1 0x18
+#define USB3_V5_5NM_UNI_PCS_PCIE_LN_RXEQ_DONE_CONFIG2 0x1c
+#define USB3_V5_5NM_UNI_PCS_PCIE_LN_PCIE_PCS_STATUS 0x20
+#define USB3_V5_5NM_UNI_PCS_PCIE_LN_INSIG_SW_CTRL2 0x24
+#define USB3_V5_5NM_UNI_PCS_PCIE_LN_INSIG_MX_CTRL2 0x28
+
+/* Module: USB3_UNI_PHY_PCIE_USB3_UNI_PCS_PCIE_USB3_UNI_PCS_PCIE_USB3_UNI_PCS */
+#define USB3_V5_5NM_UNI_PCS_SW_RESET 0x000
+#define USB3_V5_5NM_UNI_PCS_REVISION_ID0 0x004
+#define USB3_V5_5NM_UNI_PCS_REVISION_ID1 0x008
+#define USB3_V5_5NM_UNI_PCS_REVISION_ID2 0x00c
+#define USB3_V5_5NM_UNI_PCS_REVISION_ID3 0x010
+#define USB3_V5_5NM_UNI_PCS_PCS_STATUS1 0x014
+#define USB3_V5_5NM_UNI_PCS_PCS_STATUS2 0x018
+#define USB3_V5_5NM_UNI_PCS_PCS_STATUS3 0x01c
+#define USB3_V5_5NM_UNI_PCS_PCS_STATUS4 0x020
+#define USB3_V5_5NM_UNI_PCS_PCS_STATUS5 0x024
+#define USB3_V5_5NM_UNI_PCS_PCS_STATUS6 0x028
+#define USB3_V5_5NM_UNI_PCS_PCS_STATUS7 0x02c
+#define USB3_V5_5NM_UNI_PCS_DEBUG_BUS_0_STATUS 0x030
+#define USB3_V5_5NM_UNI_PCS_DEBUG_BUS_1_STATUS 0x034
+#define USB3_V5_5NM_UNI_PCS_DEBUG_BUS_2_STATUS 0x038
+#define USB3_V5_5NM_UNI_PCS_DEBUG_BUS_3_STATUS 0x03c
+#define USB3_V5_5NM_UNI_PCS_POWER_DOWN_CONTROL 0x040
+#define USB3_V5_5NM_UNI_PCS_START_CONTROL 0x044
+#define USB3_V5_5NM_UNI_PCS_INSIG_SW_CTRL1 0x048
+#define USB3_V5_5NM_UNI_PCS_INSIG_SW_CTRL2 0x04c
+#define USB3_V5_5NM_UNI_PCS_INSIG_SW_CTRL3 0x050
+#define USB3_V5_5NM_UNI_PCS_INSIG_SW_CTRL4 0x054
+#define USB3_V5_5NM_UNI_PCS_INSIG_SW_CTRL5 0x058
+#define USB3_V5_5NM_UNI_PCS_INSIG_SW_CTRL6 0x05c
+#define USB3_V5_5NM_UNI_PCS_INSIG_SW_CTRL7 0x060
+#define USB3_V5_5NM_UNI_PCS_INSIG_SW_CTRL8 0x064
+#define USB3_V5_5NM_UNI_PCS_INSIG_MX_CTRL1 0x068
+#define USB3_V5_5NM_UNI_PCS_INSIG_MX_CTRL2 0x06c
+#define USB3_V5_5NM_UNI_PCS_INSIG_MX_CTRL3 0x070
+#define USB3_V5_5NM_UNI_PCS_INSIG_MX_CTRL4 0x074
+#define USB3_V5_5NM_UNI_PCS_INSIG_MX_CTRL5 0x078
+#define USB3_V5_5NM_UNI_PCS_INSIG_MX_CTRL7 0x07c
+#define USB3_V5_5NM_UNI_PCS_INSIG_MX_CTRL8 0x080
+#define USB3_V5_5NM_UNI_PCS_OUTSIG_SW_CTRL1 0x084
+#define USB3_V5_5NM_UNI_PCS_OUTSIG_MX_CTRL1 0x088
+#define USB3_V5_5NM_UNI_PCS_CLAMP_ENABLE 0x08c
+#define USB3_V5_5NM_UNI_PCS_POWER_STATE_CONFIG1 0x090
+#define USB3_V5_5NM_UNI_PCS_POWER_STATE_CONFIG2 0x094
+#define USB3_V5_5NM_UNI_PCS_FLL_CNTRL1 0x098
+#define USB3_V5_5NM_UNI_PCS_FLL_CNTRL2 0x09c
+#define USB3_V5_5NM_UNI_PCS_FLL_CNT_VAL_L 0x0a0
+#define USB3_V5_5NM_UNI_PCS_FLL_CNT_VAL_H_TOL 0x0a4
+#define USB3_V5_5NM_UNI_PCS_FLL_MAN_CODE 0x0a8
+#define USB3_V5_5NM_UNI_PCS_TEST_CONTROL1 0x0ac
+#define USB3_V5_5NM_UNI_PCS_TEST_CONTROL2 0x0b0
+#define USB3_V5_5NM_UNI_PCS_TEST_CONTROL3 0x0b4
+#define USB3_V5_5NM_UNI_PCS_TEST_CONTROL4 0x0b8
+#define USB3_V5_5NM_UNI_PCS_TEST_CONTROL5 0x0bc
+#define USB3_V5_5NM_UNI_PCS_TEST_CONTROL6 0x0c0
+#define USB3_V5_5NM_UNI_PCS_LOCK_DETECT_CONFIG1 0x0c4
+#define USB3_V5_5NM_UNI_PCS_LOCK_DETECT_CONFIG2 0x0c8
+#define USB3_V5_5NM_UNI_PCS_LOCK_DETECT_CONFIG3 0x0cc
+#define USB3_V5_5NM_UNI_PCS_LOCK_DETECT_CONFIG4 0x0d0
+#define USB3_V5_5NM_UNI_PCS_LOCK_DETECT_CONFIG5 0x0d4
+#define USB3_V5_5NM_UNI_PCS_LOCK_DETECT_CONFIG6 0x0d8
+#define USB3_V5_5NM_UNI_PCS_REFGEN_REQ_CONFIG1 0x0dc
+#define USB3_V5_5NM_UNI_PCS_REFGEN_REQ_CONFIG2 0x0e0
+#define USB3_V5_5NM_UNI_PCS_REFGEN_REQ_CONFIG3 0x0e4
+#define USB3_V5_5NM_UNI_PCS_BIST_CTRL 0x0e8
+#define USB3_V5_5NM_UNI_PCS_PRBS_POLY0 0x0ec
+#define USB3_V5_5NM_UNI_PCS_PRBS_POLY1 0x0f0
+#define USB3_V5_5NM_UNI_PCS_FIXED_PAT0 0x0f4
+#define USB3_V5_5NM_UNI_PCS_FIXED_PAT1 0x0f8
+#define USB3_V5_5NM_UNI_PCS_FIXED_PAT2 0x0fc
+#define USB3_V5_5NM_UNI_PCS_FIXED_PAT3 0x100
+#define USB3_V5_5NM_UNI_PCS_FIXED_PAT4 0x104
+#define USB3_V5_5NM_UNI_PCS_FIXED_PAT5 0x108
+#define USB3_V5_5NM_UNI_PCS_FIXED_PAT6 0x10c
+#define USB3_V5_5NM_UNI_PCS_FIXED_PAT7 0x110
+#define USB3_V5_5NM_UNI_PCS_FIXED_PAT8 0x114
+#define USB3_V5_5NM_UNI_PCS_FIXED_PAT9 0x118
+#define USB3_V5_5NM_UNI_PCS_FIXED_PAT10 0x11c
+#define USB3_V5_5NM_UNI_PCS_FIXED_PAT11 0x120
+#define USB3_V5_5NM_UNI_PCS_FIXED_PAT12 0x124
+#define USB3_V5_5NM_UNI_PCS_FIXED_PAT13 0x128
+#define USB3_V5_5NM_UNI_PCS_FIXED_PAT14 0x12c
+#define USB3_V5_5NM_UNI_PCS_FIXED_PAT15 0x130
+#define USB3_V5_5NM_UNI_PCS_TXMGN_CONFIG 0x134
+#define USB3_V5_5NM_UNI_PCS_G12S1_TXMGN_V0 0x138
+#define USB3_V5_5NM_UNI_PCS_G12S1_TXMGN_V1 0x13c
+#define USB3_V5_5NM_UNI_PCS_G12S1_TXMGN_V2 0x140
+#define USB3_V5_5NM_UNI_PCS_G12S1_TXMGN_V3 0x144
+#define USB3_V5_5NM_UNI_PCS_G12S1_TXMGN_V4 0x148
+#define USB3_V5_5NM_UNI_PCS_G12S1_TXMGN_V0_RS 0x14c
+#define USB3_V5_5NM_UNI_PCS_G12S1_TXMGN_V1_RS 0x150
+#define USB3_V5_5NM_UNI_PCS_G12S1_TXMGN_V2_RS 0x154
+#define USB3_V5_5NM_UNI_PCS_G12S1_TXMGN_V3_RS 0x158
+#define USB3_V5_5NM_UNI_PCS_G12S1_TXMGN_V4_RS 0x15c
+#define USB3_V5_5NM_UNI_PCS_G3S2_TXMGN_MAIN 0x160
+#define USB3_V5_5NM_UNI_PCS_G3S2_TXMGN_MAIN_RS 0x164
+#define USB3_V5_5NM_UNI_PCS_G12S1_TXDEEMPH_M6DB 0x168
+#define USB3_V5_5NM_UNI_PCS_G12S1_TXDEEMPH_M3P5DB 0x16c
+#define USB3_V5_5NM_UNI_PCS_G3S2_PRE_GAIN 0x170
+#define USB3_V5_5NM_UNI_PCS_G3S2_POST_GAIN 0x174
+#define USB3_V5_5NM_UNI_PCS_G3S2_PRE_POST_OFFSET 0x178
+#define USB3_V5_5NM_UNI_PCS_G3S2_PRE_GAIN_RS 0x17c
+#define USB3_V5_5NM_UNI_PCS_G3S2_POST_GAIN_RS 0x180
+#define USB3_V5_5NM_UNI_PCS_G3S2_PRE_POST_OFFSET_RS 0x184
+#define USB3_V5_5NM_UNI_PCS_RX_SIGDET_LVL 0x188
+#define USB3_V5_5NM_UNI_PCS_RX_SIGDET_DTCT_CNTRL 0x18c
+#define USB3_V5_5NM_UNI_PCS_RCVR_DTCT_DLY_P1U2_L 0x190
+#define USB3_V5_5NM_UNI_PCS_RCVR_DTCT_DLY_P1U2_H 0x194
+#define USB3_V5_5NM_UNI_PCS_RATE_SLEW_CNTRL1 0x198
+#define USB3_V5_5NM_UNI_PCS_RATE_SLEW_CNTRL2 0x19c
+#define USB3_V5_5NM_UNI_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x1a0
+#define USB3_V5_5NM_UNI_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4
+#define USB3_V5_5NM_UNI_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8
+#define USB3_V5_5NM_UNI_PCS_TSYNC_RSYNC_TIME 0x1ac
+#define USB3_V5_5NM_UNI_PCS_CDR_RESET_TIME 0x1b0
+#define USB3_V5_5NM_UNI_PCS_TSYNC_DLY_TIME 0x1b4
+#define USB3_V5_5NM_UNI_PCS_ELECIDLE_DLY_SEL 0x1b8
+#define USB3_V5_5NM_UNI_PCS_CMN_ACK_OUT_SEL 0x1bc
+#define USB3_V5_5NM_UNI_PCS_ALIGN_DETECT_CONFIG1 0x1c0
+#define USB3_V5_5NM_UNI_PCS_ALIGN_DETECT_CONFIG2 0x1c4
+#define USB3_V5_5NM_UNI_PCS_ALIGN_DETECT_CONFIG3 0x1c8
+#define USB3_V5_5NM_UNI_PCS_ALIGN_DETECT_CONFIG4 0x1cc
+#define USB3_V5_5NM_UNI_PCS_PCS_TX_RX_CONFIG 0x1d0
+#define USB3_V5_5NM_UNI_PCS_RX_IDLE_DTCT_CNTRL 0x1d4
+#define USB3_V5_5NM_UNI_PCS_RX_DCC_CAL_CONFIG 0x1d8
+#define USB3_V5_5NM_UNI_PCS_EQ_CONFIG1 0x1dc
+#define USB3_V5_5NM_UNI_PCS_EQ_CONFIG2 0x1e0
+#define USB3_V5_5NM_UNI_PCS_EQ_CONFIG3 0x1e4
+#define USB3_V5_5NM_UNI_PCS_EQ_CONFIG4 0x1e8
+#define USB3_V5_5NM_UNI_PCS_EQ_CONFIG5 0x1ec
+
+/* Module: USB3_UNI_PHY_PCIE_PCS */
+#define USB3_V5_5NM_UNI_PCS_PCIE_INT_AUX_CLK_STATUS 0x00
+#define USB3_V5_5NM_UNI_PCS_PCIE_OSC_DTCT_STATUS 0x04
+#define USB3_V5_5NM_UNI_PCS_PCIE_POWER_STATE_CONFIG1 0x08
+#define USB3_V5_5NM_UNI_PCS_PCIE_POWER_STATE_CONFIG2 0x0c
+#define USB3_V5_5NM_UNI_PCS_PCIE_POWER_STATE_CONFIG3 0x10
+#define USB3_V5_5NM_UNI_PCS_PCIE_POWER_STATE_CONFIG4 0x14
+#define USB3_V5_5NM_UNI_PCS_PCIE_POWER_STATE_CONFIG5 0x18
+#define USB3_V5_5NM_UNI_PCS_PCIE_PCS_TX_RX_CONFIG 0x1c
+#define USB3_V5_5NM_UNI_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20
+#define USB3_V5_5NM_UNI_PCS_PCIE_ENDPOINT_REFCLK_CNTRL 0x24
+#define USB3_V5_5NM_UNI_PCS_PCIE_EPCLK_PRE_PLL_LOCK_DLY_AUXCLK 0x28
+#define USB3_V5_5NM_UNI_PCS_PCIE_EPCLK_DLY_COUNT_VAL_L 0x2c
+#define USB3_V5_5NM_UNI_PCS_PCIE_EPCLK_DLY_COUNT_VAL_H 0x30
+#define USB3_V5_5NM_UNI_PCS_PCIE_RX_IDLE_DTCT_CNTRL1 0x34
+#define USB3_V5_5NM_UNI_PCS_PCIE_RX_IDLE_DTCT_CNTRL2 0x38
+#define USB3_V5_5NM_UNI_PCS_PCIE_SIGDET_CNTRL 0x3c
+#define USB3_V5_5NM_UNI_PCS_PCIE_SIGDET_LOW_2_IDLE_TIME 0x40
+#define USB3_V5_5NM_UNI_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x44
+#define USB3_V5_5NM_UNI_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0x48
+#define USB3_V5_5NM_UNI_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x4c
+#define USB3_V5_5NM_UNI_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H 0x50
+#define USB3_V5_5NM_UNI_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x54
+#define USB3_V5_5NM_UNI_PCS_PCIE_INT_AUX_CLK_CONFIG2 0x58
+#define USB3_V5_5NM_UNI_PCS_PCIE_OSC_DTCT_CONFIG1 0x5c
+#define USB3_V5_5NM_UNI_PCS_PCIE_OSC_DTCT_CONFIG2 0x60
+#define USB3_V5_5NM_UNI_PCS_PCIE_OSC_DTCT_CONFIG3 0x64
+#define USB3_V5_5NM_UNI_PCS_PCIE_OSC_DTCT_CONFIG4 0x68
+#define USB3_V5_5NM_UNI_PCS_PCIE_OSC_DTCT_CONFIG5 0x6c
+#define USB3_V5_5NM_UNI_PCS_PCIE_OSC_DTCT_CONFIG6 0x70
+#define USB3_V5_5NM_UNI_PCS_PCIE_OSC_DTCT_CONFIG7 0x74
+#define USB3_V5_5NM_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG1 0x78
+#define USB3_V5_5NM_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 0x7c
+#define USB3_V5_5NM_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG3 0x80
+#define USB3_V5_5NM_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 0x84
+#define USB3_V5_5NM_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x88
+#define USB3_V5_5NM_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6 0x8c
+#define USB3_V5_5NM_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG7 0x90
+#define USB3_V5_5NM_UNI_PCS_PCIE_OSC_DTCT_ACTIONS 0x94
+#define USB3_V5_5NM_UNI_PCS_PCIE_LOCAL_FS 0x98
+#define USB3_V5_5NM_UNI_PCS_PCIE_LOCAL_LF 0x9c
+#define USB3_V5_5NM_UNI_PCS_PCIE_LOCAL_FS_RS 0xa0
+#define USB3_V5_5NM_UNI_PCS_PCIE_EQ_CONFIG1 0xa4
+#define USB3_V5_5NM_UNI_PCS_PCIE_EQ_CONFIG2 0xa8
+#define USB3_V5_5NM_UNI_PCS_PCIE_PRESET_P0_P1_PRE 0xac
+#define USB3_V5_5NM_UNI_PCS_PCIE_PRESET_P2_P3_PRE 0xb0
+#define USB3_V5_5NM_UNI_PCS_PCIE_PRESET_P4_P5_PRE 0xb4
+#define USB3_V5_5NM_UNI_PCS_PCIE_PRESET_P6_P7_PRE 0xb8
+#define USB3_V5_5NM_UNI_PCS_PCIE_PRESET_P8_P9_PRE 0xbc
+#define USB3_V5_5NM_UNI_PCS_PCIE_PRESET_P10_PRE 0xc0
+#define USB3_V5_5NM_UNI_PCS_PCIE_PRESET_P1_P3_PRE_RS 0xc4
+#define USB3_V5_5NM_UNI_PCS_PCIE_PRESET_P4_P5_PRE_RS 0xc8
+#define USB3_V5_5NM_UNI_PCS_PCIE_PRESET_P6_P9_PRE_RS 0xcc
+#define USB3_V5_5NM_UNI_PCS_PCIE_PRESET_P0_P1_POST 0xd0
+#define USB3_V5_5NM_UNI_PCS_PCIE_PRESET_P2_P3_POST 0xd4
+#define USB3_V5_5NM_UNI_PCS_PCIE_PRESET_P4_P5_POST 0xd8
+#define USB3_V5_5NM_UNI_PCS_PCIE_PRESET_P6_P7_POST 0xdc
+#define USB3_V5_5NM_UNI_PCS_PCIE_PRESET_P8_P9_POST 0xe0
+#define USB3_V5_5NM_UNI_PCS_PCIE_PRESET_P10_POST 0xe4
+#define USB3_V5_5NM_UNI_PCS_PCIE_PRESET_P1_P3_POST_RS 0xe8
+#define USB3_V5_5NM_UNI_PCS_PCIE_PRESET_P4_P5_POST_RS 0xec
+#define USB3_V5_5NM_UNI_PCS_PCIE_PRESET_P6_P9_POST_RS 0xf0
+#define USB3_V5_5NM_UNI_PCS_PCIE_RXEQEVAL_TIME 0xf4
+
+/* Module: USB3_UNI_PHY_PCIE_PCS_DEBUG_INTGEN */
+#define USB3_V5_5NM_UNI_PCS_INTGEN_INTGEN_STATUS1 0x00
+#define USB3_V5_5NM_UNI_PCS_INTGEN_INTGEN_STATUS2 0x04
+#define USB3_V5_5NM_UNI_PCS_INTGEN_CONFIG1 0x08
+#define USB3_V5_5NM_UNI_PCS_INTGEN_SIGNALBLK1_CONFIG1 0x0c
+#define USB3_V5_5NM_UNI_PCS_INTGEN_SIGNALBLK1_CONFIG2 0x10
+#define USB3_V5_5NM_UNI_PCS_INTGEN_SIGNALBLK1_CONFIG3 0x14
+#define USB3_V5_5NM_UNI_PCS_INTGEN_SIGNALBLK1_CONFIG4 0x18
+#define USB3_V5_5NM_UNI_PCS_INTGEN_SIGNALBLK1_CONFIG5 0x1c
+#define USB3_V5_5NM_UNI_PCS_INTGEN_SIGNALBLK2_CONFIG1 0x20
+#define USB3_V5_5NM_UNI_PCS_INTGEN_SIGNALBLK2_CONFIG2 0x24
+#define USB3_V5_5NM_UNI_PCS_INTGEN_SIGNALBLK2_CONFIG3 0x28
+#define USB3_V5_5NM_UNI_PCS_INTGEN_SIGNALBLK2_CONFIG4 0x2c
+#define USB3_V5_5NM_UNI_PCS_INTGEN_SIGNALBLK2_CONFIG5 0x30
+#define USB3_V5_5NM_UNI_PCS_INTGEN_STRINGBLK1_CONFIG1 0x34
+#define USB3_V5_5NM_UNI_PCS_INTGEN_STRINGBLK1_CONFIG2 0x38
+#define USB3_V5_5NM_UNI_PCS_INTGEN_STRINGBLK1_CONFIG3 0x3c
+#define USB3_V5_5NM_UNI_PCS_INTGEN_STRINGBLK1_CONFIG4 0x40
+#define USB3_V5_5NM_UNI_PCS_INTGEN_STRINGBLK1_CONFIG5 0x44
+#define USB3_V5_5NM_UNI_PCS_INTGEN_STRINGBLK2_CONFIG1 0x48
+#define USB3_V5_5NM_UNI_PCS_INTGEN_STRINGBLK2_CONFIG2 0x4c
+#define USB3_V5_5NM_UNI_PCS_INTGEN_STRINGBLK2_CONFIG3 0x50
+#define USB3_V5_5NM_UNI_PCS_INTGEN_STRINGBLK2_CONFIG4 0x54
+#define USB3_V5_5NM_UNI_PCS_INTGEN_STRINGBLK2_CONFIG5 0x58
+
+
+/* Module: USB3_UNI_PCS_USB3_PCIE_USB3_UNI_PCS_USB3 */
+#define USB3_V5_5NM_UNI_PCS_USB3_POWER_STATE_CONFIG1 0x00
+#define USB3_V5_5NM_UNI_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x04
+#define USB3_V5_5NM_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x08
+#define USB3_V5_5NM_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x0c
+#define USB3_V5_5NM_UNI_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x10
+#define USB3_V5_5NM_UNI_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x14
+#define USB3_V5_5NM_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x18
+#define USB3_V5_5NM_UNI_PCS_USB3_LFPS_TX_ECSTART 0x1c
+#define USB3_V5_5NM_UNI_PCS_USB3_LFPS_PER_TIMER_VAL 0x20
+#define USB3_V5_5NM_UNI_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x24
+#define USB3_V5_5NM_UNI_PCS_USB3_LFPS_CONFIG1 0x28
+#define USB3_V5_5NM_UNI_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x2c
+#define USB3_V5_5NM_UNI_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x30
+#define USB3_V5_5NM_UNI_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x34
+#define USB3_V5_5NM_UNI_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x38
+#define USB3_V5_5NM_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x3c
+#define USB3_V5_5NM_UNI_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x40
+#define USB3_V5_5NM_UNI_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x44
+#define USB3_V5_5NM_UNI_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x48
+#define USB3_V5_5NM_UNI_PCS_USB3_ARCVR_DTCT_CM_DLY 0x4c
+#define USB3_V5_5NM_UNI_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x50
+#define USB3_V5_5NM_UNI_PCS_USB3_ALFPS_DEGLITCH_VAL 0x54
+#define USB3_V5_5NM_UNI_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x58
+#define USB3_V5_5NM_UNI_PCS_USB3_TEST_CONTROL 0x5c
+#define USB3_V5_5NM_UNI_PCS_USB3_RXTERMINATION_DLY_SEL 0x60
+
+#endif
--
2.35.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v2 2/5] phy: qcom-qmp: Add USB3 5NM QMP UNI registers
2022-06-07 21:35 ` [PATCH v2 2/5] phy: qcom-qmp: Add USB3 5NM QMP UNI registers Bjorn Andersson
@ 2022-06-07 21:58 ` Dmitry Baryshkov
2022-06-07 22:45 ` Bjorn Andersson
0 siblings, 1 reply; 16+ messages in thread
From: Dmitry Baryshkov @ 2022-06-07 21:58 UTC (permalink / raw)
To: Bjorn Andersson, Kishon Vijay Abraham I, Vinod Koul, Manu Gautam
Cc: Rob Herring, Krzysztof Kozlowski, linux-arm-msm, linux-phy,
devicetree, linux-kernel
On 08/06/2022 00:35, Bjorn Andersson wrote:
> Add all registers defines from qcom,usb3-5nm-qmp-uni.h of the msm-5.4
> kernel. Offsets are adjusted to be relative to each sub-block, as we
> describe the individual pieces in the upstream kernel and "V5_5NM" is
> injected in the defines to avoid colliding with existing and future
> constants.
>
> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---
>
> Changes since v1:
> - Added "V5" to the defines, per discussion with Vinod.
>
> .../phy/qualcomm/phy-qcom-usb3-5nm-qmp-uni.h | 617 ++++++++++++++++++
> 1 file changed, 617 insertions(+)
> create mode 100644 drivers/phy/qualcomm/phy-qcom-usb3-5nm-qmp-uni.h
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-usb3-5nm-qmp-uni.h b/drivers/phy/qualcomm/phy-qcom-usb3-5nm-qmp-uni.h
> new file mode 100644
> index 000000000000..304c21167388
> --- /dev/null
> +++ b/drivers/phy/qualcomm/phy-qcom-usb3-5nm-qmp-uni.h
> @@ -0,0 +1,617 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2020, The Linux Foundation. All rights reserved.
> + */
> +
> +#ifndef PHY_QCOM_USB3_V5_5NM_QMP_UNI_H_
> +#define PHY_QCOM_USB3_V5_5NM_QMP_UNI_H_
> +
> +/* Module: USB3_UNI_PHY_QSERDES_COM_QSERDES_COM_PCIE_USB3_UNI_QMP_PLL */
> +#define USB3_V5_5NM_UNI_QSERDES_COM_ATB_SEL1 0x000
> +#define USB3_V5_5NM_UNI_QSERDES_COM_ATB_SEL2 0x004
> +#define USB3_V5_5NM_UNI_QSERDES_COM_FREQ_UPDATE 0x008
> +#define USB3_V5_5NM_UNI_QSERDES_COM_BG_TIMER 0x00c
> +#define USB3_V5_5NM_UNI_QSERDES_COM_SSC_EN_CENTER 0x010
> +#define USB3_V5_5NM_UNI_QSERDES_COM_SSC_ADJ_PER1 0x014
> +#define USB3_V5_5NM_UNI_QSERDES_COM_SSC_ADJ_PER2 0x018
> +#define USB3_V5_5NM_UNI_QSERDES_COM_SSC_PER1 0x01c
> +#define USB3_V5_5NM_UNI_QSERDES_COM_SSC_PER2 0x020
> +#define USB3_V5_5NM_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0x024
> +#define USB3_V5_5NM_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x028
> +#define USB3_V5_5NM_UNI_QSERDES_COM_SSC_STEP_SIZE3_MODE0 0x02c
> +#define USB3_V5_5NM_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0x030
> +#define USB3_V5_5NM_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x034
> +#define USB3_V5_5NM_UNI_QSERDES_COM_SSC_STEP_SIZE3_MODE1 0x038
> +#define USB3_V5_5NM_UNI_QSERDES_COM_POST_DIV 0x03c
> +#define USB3_V5_5NM_UNI_QSERDES_COM_POST_DIV_MUX 0x040
> +#define USB3_V5_5NM_UNI_QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x044
> +#define USB3_V5_5NM_UNI_QSERDES_COM_CLK_ENABLE1 0x048
> +#define USB3_V5_5NM_UNI_QSERDES_COM_SYS_CLK_CTRL 0x04c
> +#define USB3_V5_5NM_UNI_QSERDES_COM_SYSCLK_BUF_ENABLE 0x050
> +#define USB3_V5_5NM_UNI_QSERDES_COM_PLL_EN 0x054
> +#define USB3_V5_5NM_UNI_QSERDES_COM_PLL_IVCO 0x058
> +#define USB3_V5_5NM_UNI_QSERDES_COM_CMN_IETRIM 0x05c
> +#define USB3_V5_5NM_UNI_QSERDES_COM_CMN_IPTRIM 0x060
> +#define USB3_V5_5NM_UNI_QSERDES_COM_EP_CLOCK_DETECT_CTRL 0x064
> +#define USB3_V5_5NM_UNI_QSERDES_COM_SYSCLK_DET_COMP_STATUS 0x068
> +#define USB3_V5_5NM_UNI_QSERDES_COM_CLK_EP_DIV_MODE0 0x06c
> +#define USB3_V5_5NM_UNI_QSERDES_COM_CLK_EP_DIV_MODE1 0x070
> +#define USB3_V5_5NM_UNI_QSERDES_COM_CP_CTRL_MODE0 0x074
> +#define USB3_V5_5NM_UNI_QSERDES_COM_CP_CTRL_MODE1 0x078
> +#define USB3_V5_5NM_UNI_QSERDES_COM_PLL_RCTRL_MODE0 0x07c
> +#define USB3_V5_5NM_UNI_QSERDES_COM_PLL_RCTRL_MODE1 0x080
> +#define USB3_V5_5NM_UNI_QSERDES_COM_PLL_CCTRL_MODE0 0x084
> +#define USB3_V5_5NM_UNI_QSERDES_COM_PLL_CCTRL_MODE1 0x088
> +#define USB3_V5_5NM_UNI_QSERDES_COM_PLL_CNTRL 0x08c
> +#define USB3_V5_5NM_UNI_QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x090
> +#define USB3_V5_5NM_UNI_QSERDES_COM_SYSCLK_EN_SEL 0x094
> +#define USB3_V5_5NM_UNI_QSERDES_COM_CML_SYSCLK_SEL 0x098
> +#define USB3_V5_5NM_UNI_QSERDES_COM_RESETSM_CNTRL 0x09c
> +#define USB3_V5_5NM_UNI_QSERDES_COM_RESETSM_CNTRL2 0x0a0
> +#define USB3_V5_5NM_UNI_QSERDES_COM_LOCK_CMP_EN 0x0a4
> +#define USB3_V5_5NM_UNI_QSERDES_COM_LOCK_CMP_CFG 0x0a8
> +#define USB3_V5_5NM_UNI_QSERDES_COM_LOCK_CMP1_MODE0 0x0ac
> +#define USB3_V5_5NM_UNI_QSERDES_COM_LOCK_CMP2_MODE0 0x0b0
> +#define USB3_V5_5NM_UNI_QSERDES_COM_LOCK_CMP1_MODE1 0x0b4
> +#define USB3_V5_5NM_UNI_QSERDES_COM_LOCK_CMP2_MODE1 0x0b8
> +#define USB3_V5_5NM_UNI_QSERDES_COM_DEC_START_MODE0 0x0bc
> +#define USB3_V5_5NM_UNI_QSERDES_COM_DEC_START_MSB_MODE0 0x0c0
> +#define USB3_V5_5NM_UNI_QSERDES_COM_DEC_START_MODE1 0x0c4
> +#define USB3_V5_5NM_UNI_QSERDES_COM_DEC_START_MSB_MODE1 0x0c8
> +#define USB3_V5_5NM_UNI_QSERDES_COM_DIV_FRAC_START1_MODE0 0x0cc
> +#define USB3_V5_5NM_UNI_QSERDES_COM_DIV_FRAC_START2_MODE0 0x0d0
> +#define USB3_V5_5NM_UNI_QSERDES_COM_DIV_FRAC_START3_MODE0 0x0d4
> +#define USB3_V5_5NM_UNI_QSERDES_COM_DIV_FRAC_START1_MODE1 0x0d8
> +#define USB3_V5_5NM_UNI_QSERDES_COM_DIV_FRAC_START2_MODE1 0x0dc
> +#define USB3_V5_5NM_UNI_QSERDES_COM_DIV_FRAC_START3_MODE1 0x0e0
> +#define USB3_V5_5NM_UNI_QSERDES_COM_INTEGLOOP_INITVAL 0x0e4
> +#define USB3_V5_5NM_UNI_QSERDES_COM_INTEGLOOP_EN 0x0e8
> +#define USB3_V5_5NM_UNI_QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x0ec
> +#define USB3_V5_5NM_UNI_QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x0f0
> +#define USB3_V5_5NM_UNI_QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x0f4
> +#define USB3_V5_5NM_UNI_QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x0f8
> +#define USB3_V5_5NM_UNI_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0 0x0fc
> +#define USB3_V5_5NM_UNI_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1 0x100
> +#define USB3_V5_5NM_UNI_QSERDES_COM_VCOCAL_DEADMAN_CTRL 0x104
> +#define USB3_V5_5NM_UNI_QSERDES_COM_VCO_TUNE_CTRL 0x108
> +#define USB3_V5_5NM_UNI_QSERDES_COM_VCO_TUNE_MAP 0x10c
> +#define USB3_V5_5NM_UNI_QSERDES_COM_VCO_TUNE1_MODE0 0x110
> +#define USB3_V5_5NM_UNI_QSERDES_COM_VCO_TUNE2_MODE0 0x114
> +#define USB3_V5_5NM_UNI_QSERDES_COM_VCO_TUNE1_MODE1 0x118
> +#define USB3_V5_5NM_UNI_QSERDES_COM_VCO_TUNE2_MODE1 0x11c
> +#define USB3_V5_5NM_UNI_QSERDES_COM_VCO_TUNE_INITVAL1 0x120
> +#define USB3_V5_5NM_UNI_QSERDES_COM_VCO_TUNE_INITVAL2 0x124
> +#define USB3_V5_5NM_UNI_QSERDES_COM_VCO_TUNE_MINVAL1 0x128
> +#define USB3_V5_5NM_UNI_QSERDES_COM_VCO_TUNE_MINVAL2 0x12c
> +#define USB3_V5_5NM_UNI_QSERDES_COM_VCO_TUNE_MAXVAL1 0x130
> +#define USB3_V5_5NM_UNI_QSERDES_COM_VCO_TUNE_MAXVAL2 0x134
> +#define USB3_V5_5NM_UNI_QSERDES_COM_VCO_TUNE_TIMER1 0x138
> +#define USB3_V5_5NM_UNI_QSERDES_COM_VCO_TUNE_TIMER2 0x13c
> +#define USB3_V5_5NM_UNI_QSERDES_COM_CMN_STATUS 0x140
> +#define USB3_V5_5NM_UNI_QSERDES_COM_RESET_SM_STATUS 0x144
> +#define USB3_V5_5NM_UNI_QSERDES_COM_RESTRIM_CODE_STATUS 0x148
> +#define USB3_V5_5NM_UNI_QSERDES_COM_PLLCAL_CODE1_STATUS 0x14c
> +#define USB3_V5_5NM_UNI_QSERDES_COM_PLLCAL_CODE2_STATUS 0x150
> +#define USB3_V5_5NM_UNI_QSERDES_COM_CLK_SELECT 0x154
> +#define USB3_V5_5NM_UNI_QSERDES_COM_HSCLK_SEL 0x158
> +#define USB3_V5_5NM_UNI_QSERDES_COM_HSCLK_HS_SWITCH_SEL 0x15c
> +#define USB3_V5_5NM_UNI_QSERDES_COM_INTEGLOOP_BINCODE_STATUS 0x160
> +#define USB3_V5_5NM_UNI_QSERDES_COM_PLL_ANALOG 0x164
> +#define USB3_V5_5NM_UNI_QSERDES_COM_CORECLK_DIV_MODE0 0x168
> +#define USB3_V5_5NM_UNI_QSERDES_COM_CORECLK_DIV_MODE1 0x16c
> +#define USB3_V5_5NM_UNI_QSERDES_COM_SW_RESET 0x170
> +#define USB3_V5_5NM_UNI_QSERDES_COM_CORE_CLK_EN 0x174
> +#define USB3_V5_5NM_UNI_QSERDES_COM_C_READY_STATUS 0x178
> +#define USB3_V5_5NM_UNI_QSERDES_COM_CMN_CONFIG 0x17c
> +#define USB3_V5_5NM_UNI_QSERDES_COM_CMN_RATE_OVERRIDE 0x180
> +#define USB3_V5_5NM_UNI_QSERDES_COM_SVS_MODE_CLK_SEL 0x184
> +#define USB3_V5_5NM_UNI_QSERDES_COM_DEBUG_BUS0 0x188
> +#define USB3_V5_5NM_UNI_QSERDES_COM_DEBUG_BUS1 0x18c
> +#define USB3_V5_5NM_UNI_QSERDES_COM_DEBUG_BUS2 0x190
> +#define USB3_V5_5NM_UNI_QSERDES_COM_DEBUG_BUS3 0x194
> +#define USB3_V5_5NM_UNI_QSERDES_COM_DEBUG_BUS_SEL 0x198
> +#define USB3_V5_5NM_UNI_QSERDES_COM_CMN_MISC1 0x19c
> +#define USB3_V5_5NM_UNI_QSERDES_COM_CMN_MODE 0x1a0
> +#define USB3_V5_5NM_UNI_QSERDES_COM_CMN_MODE_CONTD 0x1a4
> +#define USB3_V5_5NM_UNI_QSERDES_COM_VCO_DC_LEVEL_CTRL 0x1a8
> +#define USB3_V5_5NM_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac
> +#define USB3_V5_5NM_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0
> +#define USB3_V5_5NM_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4
> +#define USB3_V5_5NM_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8
> +#define USB3_V5_5NM_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc
> +#define USB3_V5_5NM_UNI_QSERDES_COM_RESERVED_1 0x1c0
> +#define USB3_V5_5NM_UNI_QSERDES_COM_MODE_OPERATION_STATUS 0x1c4
These defines look completely compatible with the existing ones in the
QSERDES_V5_COM_ namespace. Please use them instead.
> +
> +/* Module: USB3_UNI_PHY_QSERDES_TX_PCIE_USB3_UNI_QMP_TX */
> +#define USB3_V5_5NM_UNI_QSERDES_TX_BIST_MODE_LANENO 0x000
> +#define USB3_V5_5NM_UNI_QSERDES_TX_BIST_INVERT 0x004
> +#define USB3_V5_5NM_UNI_QSERDES_TX_CLKBUF_ENABLE 0x008
> +#define USB3_V5_5NM_UNI_QSERDES_TX_TX_EMP_POST1_LVL 0x00c
> +#define USB3_V5_5NM_UNI_QSERDES_TX_TX_IDLE_LVL_LARGE_AMP 0x010
> +#define USB3_V5_5NM_UNI_QSERDES_TX_TX_DRV_LVL 0x014
> +#define USB3_V5_5NM_UNI_QSERDES_TX_TX_DRV_LVL_OFFSET 0x018
> +#define USB3_V5_5NM_UNI_QSERDES_TX_RESET_TSYNC_EN 0x01c
> +#define USB3_V5_5NM_UNI_QSERDES_TX_PRE_STALL_LDO_BOOST_EN 0x020
> +#define USB3_V5_5NM_UNI_QSERDES_TX_TX_BAND 0x024
> +#define USB3_V5_5NM_UNI_QSERDES_TX_SLEW_CNTL 0x028
> +#define USB3_V5_5NM_UNI_QSERDES_TX_INTERFACE_SELECT 0x02c
> +#define USB3_V5_5NM_UNI_QSERDES_TX_LPB_EN 0x030
> +#define USB3_V5_5NM_UNI_QSERDES_TX_RES_CODE_LANE_TX 0x034
> +#define USB3_V5_5NM_UNI_QSERDES_TX_RES_CODE_LANE_RX 0x038
> +#define USB3_V5_5NM_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x03c
> +#define USB3_V5_5NM_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_RX 0x040
> +#define USB3_V5_5NM_UNI_QSERDES_TX_PERL_LENGTH1 0x044
> +#define USB3_V5_5NM_UNI_QSERDES_TX_PERL_LENGTH2 0x048
> +#define USB3_V5_5NM_UNI_QSERDES_TX_SERDES_BYP_EN_OUT 0x04c
> +#define USB3_V5_5NM_UNI_QSERDES_TX_DEBUG_BUS_SEL 0x050
> +#define USB3_V5_5NM_UNI_QSERDES_TX_TRANSCEIVER_BIAS_EN 0x054
> +#define USB3_V5_5NM_UNI_QSERDES_TX_HIGHZ_DRVR_EN 0x058
> +#define USB3_V5_5NM_UNI_QSERDES_TX_TX_POL_INV 0x05c
> +#define USB3_V5_5NM_UNI_QSERDES_TX_PARRATE_REC_DETECT_IDLE_EN 0x060
> +#define USB3_V5_5NM_UNI_QSERDES_TX_BIST_PATTERN1 0x064
> +#define USB3_V5_5NM_UNI_QSERDES_TX_BIST_PATTERN2 0x068
> +#define USB3_V5_5NM_UNI_QSERDES_TX_BIST_PATTERN3 0x06c
> +#define USB3_V5_5NM_UNI_QSERDES_TX_BIST_PATTERN4 0x070
> +#define USB3_V5_5NM_UNI_QSERDES_TX_BIST_PATTERN5 0x074
> +#define USB3_V5_5NM_UNI_QSERDES_TX_BIST_PATTERN6 0x078
> +#define USB3_V5_5NM_UNI_QSERDES_TX_BIST_PATTERN7 0x07c
> +#define USB3_V5_5NM_UNI_QSERDES_TX_BIST_PATTERN8 0x080
> +#define USB3_V5_5NM_UNI_QSERDES_TX_LANE_MODE_1 0x084
> +#define USB3_V5_5NM_UNI_QSERDES_TX_LANE_MODE_2 0x088
> +#define USB3_V5_5NM_UNI_QSERDES_TX_LANE_MODE_3 0x08c
> +#define USB3_V5_5NM_UNI_QSERDES_TX_LANE_MODE_4 0x090
> +#define USB3_V5_5NM_UNI_QSERDES_TX_LANE_MODE_5 0x094
> +#define USB3_V5_5NM_UNI_QSERDES_TX_ATB_SEL1 0x098
> +#define USB3_V5_5NM_UNI_QSERDES_TX_ATB_SEL2 0x09c
> +#define USB3_V5_5NM_UNI_QSERDES_TX_RCV_DETECT_LVL 0x0a0
> +#define USB3_V5_5NM_UNI_QSERDES_TX_RCV_DETECT_LVL_2 0x0a4
> +#define USB3_V5_5NM_UNI_QSERDES_TX_PRBS_SEED1 0x0a8
> +#define USB3_V5_5NM_UNI_QSERDES_TX_PRBS_SEED2 0x0ac
> +#define USB3_V5_5NM_UNI_QSERDES_TX_PRBS_SEED3 0x0b0
> +#define USB3_V5_5NM_UNI_QSERDES_TX_PRBS_SEED4 0x0b4
> +#define USB3_V5_5NM_UNI_QSERDES_TX_RESET_GEN 0x0b8
> +#define USB3_V5_5NM_UNI_QSERDES_TX_RESET_GEN_MUXES 0x0bc
> +#define USB3_V5_5NM_UNI_QSERDES_TX_TRAN_DRVR_EMP_EN 0x0c0
> +#define USB3_V5_5NM_UNI_QSERDES_TX_TX_INTERFACE_MODE 0x0c4
> +#define USB3_V5_5NM_UNI_QSERDES_TX_VMODE_CTRL1 0x0c8
> +#define USB3_V5_5NM_UNI_QSERDES_TX_ALOG_OBSV_BUS_CTRL_1 0x0cc
> +#define USB3_V5_5NM_UNI_QSERDES_TX_BIST_STATUS 0x0d0
> +#define USB3_V5_5NM_UNI_QSERDES_TX_BIST_ERROR_COUNT1 0x0d4
> +#define USB3_V5_5NM_UNI_QSERDES_TX_BIST_ERROR_COUNT2 0x0d8
> +#define USB3_V5_5NM_UNI_QSERDES_TX_ALOG_OBSV_BUS_STATUS_1 0x0dc
> +#define USB3_V5_5NM_UNI_QSERDES_TX_LANE_DIG_CONFIG 0x0e0
> +#define USB3_V5_5NM_UNI_QSERDES_TX_PI_QEC_CTRL 0x0e4
> +#define USB3_V5_5NM_UNI_QSERDES_TX_PRE_EMPH 0x0e8
> +#define USB3_V5_5NM_UNI_QSERDES_TX_SW_RESET 0x0ec
> +#define USB3_V5_5NM_UNI_QSERDES_TX_DCC_OFFSET 0x0f0
> +#define USB3_V5_5NM_UNI_QSERDES_TX_DCC_CMUX_POSTCAL_OFFSET 0x0f4
> +#define USB3_V5_5NM_UNI_QSERDES_TX_DCC_CMUX_CAL_CTRL1 0x0f8
> +#define USB3_V5_5NM_UNI_QSERDES_TX_DCC_CMUX_CAL_CTRL2 0x0fc
> +#define USB3_V5_5NM_UNI_QSERDES_TX_DIG_BKUP_CTRL 0x100
> +#define USB3_V5_5NM_UNI_QSERDES_TX_DEBUG_BUS0 0x104
> +#define USB3_V5_5NM_UNI_QSERDES_TX_DEBUG_BUS1 0x108
> +#define USB3_V5_5NM_UNI_QSERDES_TX_DEBUG_BUS2 0x10c
> +#define USB3_V5_5NM_UNI_QSERDES_TX_DEBUG_BUS3 0x110
> +#define USB3_V5_5NM_UNI_QSERDES_TX_READ_EQCODE 0x114
> +#define USB3_V5_5NM_UNI_QSERDES_TX_READ_OFFSETCODE 0x118
> +#define USB3_V5_5NM_UNI_QSERDES_TX_IA_ERROR_COUNTER_LOW 0x11c
> +#define USB3_V5_5NM_UNI_QSERDES_TX_IA_ERROR_COUNTER_HIGH 0x120
> +#define USB3_V5_5NM_UNI_QSERDES_TX_VGA_READ_CODE 0x124
> +#define USB3_V5_5NM_UNI_QSERDES_TX_VTH_READ_CODE 0x128
> +#define USB3_V5_5NM_UNI_QSERDES_TX_DFE_TAP1_READ_CODE 0x12c
> +#define USB3_V5_5NM_UNI_QSERDES_TX_DFE_TAP2_READ_CODE 0x130
> +#define USB3_V5_5NM_UNI_QSERDES_TX_IDAC_STATUS_I 0x134
> +#define USB3_V5_5NM_UNI_QSERDES_TX_IDAC_STATUS_IBAR 0x138
> +#define USB3_V5_5NM_UNI_QSERDES_TX_IDAC_STATUS_Q 0x13c
> +#define USB3_V5_5NM_UNI_QSERDES_TX_IDAC_STATUS_QBAR 0x140
> +#define USB3_V5_5NM_UNI_QSERDES_TX_IDAC_STATUS_A 0x144
> +#define USB3_V5_5NM_UNI_QSERDES_TX_IDAC_STATUS_ABAR 0x148
> +#define USB3_V5_5NM_UNI_QSERDES_TX_IDAC_STATUS_SM_ON 0x14c
> +#define USB3_V5_5NM_UNI_QSERDES_TX_IDAC_STATUS_CAL_DONE 0x150
> +#define USB3_V5_5NM_UNI_QSERDES_TX_IDAC_STATUS_SIGNERROR 0x154
> +#define USB3_V5_5NM_UNI_QSERDES_TX_DCC_CAL_STATUS 0x158
> +#define USB3_V5_5NM_UNI_QSERDES_TX_DCC_READ_CODE_STATUS 0x15c
As far as I understand, these ones should fall into the QSERDES_V5_TX_
namespace.
> +
> +/* Module: USB3_UNI_PHY_QSERDES_RX_QSERDES_RX_PCIE_USB3_UNI_QMP_RX */
> +#define USB3_V5_5NM_UNI_QSERDES_RX_UCDR_FO_GAIN_HALF 0x000
> +#define USB3_V5_5NM_UNI_QSERDES_RX_UCDR_FO_GAIN_QUARTER 0x004
> +#define USB3_V5_5NM_UNI_QSERDES_RX_UCDR_FO_GAIN 0x008
> +#define USB3_V5_5NM_UNI_QSERDES_RX_UCDR_SO_GAIN_HALF 0x00c
> +#define USB3_V5_5NM_UNI_QSERDES_RX_UCDR_SO_GAIN_QUARTER 0x010
> +#define USB3_V5_5NM_UNI_QSERDES_RX_UCDR_SO_GAIN 0x014
> +#define USB3_V5_5NM_UNI_QSERDES_RX_UCDR_SVS_FO_GAIN_HALF 0x018
> +#define USB3_V5_5NM_UNI_QSERDES_RX_UCDR_SVS_FO_GAIN_QUARTER 0x01c
> +#define USB3_V5_5NM_UNI_QSERDES_RX_UCDR_SVS_FO_GAIN 0x020
> +#define USB3_V5_5NM_UNI_QSERDES_RX_UCDR_SVS_SO_GAIN_HALF 0x024
> +#define USB3_V5_5NM_UNI_QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER 0x028
> +#define USB3_V5_5NM_UNI_QSERDES_RX_UCDR_SVS_SO_GAIN 0x02c
> +#define USB3_V5_5NM_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x030
> +#define USB3_V5_5NM_UNI_QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034
> +#define USB3_V5_5NM_UNI_QSERDES_RX_UCDR_FO_TO_SO_DELAY 0x038
> +#define USB3_V5_5NM_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c
> +#define USB3_V5_5NM_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040
> +#define USB3_V5_5NM_UNI_QSERDES_RX_UCDR_PI_CONTROLS 0x044
> +#define USB3_V5_5NM_UNI_QSERDES_RX_UCDR_PI_CTRL2 0x048
> +#define USB3_V5_5NM_UNI_QSERDES_RX_UCDR_SB2_THRESH1 0x04c
> +#define USB3_V5_5NM_UNI_QSERDES_RX_UCDR_SB2_THRESH2 0x050
> +#define USB3_V5_5NM_UNI_QSERDES_RX_UCDR_SB2_GAIN1 0x054
> +#define USB3_V5_5NM_UNI_QSERDES_RX_UCDR_SB2_GAIN2 0x058
> +#define USB3_V5_5NM_UNI_QSERDES_RX_AUX_CONTROL 0x05c
> +#define USB3_V5_5NM_UNI_QSERDES_RX_AUX_DATA_TCOARSE_TFINE 0x060
> +#define USB3_V5_5NM_UNI_QSERDES_RX_RCLK_AUXDATA_SEL 0x064
> +#define USB3_V5_5NM_UNI_QSERDES_RX_AC_JTAG_ENABLE 0x068
> +#define USB3_V5_5NM_UNI_QSERDES_RX_AC_JTAG_INITP 0x06c
> +#define USB3_V5_5NM_UNI_QSERDES_RX_AC_JTAG_INITN 0x070
> +#define USB3_V5_5NM_UNI_QSERDES_RX_AC_JTAG_LVL 0x074
> +#define USB3_V5_5NM_UNI_QSERDES_RX_AC_JTAG_MODE 0x078
> +#define USB3_V5_5NM_UNI_QSERDES_RX_AC_JTAG_RESET 0x07c
> +#define USB3_V5_5NM_UNI_QSERDES_RX_RX_TERM_BW 0x080
> +#define USB3_V5_5NM_UNI_QSERDES_RX_RX_RCVR_IQ_EN 0x084
> +#define USB3_V5_5NM_UNI_QSERDES_RX_RX_IDAC_I_DC_OFFSETS 0x088
> +#define USB3_V5_5NM_UNI_QSERDES_RX_RX_IDAC_IBAR_DC_OFFSETS 0x08c
> +#define USB3_V5_5NM_UNI_QSERDES_RX_RX_IDAC_Q_DC_OFFSETS 0x090
> +#define USB3_V5_5NM_UNI_QSERDES_RX_RX_IDAC_QBAR_DC_OFFSETS 0x094
> +#define USB3_V5_5NM_UNI_QSERDES_RX_RX_IDAC_A_DC_OFFSETS 0x098
> +#define USB3_V5_5NM_UNI_QSERDES_RX_RX_IDAC_ABAR_DC_OFFSETS 0x09c
> +#define USB3_V5_5NM_UNI_QSERDES_RX_RX_IDAC_EN 0x0a0
> +#define USB3_V5_5NM_UNI_QSERDES_RX_RX_IDAC_ENABLES 0x0a4
> +#define USB3_V5_5NM_UNI_QSERDES_RX_RX_IDAC_SIGN 0x0a8
> +#define USB3_V5_5NM_UNI_QSERDES_RX_RX_HIGHZ_HIGHRATE 0x0ac
> +#define USB3_V5_5NM_UNI_QSERDES_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x0b0
> +#define USB3_V5_5NM_UNI_QSERDES_RX_DFE_1 0x0b4
> +#define USB3_V5_5NM_UNI_QSERDES_RX_DFE_2 0x0b8
> +#define USB3_V5_5NM_UNI_QSERDES_RX_DFE_3 0x0bc
> +#define USB3_V5_5NM_UNI_QSERDES_RX_DFE_4 0x0c0
> +#define USB3_V5_5NM_UNI_QSERDES_RX_TX_ADAPT_PRE_THRESH1 0x0c4
> +#define USB3_V5_5NM_UNI_QSERDES_RX_TX_ADAPT_PRE_THRESH2 0x0c8
> +#define USB3_V5_5NM_UNI_QSERDES_RX_TX_ADAPT_POST_THRESH 0x0cc
> +#define USB3_V5_5NM_UNI_QSERDES_RX_TX_ADAPT_MAIN_THRESH 0x0d0
> +#define USB3_V5_5NM_UNI_QSERDES_RX_VGA_CAL_CNTRL1 0x0d4
> +#define USB3_V5_5NM_UNI_QSERDES_RX_VGA_CAL_CNTRL2 0x0d8
> +#define USB3_V5_5NM_UNI_QSERDES_RX_GM_CAL 0x0dc
> +#define USB3_V5_5NM_UNI_QSERDES_RX_RX_VGA_GAIN2_LSB 0x0e0
> +#define USB3_V5_5NM_UNI_QSERDES_RX_RX_VGA_GAIN2_MSB 0x0e4
> +#define USB3_V5_5NM_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8
> +#define USB3_V5_5NM_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec
> +#define USB3_V5_5NM_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0
> +#define USB3_V5_5NM_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4
> +#define USB3_V5_5NM_UNI_QSERDES_RX_RX_IDAC_TSETTLE_LOW 0x0f8
> +#define USB3_V5_5NM_UNI_QSERDES_RX_RX_IDAC_TSETTLE_HIGH 0x0fc
> +#define USB3_V5_5NM_UNI_QSERDES_RX_RX_IDAC_MEASURE_TIME 0x100
> +#define USB3_V5_5NM_UNI_QSERDES_RX_RX_IDAC_ACCUMULATOR 0x104
> +#define USB3_V5_5NM_UNI_QSERDES_RX_RX_EQ_OFFSET_LSB 0x108
> +#define USB3_V5_5NM_UNI_QSERDES_RX_RX_EQ_OFFSET_MSB 0x10c
> +#define USB3_V5_5NM_UNI_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110
> +#define USB3_V5_5NM_UNI_QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114
> +#define USB3_V5_5NM_UNI_QSERDES_RX_SIGDET_ENABLES 0x118
> +#define USB3_V5_5NM_UNI_QSERDES_RX_SIGDET_CNTRL 0x11c
> +#define USB3_V5_5NM_UNI_QSERDES_RX_SIGDET_LVL 0x120
> +#define USB3_V5_5NM_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x124
> +#define USB3_V5_5NM_UNI_QSERDES_RX_RX_BAND 0x128
> +#define USB3_V5_5NM_UNI_QSERDES_RX_CDR_FREEZE_UP_DN 0x12c
> +#define USB3_V5_5NM_UNI_QSERDES_RX_CDR_RESET_OVERRIDE 0x130
> +#define USB3_V5_5NM_UNI_QSERDES_RX_RX_INTERFACE_MODE 0x134
> +#define USB3_V5_5NM_UNI_QSERDES_RX_JITTER_GEN_MODE 0x138
> +#define USB3_V5_5NM_UNI_QSERDES_RX_SJ_AMP1 0x13c
> +#define USB3_V5_5NM_UNI_QSERDES_RX_SJ_AMP2 0x140
> +#define USB3_V5_5NM_UNI_QSERDES_RX_SJ_PER1 0x144
> +#define USB3_V5_5NM_UNI_QSERDES_RX_SJ_PER2 0x148
> +#define USB3_V5_5NM_UNI_QSERDES_RX_PPM_OFFSET1 0x14c
> +#define USB3_V5_5NM_UNI_QSERDES_RX_PPM_OFFSET2 0x150
> +#define USB3_V5_5NM_UNI_QSERDES_RX_SIGN_PPM_PERIOD1 0x154
> +#define USB3_V5_5NM_UNI_QSERDES_RX_SIGN_PPM_PERIOD2 0x158
> +#define USB3_V5_5NM_UNI_QSERDES_RX_RX_MODE_00_LOW 0x15c
> +#define USB3_V5_5NM_UNI_QSERDES_RX_RX_MODE_00_HIGH 0x160
> +#define USB3_V5_5NM_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0x164
> +#define USB3_V5_5NM_UNI_QSERDES_RX_RX_MODE_00_HIGH3 0x168
> +#define USB3_V5_5NM_UNI_QSERDES_RX_RX_MODE_00_HIGH4 0x16c
> +#define USB3_V5_5NM_UNI_QSERDES_RX_RX_MODE_01_LOW 0x170
> +#define USB3_V5_5NM_UNI_QSERDES_RX_RX_MODE_01_HIGH 0x174
> +#define USB3_V5_5NM_UNI_QSERDES_RX_RX_MODE_01_HIGH2 0x178
> +#define USB3_V5_5NM_UNI_QSERDES_RX_RX_MODE_01_HIGH3 0x17c
> +#define USB3_V5_5NM_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0x180
> +#define USB3_V5_5NM_UNI_QSERDES_RX_RX_MODE_10_LOW 0x184
> +#define USB3_V5_5NM_UNI_QSERDES_RX_RX_MODE_10_HIGH 0x188
> +#define USB3_V5_5NM_UNI_QSERDES_RX_RX_MODE_10_HIGH2 0x18c
> +#define USB3_V5_5NM_UNI_QSERDES_RX_RX_MODE_10_HIGH3 0x190
> +#define USB3_V5_5NM_UNI_QSERDES_RX_RX_MODE_10_HIGH4 0x194
> +#define USB3_V5_5NM_UNI_QSERDES_RX_PHPRE_CTRL 0x198
> +#define USB3_V5_5NM_UNI_QSERDES_RX_PHPRE_INITVAL 0x19c
> +#define USB3_V5_5NM_UNI_QSERDES_RX_DFE_EN_TIMER 0x1a0
> +#define USB3_V5_5NM_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4
> +#define USB3_V5_5NM_UNI_QSERDES_RX_DCC_CTRL1 0x1a8
> +#define USB3_V5_5NM_UNI_QSERDES_RX_DCC_CTRL2 0x1ac
> +#define USB3_V5_5NM_UNI_QSERDES_RX_VTH_CODE 0x1b0
> +#define USB3_V5_5NM_UNI_QSERDES_RX_VTH_MIN_THRESH 0x1b4
> +#define USB3_V5_5NM_UNI_QSERDES_RX_VTH_MAX_THRESH 0x1b8
> +#define USB3_V5_5NM_UNI_QSERDES_RX_ALOG_OBSV_BUS_CTRL_1 0x1bc
> +#define USB3_V5_5NM_UNI_QSERDES_RX_PI_CTRL1 0x1c0
> +#define USB3_V5_5NM_UNI_QSERDES_RX_PI_CTRL2 0x1c4
> +#define USB3_V5_5NM_UNI_QSERDES_RX_PI_QUAD 0x1c8
> +#define USB3_V5_5NM_UNI_QSERDES_RX_IDATA1 0x1cc
> +#define USB3_V5_5NM_UNI_QSERDES_RX_IDATA2 0x1d0
> +#define USB3_V5_5NM_UNI_QSERDES_RX_AUX_DATA1 0x1d4
> +#define USB3_V5_5NM_UNI_QSERDES_RX_AUX_DATA2 0x1d8
> +#define USB3_V5_5NM_UNI_QSERDES_RX_AC_JTAG_OUTP 0x1dc
> +#define USB3_V5_5NM_UNI_QSERDES_RX_AC_JTAG_OUTN 0x1e0
> +#define USB3_V5_5NM_UNI_QSERDES_RX_RX_SIGDET 0x1e4
> +#define USB3_V5_5NM_UNI_QSERDES_RX_ALOG_OBSV_BUS_STATUS_1 0x1e8
QSERDES_V5_RX_foo.
> +
> +/* Module: USB3_UNI_PCS_LN_PCIE_USB3_UNI_PCS_LANE */
> +#define USB3_V5_5NM_UNI_PCS_LN_PCS_STATUS1 0x00
> +#define USB3_V5_5NM_UNI_PCS_LN_PCS_STATUS2 0x04
> +#define USB3_V5_5NM_UNI_PCS_LN_PCS_STATUS2_CLEAR 0x08
> +#define USB3_V5_5NM_UNI_PCS_LN_PCS_STATUS3 0x0c
> +#define USB3_V5_5NM_UNI_PCS_LN_BIST_CHK_ERR_CNT_L_STATUS 0x10
> +#define USB3_V5_5NM_UNI_PCS_LN_BIST_CHK_ERR_CNT_H_STATUS 0x14
> +#define USB3_V5_5NM_UNI_PCS_LN_BIST_CHK_STATUS 0x18
> +#define USB3_V5_5NM_UNI_PCS_LN_INSIG_SW_CTRL1 0x1c
> +#define USB3_V5_5NM_UNI_PCS_LN_INSIG_MX_CTRL1 0x20
> +#define USB3_V5_5NM_UNI_PCS_LN_OUTSIG_SW_CTRL1 0x24
> +#define USB3_V5_5NM_UNI_PCS_LN_OUTSIG_MX_CTRL1 0x28
> +#define USB3_V5_5NM_UNI_PCS_LN_TEST_CONTROL1 0x2c
> +#define USB3_V5_5NM_UNI_PCS_LN_BIST_CTRL 0x30
> +#define USB3_V5_5NM_UNI_PCS_LN_PRBS_SEED0 0x34
> +#define USB3_V5_5NM_UNI_PCS_LN_PRBS_SEED1 0x38
> +#define USB3_V5_5NM_UNI_PCS_LN_FIXED_PAT_CTRL 0x3c
> +#define USB3_V5_5NM_UNI_PCS_LN_EQ_CONFIG 0x40
> +#define USB3_V5_5NM_UNI_PCS_LN_TEST_CONTROL2 0x44
> +#define USB3_V5_5NM_UNI_PCS_LN_TEST_CONTROL3 0x48
> +
> +/* Module: USB3_UNI_PCS_PCIE_LN_PCIE_USB3_UNI_PCS_PCIE_LANE */
> +#define USB3_V5_5NM_UNI_PCS_PCIE_LN_PRESET_OVERRIDE_PRE_POST 0x00
> +#define USB3_V5_5NM_UNI_PCS_PCIE_LN_PRESET_OVERRIDE_PRE_POST_RS 0x04
> +#define USB3_V5_5NM_UNI_PCS_PCIE_LN_PRESET_OVERRIDE_EN 0x08
> +#define USB3_V5_5NM_UNI_PCS_PCIE_LN_PRESET_DSBL_L 0x0c
> +#define USB3_V5_5NM_UNI_PCS_PCIE_LN_PRESET_DSBL_H 0x10
> +#define USB3_V5_5NM_UNI_PCS_PCIE_LN_LANE_OFF_CONFIG 0x14
> +#define USB3_V5_5NM_UNI_PCS_PCIE_LN_RXEQ_DONE_CONFIG1 0x18
> +#define USB3_V5_5NM_UNI_PCS_PCIE_LN_RXEQ_DONE_CONFIG2 0x1c
> +#define USB3_V5_5NM_UNI_PCS_PCIE_LN_PCIE_PCS_STATUS 0x20
> +#define USB3_V5_5NM_UNI_PCS_PCIE_LN_INSIG_SW_CTRL2 0x24
> +#define USB3_V5_5NM_UNI_PCS_PCIE_LN_INSIG_MX_CTRL2 0x28
> +
> +/* Module: USB3_UNI_PHY_PCIE_USB3_UNI_PCS_PCIE_USB3_UNI_PCS_PCIE_USB3_UNI_PCS */
> +#define USB3_V5_5NM_UNI_PCS_SW_RESET 0x000
> +#define USB3_V5_5NM_UNI_PCS_REVISION_ID0 0x004
> +#define USB3_V5_5NM_UNI_PCS_REVISION_ID1 0x008
> +#define USB3_V5_5NM_UNI_PCS_REVISION_ID2 0x00c
> +#define USB3_V5_5NM_UNI_PCS_REVISION_ID3 0x010
> +#define USB3_V5_5NM_UNI_PCS_PCS_STATUS1 0x014
> +#define USB3_V5_5NM_UNI_PCS_PCS_STATUS2 0x018
> +#define USB3_V5_5NM_UNI_PCS_PCS_STATUS3 0x01c
> +#define USB3_V5_5NM_UNI_PCS_PCS_STATUS4 0x020
> +#define USB3_V5_5NM_UNI_PCS_PCS_STATUS5 0x024
> +#define USB3_V5_5NM_UNI_PCS_PCS_STATUS6 0x028
> +#define USB3_V5_5NM_UNI_PCS_PCS_STATUS7 0x02c
> +#define USB3_V5_5NM_UNI_PCS_DEBUG_BUS_0_STATUS 0x030
> +#define USB3_V5_5NM_UNI_PCS_DEBUG_BUS_1_STATUS 0x034
> +#define USB3_V5_5NM_UNI_PCS_DEBUG_BUS_2_STATUS 0x038
> +#define USB3_V5_5NM_UNI_PCS_DEBUG_BUS_3_STATUS 0x03c
> +#define USB3_V5_5NM_UNI_PCS_POWER_DOWN_CONTROL 0x040
> +#define USB3_V5_5NM_UNI_PCS_START_CONTROL 0x044
> +#define USB3_V5_5NM_UNI_PCS_INSIG_SW_CTRL1 0x048
> +#define USB3_V5_5NM_UNI_PCS_INSIG_SW_CTRL2 0x04c
> +#define USB3_V5_5NM_UNI_PCS_INSIG_SW_CTRL3 0x050
> +#define USB3_V5_5NM_UNI_PCS_INSIG_SW_CTRL4 0x054
> +#define USB3_V5_5NM_UNI_PCS_INSIG_SW_CTRL5 0x058
> +#define USB3_V5_5NM_UNI_PCS_INSIG_SW_CTRL6 0x05c
> +#define USB3_V5_5NM_UNI_PCS_INSIG_SW_CTRL7 0x060
> +#define USB3_V5_5NM_UNI_PCS_INSIG_SW_CTRL8 0x064
> +#define USB3_V5_5NM_UNI_PCS_INSIG_MX_CTRL1 0x068
> +#define USB3_V5_5NM_UNI_PCS_INSIG_MX_CTRL2 0x06c
> +#define USB3_V5_5NM_UNI_PCS_INSIG_MX_CTRL3 0x070
> +#define USB3_V5_5NM_UNI_PCS_INSIG_MX_CTRL4 0x074
> +#define USB3_V5_5NM_UNI_PCS_INSIG_MX_CTRL5 0x078
> +#define USB3_V5_5NM_UNI_PCS_INSIG_MX_CTRL7 0x07c
> +#define USB3_V5_5NM_UNI_PCS_INSIG_MX_CTRL8 0x080
> +#define USB3_V5_5NM_UNI_PCS_OUTSIG_SW_CTRL1 0x084
> +#define USB3_V5_5NM_UNI_PCS_OUTSIG_MX_CTRL1 0x088
> +#define USB3_V5_5NM_UNI_PCS_CLAMP_ENABLE 0x08c
> +#define USB3_V5_5NM_UNI_PCS_POWER_STATE_CONFIG1 0x090
> +#define USB3_V5_5NM_UNI_PCS_POWER_STATE_CONFIG2 0x094
> +#define USB3_V5_5NM_UNI_PCS_FLL_CNTRL1 0x098
> +#define USB3_V5_5NM_UNI_PCS_FLL_CNTRL2 0x09c
> +#define USB3_V5_5NM_UNI_PCS_FLL_CNT_VAL_L 0x0a0
> +#define USB3_V5_5NM_UNI_PCS_FLL_CNT_VAL_H_TOL 0x0a4
> +#define USB3_V5_5NM_UNI_PCS_FLL_MAN_CODE 0x0a8
> +#define USB3_V5_5NM_UNI_PCS_TEST_CONTROL1 0x0ac
> +#define USB3_V5_5NM_UNI_PCS_TEST_CONTROL2 0x0b0
> +#define USB3_V5_5NM_UNI_PCS_TEST_CONTROL3 0x0b4
> +#define USB3_V5_5NM_UNI_PCS_TEST_CONTROL4 0x0b8
> +#define USB3_V5_5NM_UNI_PCS_TEST_CONTROL5 0x0bc
> +#define USB3_V5_5NM_UNI_PCS_TEST_CONTROL6 0x0c0
> +#define USB3_V5_5NM_UNI_PCS_LOCK_DETECT_CONFIG1 0x0c4
> +#define USB3_V5_5NM_UNI_PCS_LOCK_DETECT_CONFIG2 0x0c8
> +#define USB3_V5_5NM_UNI_PCS_LOCK_DETECT_CONFIG3 0x0cc
> +#define USB3_V5_5NM_UNI_PCS_LOCK_DETECT_CONFIG4 0x0d0
> +#define USB3_V5_5NM_UNI_PCS_LOCK_DETECT_CONFIG5 0x0d4
> +#define USB3_V5_5NM_UNI_PCS_LOCK_DETECT_CONFIG6 0x0d8
> +#define USB3_V5_5NM_UNI_PCS_REFGEN_REQ_CONFIG1 0x0dc
> +#define USB3_V5_5NM_UNI_PCS_REFGEN_REQ_CONFIG2 0x0e0
> +#define USB3_V5_5NM_UNI_PCS_REFGEN_REQ_CONFIG3 0x0e4
> +#define USB3_V5_5NM_UNI_PCS_BIST_CTRL 0x0e8
> +#define USB3_V5_5NM_UNI_PCS_PRBS_POLY0 0x0ec
> +#define USB3_V5_5NM_UNI_PCS_PRBS_POLY1 0x0f0
> +#define USB3_V5_5NM_UNI_PCS_FIXED_PAT0 0x0f4
> +#define USB3_V5_5NM_UNI_PCS_FIXED_PAT1 0x0f8
> +#define USB3_V5_5NM_UNI_PCS_FIXED_PAT2 0x0fc
> +#define USB3_V5_5NM_UNI_PCS_FIXED_PAT3 0x100
> +#define USB3_V5_5NM_UNI_PCS_FIXED_PAT4 0x104
> +#define USB3_V5_5NM_UNI_PCS_FIXED_PAT5 0x108
> +#define USB3_V5_5NM_UNI_PCS_FIXED_PAT6 0x10c
> +#define USB3_V5_5NM_UNI_PCS_FIXED_PAT7 0x110
> +#define USB3_V5_5NM_UNI_PCS_FIXED_PAT8 0x114
> +#define USB3_V5_5NM_UNI_PCS_FIXED_PAT9 0x118
> +#define USB3_V5_5NM_UNI_PCS_FIXED_PAT10 0x11c
> +#define USB3_V5_5NM_UNI_PCS_FIXED_PAT11 0x120
> +#define USB3_V5_5NM_UNI_PCS_FIXED_PAT12 0x124
> +#define USB3_V5_5NM_UNI_PCS_FIXED_PAT13 0x128
> +#define USB3_V5_5NM_UNI_PCS_FIXED_PAT14 0x12c
> +#define USB3_V5_5NM_UNI_PCS_FIXED_PAT15 0x130
> +#define USB3_V5_5NM_UNI_PCS_TXMGN_CONFIG 0x134
> +#define USB3_V5_5NM_UNI_PCS_G12S1_TXMGN_V0 0x138
> +#define USB3_V5_5NM_UNI_PCS_G12S1_TXMGN_V1 0x13c
> +#define USB3_V5_5NM_UNI_PCS_G12S1_TXMGN_V2 0x140
> +#define USB3_V5_5NM_UNI_PCS_G12S1_TXMGN_V3 0x144
> +#define USB3_V5_5NM_UNI_PCS_G12S1_TXMGN_V4 0x148
> +#define USB3_V5_5NM_UNI_PCS_G12S1_TXMGN_V0_RS 0x14c
> +#define USB3_V5_5NM_UNI_PCS_G12S1_TXMGN_V1_RS 0x150
> +#define USB3_V5_5NM_UNI_PCS_G12S1_TXMGN_V2_RS 0x154
> +#define USB3_V5_5NM_UNI_PCS_G12S1_TXMGN_V3_RS 0x158
> +#define USB3_V5_5NM_UNI_PCS_G12S1_TXMGN_V4_RS 0x15c
> +#define USB3_V5_5NM_UNI_PCS_G3S2_TXMGN_MAIN 0x160
> +#define USB3_V5_5NM_UNI_PCS_G3S2_TXMGN_MAIN_RS 0x164
> +#define USB3_V5_5NM_UNI_PCS_G12S1_TXDEEMPH_M6DB 0x168
> +#define USB3_V5_5NM_UNI_PCS_G12S1_TXDEEMPH_M3P5DB 0x16c
> +#define USB3_V5_5NM_UNI_PCS_G3S2_PRE_GAIN 0x170
> +#define USB3_V5_5NM_UNI_PCS_G3S2_POST_GAIN 0x174
> +#define USB3_V5_5NM_UNI_PCS_G3S2_PRE_POST_OFFSET 0x178
> +#define USB3_V5_5NM_UNI_PCS_G3S2_PRE_GAIN_RS 0x17c
> +#define USB3_V5_5NM_UNI_PCS_G3S2_POST_GAIN_RS 0x180
> +#define USB3_V5_5NM_UNI_PCS_G3S2_PRE_POST_OFFSET_RS 0x184
> +#define USB3_V5_5NM_UNI_PCS_RX_SIGDET_LVL 0x188
> +#define USB3_V5_5NM_UNI_PCS_RX_SIGDET_DTCT_CNTRL 0x18c
> +#define USB3_V5_5NM_UNI_PCS_RCVR_DTCT_DLY_P1U2_L 0x190
> +#define USB3_V5_5NM_UNI_PCS_RCVR_DTCT_DLY_P1U2_H 0x194
> +#define USB3_V5_5NM_UNI_PCS_RATE_SLEW_CNTRL1 0x198
> +#define USB3_V5_5NM_UNI_PCS_RATE_SLEW_CNTRL2 0x19c
> +#define USB3_V5_5NM_UNI_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x1a0
> +#define USB3_V5_5NM_UNI_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4
> +#define USB3_V5_5NM_UNI_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8
> +#define USB3_V5_5NM_UNI_PCS_TSYNC_RSYNC_TIME 0x1ac
> +#define USB3_V5_5NM_UNI_PCS_CDR_RESET_TIME 0x1b0
> +#define USB3_V5_5NM_UNI_PCS_TSYNC_DLY_TIME 0x1b4
> +#define USB3_V5_5NM_UNI_PCS_ELECIDLE_DLY_SEL 0x1b8
> +#define USB3_V5_5NM_UNI_PCS_CMN_ACK_OUT_SEL 0x1bc
> +#define USB3_V5_5NM_UNI_PCS_ALIGN_DETECT_CONFIG1 0x1c0
> +#define USB3_V5_5NM_UNI_PCS_ALIGN_DETECT_CONFIG2 0x1c4
> +#define USB3_V5_5NM_UNI_PCS_ALIGN_DETECT_CONFIG3 0x1c8
> +#define USB3_V5_5NM_UNI_PCS_ALIGN_DETECT_CONFIG4 0x1cc
> +#define USB3_V5_5NM_UNI_PCS_PCS_TX_RX_CONFIG 0x1d0
> +#define USB3_V5_5NM_UNI_PCS_RX_IDLE_DTCT_CNTRL 0x1d4
> +#define USB3_V5_5NM_UNI_PCS_RX_DCC_CAL_CONFIG 0x1d8
> +#define USB3_V5_5NM_UNI_PCS_EQ_CONFIG1 0x1dc
> +#define USB3_V5_5NM_UNI_PCS_EQ_CONFIG2 0x1e0
> +#define USB3_V5_5NM_UNI_PCS_EQ_CONFIG3 0x1e4
> +#define USB3_V5_5NM_UNI_PCS_EQ_CONFIG4 0x1e8
> +#define USB3_V5_5NM_UNI_PCS_EQ_CONFIG5 0x1ec
QPHY_V5_PCS_
> +
> +/* Module: USB3_UNI_PHY_PCIE_PCS */
> +#define USB3_V5_5NM_UNI_PCS_PCIE_INT_AUX_CLK_STATUS 0x00
> +#define USB3_V5_5NM_UNI_PCS_PCIE_OSC_DTCT_STATUS 0x04
> +#define USB3_V5_5NM_UNI_PCS_PCIE_POWER_STATE_CONFIG1 0x08
> +#define USB3_V5_5NM_UNI_PCS_PCIE_POWER_STATE_CONFIG2 0x0c
> +#define USB3_V5_5NM_UNI_PCS_PCIE_POWER_STATE_CONFIG3 0x10
> +#define USB3_V5_5NM_UNI_PCS_PCIE_POWER_STATE_CONFIG4 0x14
> +#define USB3_V5_5NM_UNI_PCS_PCIE_POWER_STATE_CONFIG5 0x18
> +#define USB3_V5_5NM_UNI_PCS_PCIE_PCS_TX_RX_CONFIG 0x1c
> +#define USB3_V5_5NM_UNI_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20
> +#define USB3_V5_5NM_UNI_PCS_PCIE_ENDPOINT_REFCLK_CNTRL 0x24
> +#define USB3_V5_5NM_UNI_PCS_PCIE_EPCLK_PRE_PLL_LOCK_DLY_AUXCLK 0x28
> +#define USB3_V5_5NM_UNI_PCS_PCIE_EPCLK_DLY_COUNT_VAL_L 0x2c
> +#define USB3_V5_5NM_UNI_PCS_PCIE_EPCLK_DLY_COUNT_VAL_H 0x30
> +#define USB3_V5_5NM_UNI_PCS_PCIE_RX_IDLE_DTCT_CNTRL1 0x34
> +#define USB3_V5_5NM_UNI_PCS_PCIE_RX_IDLE_DTCT_CNTRL2 0x38
> +#define USB3_V5_5NM_UNI_PCS_PCIE_SIGDET_CNTRL 0x3c
> +#define USB3_V5_5NM_UNI_PCS_PCIE_SIGDET_LOW_2_IDLE_TIME 0x40
> +#define USB3_V5_5NM_UNI_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x44
> +#define USB3_V5_5NM_UNI_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0x48
> +#define USB3_V5_5NM_UNI_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x4c
> +#define USB3_V5_5NM_UNI_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H 0x50
> +#define USB3_V5_5NM_UNI_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x54
> +#define USB3_V5_5NM_UNI_PCS_PCIE_INT_AUX_CLK_CONFIG2 0x58
> +#define USB3_V5_5NM_UNI_PCS_PCIE_OSC_DTCT_CONFIG1 0x5c
> +#define USB3_V5_5NM_UNI_PCS_PCIE_OSC_DTCT_CONFIG2 0x60
> +#define USB3_V5_5NM_UNI_PCS_PCIE_OSC_DTCT_CONFIG3 0x64
> +#define USB3_V5_5NM_UNI_PCS_PCIE_OSC_DTCT_CONFIG4 0x68
> +#define USB3_V5_5NM_UNI_PCS_PCIE_OSC_DTCT_CONFIG5 0x6c
> +#define USB3_V5_5NM_UNI_PCS_PCIE_OSC_DTCT_CONFIG6 0x70
> +#define USB3_V5_5NM_UNI_PCS_PCIE_OSC_DTCT_CONFIG7 0x74
> +#define USB3_V5_5NM_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG1 0x78
> +#define USB3_V5_5NM_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 0x7c
> +#define USB3_V5_5NM_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG3 0x80
> +#define USB3_V5_5NM_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 0x84
> +#define USB3_V5_5NM_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x88
> +#define USB3_V5_5NM_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6 0x8c
> +#define USB3_V5_5NM_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG7 0x90
> +#define USB3_V5_5NM_UNI_PCS_PCIE_OSC_DTCT_ACTIONS 0x94
> +#define USB3_V5_5NM_UNI_PCS_PCIE_LOCAL_FS 0x98
> +#define USB3_V5_5NM_UNI_PCS_PCIE_LOCAL_LF 0x9c
> +#define USB3_V5_5NM_UNI_PCS_PCIE_LOCAL_FS_RS 0xa0
> +#define USB3_V5_5NM_UNI_PCS_PCIE_EQ_CONFIG1 0xa4
> +#define USB3_V5_5NM_UNI_PCS_PCIE_EQ_CONFIG2 0xa8
> +#define USB3_V5_5NM_UNI_PCS_PCIE_PRESET_P0_P1_PRE 0xac
> +#define USB3_V5_5NM_UNI_PCS_PCIE_PRESET_P2_P3_PRE 0xb0
> +#define USB3_V5_5NM_UNI_PCS_PCIE_PRESET_P4_P5_PRE 0xb4
> +#define USB3_V5_5NM_UNI_PCS_PCIE_PRESET_P6_P7_PRE 0xb8
> +#define USB3_V5_5NM_UNI_PCS_PCIE_PRESET_P8_P9_PRE 0xbc
> +#define USB3_V5_5NM_UNI_PCS_PCIE_PRESET_P10_PRE 0xc0
> +#define USB3_V5_5NM_UNI_PCS_PCIE_PRESET_P1_P3_PRE_RS 0xc4
> +#define USB3_V5_5NM_UNI_PCS_PCIE_PRESET_P4_P5_PRE_RS 0xc8
> +#define USB3_V5_5NM_UNI_PCS_PCIE_PRESET_P6_P9_PRE_RS 0xcc
> +#define USB3_V5_5NM_UNI_PCS_PCIE_PRESET_P0_P1_POST 0xd0
> +#define USB3_V5_5NM_UNI_PCS_PCIE_PRESET_P2_P3_POST 0xd4
> +#define USB3_V5_5NM_UNI_PCS_PCIE_PRESET_P4_P5_POST 0xd8
> +#define USB3_V5_5NM_UNI_PCS_PCIE_PRESET_P6_P7_POST 0xdc
> +#define USB3_V5_5NM_UNI_PCS_PCIE_PRESET_P8_P9_POST 0xe0
> +#define USB3_V5_5NM_UNI_PCS_PCIE_PRESET_P10_POST 0xe4
> +#define USB3_V5_5NM_UNI_PCS_PCIE_PRESET_P1_P3_POST_RS 0xe8
> +#define USB3_V5_5NM_UNI_PCS_PCIE_PRESET_P4_P5_POST_RS 0xec
> +#define USB3_V5_5NM_UNI_PCS_PCIE_PRESET_P6_P9_POST_RS 0xf0
> +#define USB3_V5_5NM_UNI_PCS_PCIE_RXEQEVAL_TIME 0xf4
QPHY_V5_PCS_PCIE_
> +
> +/* Module: USB3_UNI_PHY_PCIE_PCS_DEBUG_INTGEN */
> +#define USB3_V5_5NM_UNI_PCS_INTGEN_INTGEN_STATUS1 0x00
> +#define USB3_V5_5NM_UNI_PCS_INTGEN_INTGEN_STATUS2 0x04
> +#define USB3_V5_5NM_UNI_PCS_INTGEN_CONFIG1 0x08
> +#define USB3_V5_5NM_UNI_PCS_INTGEN_SIGNALBLK1_CONFIG1 0x0c
> +#define USB3_V5_5NM_UNI_PCS_INTGEN_SIGNALBLK1_CONFIG2 0x10
> +#define USB3_V5_5NM_UNI_PCS_INTGEN_SIGNALBLK1_CONFIG3 0x14
> +#define USB3_V5_5NM_UNI_PCS_INTGEN_SIGNALBLK1_CONFIG4 0x18
> +#define USB3_V5_5NM_UNI_PCS_INTGEN_SIGNALBLK1_CONFIG5 0x1c
> +#define USB3_V5_5NM_UNI_PCS_INTGEN_SIGNALBLK2_CONFIG1 0x20
> +#define USB3_V5_5NM_UNI_PCS_INTGEN_SIGNALBLK2_CONFIG2 0x24
> +#define USB3_V5_5NM_UNI_PCS_INTGEN_SIGNALBLK2_CONFIG3 0x28
> +#define USB3_V5_5NM_UNI_PCS_INTGEN_SIGNALBLK2_CONFIG4 0x2c
> +#define USB3_V5_5NM_UNI_PCS_INTGEN_SIGNALBLK2_CONFIG5 0x30
> +#define USB3_V5_5NM_UNI_PCS_INTGEN_STRINGBLK1_CONFIG1 0x34
> +#define USB3_V5_5NM_UNI_PCS_INTGEN_STRINGBLK1_CONFIG2 0x38
> +#define USB3_V5_5NM_UNI_PCS_INTGEN_STRINGBLK1_CONFIG3 0x3c
> +#define USB3_V5_5NM_UNI_PCS_INTGEN_STRINGBLK1_CONFIG4 0x40
> +#define USB3_V5_5NM_UNI_PCS_INTGEN_STRINGBLK1_CONFIG5 0x44
> +#define USB3_V5_5NM_UNI_PCS_INTGEN_STRINGBLK2_CONFIG1 0x48
> +#define USB3_V5_5NM_UNI_PCS_INTGEN_STRINGBLK2_CONFIG2 0x4c
> +#define USB3_V5_5NM_UNI_PCS_INTGEN_STRINGBLK2_CONFIG3 0x50
> +#define USB3_V5_5NM_UNI_PCS_INTGEN_STRINGBLK2_CONFIG4 0x54
> +#define USB3_V5_5NM_UNI_PCS_INTGEN_STRINGBLK2_CONFIG5 0x58
> +
> +
> +/* Module: USB3_UNI_PCS_USB3_PCIE_USB3_UNI_PCS_USB3 */
> +#define USB3_V5_5NM_UNI_PCS_USB3_POWER_STATE_CONFIG1 0x00
> +#define USB3_V5_5NM_UNI_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x04
> +#define USB3_V5_5NM_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x08
> +#define USB3_V5_5NM_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x0c
> +#define USB3_V5_5NM_UNI_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x10
> +#define USB3_V5_5NM_UNI_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x14
> +#define USB3_V5_5NM_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x18
> +#define USB3_V5_5NM_UNI_PCS_USB3_LFPS_TX_ECSTART 0x1c
> +#define USB3_V5_5NM_UNI_PCS_USB3_LFPS_PER_TIMER_VAL 0x20
> +#define USB3_V5_5NM_UNI_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x24
> +#define USB3_V5_5NM_UNI_PCS_USB3_LFPS_CONFIG1 0x28
> +#define USB3_V5_5NM_UNI_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x2c
> +#define USB3_V5_5NM_UNI_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x30
> +#define USB3_V5_5NM_UNI_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x34
> +#define USB3_V5_5NM_UNI_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x38
> +#define USB3_V5_5NM_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x3c
> +#define USB3_V5_5NM_UNI_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x40
> +#define USB3_V5_5NM_UNI_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x44
> +#define USB3_V5_5NM_UNI_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x48
> +#define USB3_V5_5NM_UNI_PCS_USB3_ARCVR_DTCT_CM_DLY 0x4c
> +#define USB3_V5_5NM_UNI_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x50
> +#define USB3_V5_5NM_UNI_PCS_USB3_ALFPS_DEGLITCH_VAL 0x54
> +#define USB3_V5_5NM_UNI_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x58
> +#define USB3_V5_5NM_UNI_PCS_USB3_TEST_CONTROL 0x5c
> +#define USB3_V5_5NM_UNI_PCS_USB3_RXTERMINATION_DLY_SEL 0x60
These look like QPHY_V5_PCS_USB3, but without additional 0x300 offset.
I'd suggest modifying qcom-qmp-phy-usb.c to allocate another register
space for pcs_usb and updating QPHY_V4_PCS_USB3_foo /
QPHY_V5_PCS_USB3_foo defines to remove this offset.
Afterwards most if not all constants from this header can be merged into
phy-qcom-qmp.h I do not think that it makes sense to split this header
at this moment. The QSERDES_COM/_TX/_RX/_PCS defines are common to all
PHY types.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 2/5] phy: qcom-qmp: Add USB3 5NM QMP UNI registers
2022-06-07 21:58 ` Dmitry Baryshkov
@ 2022-06-07 22:45 ` Bjorn Andersson
2022-06-07 23:17 ` Dmitry Baryshkov
0 siblings, 1 reply; 16+ messages in thread
From: Bjorn Andersson @ 2022-06-07 22:45 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Kishon Vijay Abraham I, Vinod Koul, Manu Gautam, Rob Herring,
Krzysztof Kozlowski, linux-arm-msm, linux-phy, devicetree,
linux-kernel
On Tue 07 Jun 14:58 PDT 2022, Dmitry Baryshkov wrote:
> On 08/06/2022 00:35, Bjorn Andersson wrote:
[..]
> > +#define USB3_V5_5NM_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0
> > +#define USB3_V5_5NM_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4
> > +#define USB3_V5_5NM_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8
> > +#define USB3_V5_5NM_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc
> > +#define USB3_V5_5NM_UNI_QSERDES_COM_RESERVED_1 0x1c0
> > +#define USB3_V5_5NM_UNI_QSERDES_COM_MODE_OPERATION_STATUS 0x1c4
>
> These defines look completely compatible with the existing ones in the
> QSERDES_V5_COM_ namespace. Please use them instead.
>
Can you please confirm that all these constants are exactly the same as
the existing V5 entries?
[..]
> > +/* Module: USB3_UNI_PCS_USB3_PCIE_USB3_UNI_PCS_USB3 */
> > +#define USB3_V5_5NM_UNI_PCS_USB3_POWER_STATE_CONFIG1 0x00
> > +#define USB3_V5_5NM_UNI_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x04
> > +#define USB3_V5_5NM_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x08
> > +#define USB3_V5_5NM_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x0c
> > +#define USB3_V5_5NM_UNI_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x10
> > +#define USB3_V5_5NM_UNI_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x14
> > +#define USB3_V5_5NM_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x18
> > +#define USB3_V5_5NM_UNI_PCS_USB3_LFPS_TX_ECSTART 0x1c
> > +#define USB3_V5_5NM_UNI_PCS_USB3_LFPS_PER_TIMER_VAL 0x20
> > +#define USB3_V5_5NM_UNI_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x24
> > +#define USB3_V5_5NM_UNI_PCS_USB3_LFPS_CONFIG1 0x28
> > +#define USB3_V5_5NM_UNI_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x2c
> > +#define USB3_V5_5NM_UNI_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x30
> > +#define USB3_V5_5NM_UNI_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x34
> > +#define USB3_V5_5NM_UNI_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x38
> > +#define USB3_V5_5NM_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x3c
> > +#define USB3_V5_5NM_UNI_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x40
> > +#define USB3_V5_5NM_UNI_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x44
> > +#define USB3_V5_5NM_UNI_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x48
> > +#define USB3_V5_5NM_UNI_PCS_USB3_ARCVR_DTCT_CM_DLY 0x4c
> > +#define USB3_V5_5NM_UNI_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x50
> > +#define USB3_V5_5NM_UNI_PCS_USB3_ALFPS_DEGLITCH_VAL 0x54
> > +#define USB3_V5_5NM_UNI_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x58
> > +#define USB3_V5_5NM_UNI_PCS_USB3_TEST_CONTROL 0x5c
> > +#define USB3_V5_5NM_UNI_PCS_USB3_RXTERMINATION_DLY_SEL 0x60
>
> These look like QPHY_V5_PCS_USB3, but without additional 0x300 offset. I'd
> suggest modifying qcom-qmp-phy-usb.c to allocate another register space for
> pcs_usb and updating QPHY_V4_PCS_USB3_foo / QPHY_V5_PCS_USB3_foo defines to
> remove this offset.
>
> Afterwards most if not all constants from this header can be merged into
> phy-qcom-qmp.h I do not think that it makes sense to split this header at
> this moment. The QSERDES_COM/_TX/_RX/_PCS defines are common to all PHY
> types.
>
You might be right, but I spent considerable time debugging the combo
phy (which is version 5.0.0) and in the end it turned out that it's not
the same offsets.
I really would prefer that we stop haphazardly try to fit things into
the phy-qcom-qmp.h with version numbers that we essentially make up
base, when Qualcomm dumps the register layout for each generation in
their downstream kernel.
Regards,
Bjorn
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 2/5] phy: qcom-qmp: Add USB3 5NM QMP UNI registers
2022-06-07 22:45 ` Bjorn Andersson
@ 2022-06-07 23:17 ` Dmitry Baryshkov
0 siblings, 0 replies; 16+ messages in thread
From: Dmitry Baryshkov @ 2022-06-07 23:17 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Kishon Vijay Abraham I, Vinod Koul, Manu Gautam, Rob Herring,
Krzysztof Kozlowski, linux-arm-msm, linux-phy, devicetree,
linux-kernel
On Wed, 8 Jun 2022 at 01:43, Bjorn Andersson <bjorn.andersson@linaro.org> wrote:
>
> On Tue 07 Jun 14:58 PDT 2022, Dmitry Baryshkov wrote:
> > On 08/06/2022 00:35, Bjorn Andersson wrote:
> [..]
> > > +#define USB3_V5_5NM_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0
> > > +#define USB3_V5_5NM_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4
> > > +#define USB3_V5_5NM_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8
> > > +#define USB3_V5_5NM_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc
> > > +#define USB3_V5_5NM_UNI_QSERDES_COM_RESERVED_1 0x1c0
> > > +#define USB3_V5_5NM_UNI_QSERDES_COM_MODE_OPERATION_STATUS 0x1c4
> >
> > These defines look completely compatible with the existing ones in the
> > QSERDES_V5_COM_ namespace. Please use them instead.
> >
>
> Can you please confirm that all these constants are exactly the same as
> the existing V5 entries?
The only difference that I see is the phy-qcom-qmp.h defining
QSERDES_V5_COM_CMN_MODE to 0x1a4, which should be 0x1a0. This is
clearly a mistake on the upstream side (confirmed by the msm-5.10).
Could you please send a patch for it?
>
> [..]
> > > +/* Module: USB3_UNI_PCS_USB3_PCIE_USB3_UNI_PCS_USB3 */
> > > +#define USB3_V5_5NM_UNI_PCS_USB3_POWER_STATE_CONFIG1 0x00
> > > +#define USB3_V5_5NM_UNI_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x04
> > > +#define USB3_V5_5NM_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x08
> > > +#define USB3_V5_5NM_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x0c
> > > +#define USB3_V5_5NM_UNI_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x10
> > > +#define USB3_V5_5NM_UNI_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x14
> > > +#define USB3_V5_5NM_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x18
> > > +#define USB3_V5_5NM_UNI_PCS_USB3_LFPS_TX_ECSTART 0x1c
> > > +#define USB3_V5_5NM_UNI_PCS_USB3_LFPS_PER_TIMER_VAL 0x20
> > > +#define USB3_V5_5NM_UNI_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x24
> > > +#define USB3_V5_5NM_UNI_PCS_USB3_LFPS_CONFIG1 0x28
> > > +#define USB3_V5_5NM_UNI_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x2c
> > > +#define USB3_V5_5NM_UNI_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x30
> > > +#define USB3_V5_5NM_UNI_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x34
> > > +#define USB3_V5_5NM_UNI_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x38
> > > +#define USB3_V5_5NM_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x3c
> > > +#define USB3_V5_5NM_UNI_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x40
> > > +#define USB3_V5_5NM_UNI_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x44
> > > +#define USB3_V5_5NM_UNI_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x48
> > > +#define USB3_V5_5NM_UNI_PCS_USB3_ARCVR_DTCT_CM_DLY 0x4c
> > > +#define USB3_V5_5NM_UNI_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x50
> > > +#define USB3_V5_5NM_UNI_PCS_USB3_ALFPS_DEGLITCH_VAL 0x54
> > > +#define USB3_V5_5NM_UNI_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x58
> > > +#define USB3_V5_5NM_UNI_PCS_USB3_TEST_CONTROL 0x5c
> > > +#define USB3_V5_5NM_UNI_PCS_USB3_RXTERMINATION_DLY_SEL 0x60
> >
> > These look like QPHY_V5_PCS_USB3, but without additional 0x300 offset. I'd
> > suggest modifying qcom-qmp-phy-usb.c to allocate another register space for
> > pcs_usb and updating QPHY_V4_PCS_USB3_foo / QPHY_V5_PCS_USB3_foo defines to
> > remove this offset.
> >
> > Afterwards most if not all constants from this header can be merged into
> > phy-qcom-qmp.h I do not think that it makes sense to split this header at
> > this moment. The QSERDES_COM/_TX/_RX/_PCS defines are common to all PHY
> > types.
> >
>
> You might be right, but I spent considerable time debugging the combo
> phy (which is version 5.0.0) and in the end it turned out that it's not
> the same offsets.
>
> I really would prefer that we stop haphazardly try to fit things into
> the phy-qcom-qmp.h with version numbers that we essentially make up
> base, when Qualcomm dumps the register layout for each generation in
> their downstream kernel.
Well... Let's come up with a better versioning/naming scheme. But I
don't think we should dump repeatable symbol headers, which are in
reality common between different PHYs. This would make things harder
to understand and harder to maintain.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v2 3/5] phy: qcom-qmp: Add USB4 5NM QMP combo PHY registers
2022-06-07 21:35 [PATCH v2 0/5] phy: qcom: Add SC8280XP UNI and COMBO USB phys Bjorn Andersson
2022-06-07 21:35 ` [PATCH v2 1/5] dt-bindings: phy: qcom,qmp: Add compatible for SC8280XP " Bjorn Andersson
2022-06-07 21:35 ` [PATCH v2 2/5] phy: qcom-qmp: Add USB3 5NM QMP UNI registers Bjorn Andersson
@ 2022-06-07 21:35 ` Bjorn Andersson
2022-06-07 22:24 ` Dmitry Baryshkov
2022-06-07 21:35 ` [PATCH v2 4/5] phy: qcom-qmp: Add SC8280XP USB3 UNI phy Bjorn Andersson
` (2 subsequent siblings)
5 siblings, 1 reply; 16+ messages in thread
From: Bjorn Andersson @ 2022-06-07 21:35 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Manu Gautam
Cc: Rob Herring, Krzysztof Kozlowski, linux-arm-msm, linux-phy,
devicetree, linux-kernel
Add all registers defines from qcom,usb4-5nm-qmp-combo.h of the msm-5.4
kernel. Offsets are adjusted to be relative to each sub-block, as we
describe the individual pieces in the upstream kernel and "v5_5NM" are
injected in the defines to not collide with existing constants.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
Changes since v1:
- New patch
.../qualcomm/phy-qcom-usb4-5nm-qmp-combo.h | 1547 +++++++++++++++++
1 file changed, 1547 insertions(+)
create mode 100644 drivers/phy/qualcomm/phy-qcom-usb4-5nm-qmp-combo.h
diff --git a/drivers/phy/qualcomm/phy-qcom-usb4-5nm-qmp-combo.h b/drivers/phy/qualcomm/phy-qcom-usb4-5nm-qmp-combo.h
new file mode 100644
index 000000000000..7be8a50269ec
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-usb4-5nm-qmp-combo.h
@@ -0,0 +1,1547 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef PHY_QCOM_V5_5NM_QMP_COMBO_USB4_H
+#define PHY_QCOM_V5_5NM_QMP_COMBO_USB4_H
+
+/* USB4-USB3-DP Combo PHY register offsets */
+/* Module: USB43DP_COM_USB43DP_COM_USB4_USB3_DP_COM */
+#define USB43DP_V5_5NM_COM_PHY_MODE_CTRL 0x00
+#define USB43DP_V5_5NM_COM_SW_RESET 0x04
+#define USB43DP_V5_5NM_COM_POWER_DOWN_CTRL 0x08
+#define USB43DP_V5_5NM_COM_SWI_CTRL 0x0c
+#define USB43DP_V5_5NM_COM_TYPEC_CTRL 0x10
+#define USB43DP_V5_5NM_COM_TYPEC_PWRDN_CTRL 0x14
+#define USB43DP_V5_5NM_COM_DP_BIST_CFG_0 0x18
+#define USB43DP_V5_5NM_COM_RESET_OVRD_CTRL1 0x1c
+#define USB43DP_V5_5NM_COM_RESET_OVRD_CTRL2 0x20
+#define USB43DP_V5_5NM_COM_DBG_CLK_MUX_CTRL 0x24
+#define USB43DP_V5_5NM_COM_TYPEC_STATUS 0x28
+#define USB43DP_V5_5NM_COM_PLACEHOLDER_STATUS 0x2c
+#define USB43DP_V5_5NM_COM_REVISION_ID0 0x30
+#define USB43DP_V5_5NM_COM_REVISION_ID1 0x34
+#define USB43DP_V5_5NM_COM_REVISION_ID2 0x38
+#define USB43DP_V5_5NM_COM_REVISION_ID3 0x3c
+
+/* Module: USB43DP_DBGINT_USB43DP_DBGINT_USB3_PCS_DEBUG_INT */
+#define USB43DP_V5_5NM_DBGINT_INTGEN_STATUS1 0x00
+#define USB43DP_V5_5NM_DBGINT_INTGEN_STATUS2 0x04
+#define USB43DP_V5_5NM_DBGINT_CONFIG1 0x08
+#define USB43DP_V5_5NM_DBGINT_SIGNALBLK1_CONFIG1 0x0c
+#define USB43DP_V5_5NM_DBGINT_SIGNALBLK1_CONFIG2 0x10
+#define USB43DP_V5_5NM_DBGINT_SIGNALBLK1_CONFIG3 0x14
+#define USB43DP_V5_5NM_DBGINT_SIGNALBLK1_CONFIG4 0x18
+#define USB43DP_V5_5NM_DBGINT_SIGNALBLK1_CONFIG5 0x1c
+#define USB43DP_V5_5NM_DBGINT_SIGNALBLK2_CONFIG1 0x20
+#define USB43DP_V5_5NM_DBGINT_SIGNALBLK2_CONFIG2 0x24
+#define USB43DP_V5_5NM_DBGINT_SIGNALBLK2_CONFIG3 0x28
+#define USB43DP_V5_5NM_DBGINT_SIGNALBLK2_CONFIG4 0x2c
+#define USB43DP_V5_5NM_DBGINT_SIGNALBLK2_CONFIG5 0x30
+#define USB43DP_V5_5NM_DBGINT_STRINGBLK1_CONFIG1 0x34
+#define USB43DP_V5_5NM_DBGINT_STRINGBLK1_CONFIG2 0x38
+#define USB43DP_V5_5NM_DBGINT_STRINGBLK1_CONFIG3 0x3c
+#define USB43DP_V5_5NM_DBGINT_STRINGBLK1_CONFIG4 0x40
+#define USB43DP_V5_5NM_DBGINT_STRINGBLK1_CONFIG5 0x44
+#define USB43DP_V5_5NM_DBGINT_STRINGBLK2_CONFIG1 0x48
+#define USB43DP_V5_5NM_DBGINT_STRINGBLK2_CONFIG2 0x4c
+#define USB43DP_V5_5NM_DBGINT_STRINGBLK2_CONFIG3 0x50
+#define USB43DP_V5_5NM_DBGINT_STRINGBLK2_CONFIG4 0x54
+#define USB43DP_V5_5NM_DBGINT_STRINGBLK2_CONFIG5 0x58
+
+/* Module: USB43DP_QSERDES_TXA_USB43DP_QSERDES_TXA_USB4_USB3_DP_QMP_TX */
+#define USB43DP_V5_5NM_QSERDES_TXA_BIST_MODE_LANENO 0x00
+#define USB43DP_V5_5NM_QSERDES_TXA_BIST_INVERT 0x04
+#define USB43DP_V5_5NM_QSERDES_TXA_CLKBUF_ENABLE 0x08
+#define USB43DP_V5_5NM_QSERDES_TXA_TX_EMP_POST1_LVL 0x0c
+#define USB43DP_V5_5NM_QSERDES_TXA_TX_IDLE_LVL_LARGE_AMP 0x10
+#define USB43DP_V5_5NM_QSERDES_TXA_TX_DRV_LVL 0x14
+#define USB43DP_V5_5NM_QSERDES_TXA_TX_DRV_LVL_OFFSET 0x18
+#define USB43DP_V5_5NM_QSERDES_TXA_RESET_TSYNC_EN 0x1c
+#define USB43DP_V5_5NM_QSERDES_TXA_PRE_STALL_LDO_BOOST_EN 0x20
+#define USB43DP_V5_5NM_QSERDES_TXA_LPB_EN 0x24
+#define USB43DP_V5_5NM_QSERDES_TXA_RES_CODE_LANE_TX 0x28
+#define USB43DP_V5_5NM_QSERDES_TXA_RES_CODE_LANE_RX 0x2c
+#define USB43DP_V5_5NM_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x30
+#define USB43DP_V5_5NM_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x34
+#define USB43DP_V5_5NM_QSERDES_TXA_PERL_LENGTH1 0x38
+#define USB43DP_V5_5NM_QSERDES_TXA_PERL_LENGTH2 0x3c
+#define USB43DP_V5_5NM_QSERDES_TXA_SERDES_BYP_EN_OUT 0x40
+#define USB43DP_V5_5NM_QSERDES_TXA_DEBUG_BUS_SEL 0x44
+#define USB43DP_V5_5NM_QSERDES_TXA_TRANSCEIVER_BIAS_EN 0x48
+#define USB43DP_V5_5NM_QSERDES_TXA_HIGHZ_DRVR_EN 0x4c
+#define USB43DP_V5_5NM_QSERDES_TXA_TX_POL_INV 0x50
+#define USB43DP_V5_5NM_QSERDES_TXA_PARRATE_REC_DETECT_IDLE_EN 0x54
+#define USB43DP_V5_5NM_QSERDES_TXA_BIST_PATTERN1 0x58
+#define USB43DP_V5_5NM_QSERDES_TXA_BIST_PATTERN2 0x5c
+#define USB43DP_V5_5NM_QSERDES_TXA_BIST_PATTERN3 0x60
+#define USB43DP_V5_5NM_QSERDES_TXA_BIST_PATTERN4 0x64
+#define USB43DP_V5_5NM_QSERDES_TXA_BIST_PATTERN5 0x68
+#define USB43DP_V5_5NM_QSERDES_TXA_BIST_PATTERN6 0x6c
+#define USB43DP_V5_5NM_QSERDES_TXA_BIST_PATTERN7 0x70
+#define USB43DP_V5_5NM_QSERDES_TXA_BIST_PATTERN8 0x74
+#define USB43DP_V5_5NM_QSERDES_TXA_LANE_MODE_1 0x78
+#define USB43DP_V5_5NM_QSERDES_TXA_LANE_MODE_2 0x7c
+#define USB43DP_V5_5NM_QSERDES_TXA_LANE_MODE_3 0x80
+#define USB43DP_V5_5NM_QSERDES_TXA_ATB_SEL1 0x84
+#define USB43DP_V5_5NM_QSERDES_TXA_ATB_SEL2 0x88
+#define USB43DP_V5_5NM_QSERDES_TXA_RCV_DETECT_LVL 0x8c
+#define USB43DP_V5_5NM_QSERDES_TXA_RCV_DETECT_LVL_2 0x90
+#define USB43DP_V5_5NM_QSERDES_TXA_PRBS_SEED1 0x94
+#define USB43DP_V5_5NM_QSERDES_TXA_PRBS_SEED2 0x98
+#define USB43DP_V5_5NM_QSERDES_TXA_PRBS_SEED3 0x9c
+#define USB43DP_V5_5NM_QSERDES_TXA_PRBS_SEED4 0xa0
+#define USB43DP_V5_5NM_QSERDES_TXA_RESET_GEN 0xa4
+#define USB43DP_V5_5NM_QSERDES_TXA_RESET_GEN_MUXES 0xa8
+#define USB43DP_V5_5NM_QSERDES_TXA_TRAN_DRVR_EMP_EN 0xac
+#define USB43DP_V5_5NM_QSERDES_TXA_VMODE_CTRL1 0xb0
+#define USB43DP_V5_5NM_QSERDES_TXA_ALOG_OBSV_BUS_CTRL_1 0xb4
+#define USB43DP_V5_5NM_QSERDES_TXA_BIST_STATUS 0xb8
+#define USB43DP_V5_5NM_QSERDES_TXA_BIST_ERROR_COUNT1 0xbc
+#define USB43DP_V5_5NM_QSERDES_TXA_BIST_ERROR_COUNT2 0xc0
+#define USB43DP_V5_5NM_QSERDES_TXA_ALOG_OBSV_BUS_STATUS_1 0xc4
+#define USB43DP_V5_5NM_QSERDES_TXA_LANE_DIG_CONFIG 0xc8
+#define USB43DP_V5_5NM_QSERDES_TXA_PI_QEC_CTRL 0xcc
+#define USB43DP_V5_5NM_QSERDES_TXA_PRE_EMPH 0xd0
+#define USB43DP_V5_5NM_QSERDES_TXA_SW_RESET 0xd4
+#define USB43DP_V5_5NM_QSERDES_TXA_TX_BAND 0xd8
+#define USB43DP_V5_5NM_QSERDES_TXA_SLEW_CNTL0 0xdc
+#define USB43DP_V5_5NM_QSERDES_TXA_SLEW_CNTL1 0xe0
+#define USB43DP_V5_5NM_QSERDES_TXA_INTERFACE_SELECT 0xe4
+#define USB43DP_V5_5NM_QSERDES_TXA_DIG_BKUP_CTRL 0xe8
+#define USB43DP_V5_5NM_QSERDES_TXA_DEBUG_BUS0 0xec
+#define USB43DP_V5_5NM_QSERDES_TXA_DEBUG_BUS1 0xf0
+#define USB43DP_V5_5NM_QSERDES_TXA_DEBUG_BUS2 0xf4
+#define USB43DP_V5_5NM_QSERDES_TXA_DEBUG_BUS3 0xf8
+#define USB43DP_V5_5NM_QSERDES_TXA_TX_BKUP_RO_BUS 0xfc
+
+/* Module: USB43DP_QSERDES_RXA_USB43DP_QSERDES_RXA_USB4_USB3_DP_QMP_RX */
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN_RATE0 0x000
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN_RATE1 0x004
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN_RATE2 0x008
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN_RATE3 0x00c
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FASTLOCK_SO_GAIN_RATE0 0x010
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FASTLOCK_SO_GAIN_RATE1 0x014
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FASTLOCK_SO_GAIN_RATE2 0x018
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FASTLOCK_SO_GAIN_RATE3 0x01c
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SO_SATURATION 0x020
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FO_TO_SO_DELAY 0x024
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW_RATE0 0x028
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH_RATE0 0x02c
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW_RATE1 0x030
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH_RATE1 0x034
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW_RATE2 0x038
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH_RATE2 0x03c
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW_RATE3 0x040
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH_RATE3 0x044
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_PI_CTRL1 0x048
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_PI_CTRL2 0x04c
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SB2_THRESH1_RATE0 0x050
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SB2_THRESH1_RATE1 0x054
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SB2_THRESH1_RATE2 0x058
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SB2_THRESH1_RATE3 0x05c
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SB2_THRESH2_RATE0 0x060
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SB2_THRESH2_RATE1 0x064
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SB2_THRESH2_RATE2 0x068
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SB2_THRESH2_RATE3 0x06c
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SB2_GAIN1_RATE0 0x070
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SB2_GAIN1_RATE1 0x074
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SB2_GAIN1_RATE2 0x078
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SB2_GAIN1_RATE3 0x07c
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SB2_GAIN2_RATE0 0x080
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SB2_GAIN2_RATE1 0x084
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SB2_GAIN2_RATE2 0x088
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SB2_GAIN2_RATE3 0x08c
+#define USB43DP_V5_5NM_QSERDES_RXA_RXCLK_DIV2_CTRL 0x090
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_BAND 0x094
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_TERM_BW 0x098
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FO_GAIN_RATE0 0x09c
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FO_GAIN_RATE1 0x0a0
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FO_GAIN_RATE2 0x0a4
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FO_GAIN_RATE3 0x0a8
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SO_GAIN_RATE0 0x0ac
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SO_GAIN_RATE1 0x0b0
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SO_GAIN_RATE2 0x0b4
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SO_GAIN_RATE3 0x0b8
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_PI_CONTROLS 0x0bc
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_PD_DATA_FILTER_ENABLES 0x0c0
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SO_ACC_DEFAULT_VAL_RATE0 0x0c4
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SO_ACC_DEFAULT_VAL_RATE1 0x0c8
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SO_ACC_DEFAULT_VAL_RATE2 0x0cc
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SO_ACC_DEFAULT_VAL_RATE3 0x0d0
+#define USB43DP_V5_5NM_QSERDES_RXA_AUX_CONTROL 0x0d4
+#define USB43DP_V5_5NM_QSERDES_RXA_AUXDATA_TB 0x0d8
+#define USB43DP_V5_5NM_QSERDES_RXA_RCLK_AUXDATA_SEL 0x0dc
+#define USB43DP_V5_5NM_QSERDES_RXA_EOM_CTRL 0x0e0
+#define USB43DP_V5_5NM_QSERDES_RXA_AC_JTAG_ENABLE 0x0e4
+#define USB43DP_V5_5NM_QSERDES_RXA_AC_JTAG_INITP 0x0e8
+#define USB43DP_V5_5NM_QSERDES_RXA_AC_JTAG_INITN 0x0ec
+#define USB43DP_V5_5NM_QSERDES_RXA_AC_JTAG_LVL 0x0f0
+#define USB43DP_V5_5NM_QSERDES_RXA_AC_JTAG_MODE 0x0f4
+#define USB43DP_V5_5NM_QSERDES_RXA_AC_JTAG_RESET 0x0f8
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_RCVR_IQ_EN 0x0fc
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_Q_EN_RATES 0x100
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_IDAC_I0_DC_OFFSETS 0x104
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_IDAC_I0BAR_DC_OFFSETS 0x108
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_IDAC_I1_DC_OFFSETS 0x10c
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_IDAC_I1BAR_DC_OFFSETS 0x110
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_IDAC_Q_DC_OFFSETS 0x114
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_IDAC_QBAR_DC_OFFSETS 0x118
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_IDAC_A_DC_OFFSETS 0x11c
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_IDAC_ABAR_DC_OFFSETS 0x120
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_IDAC_EN 0x124
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_IDAC_ENABLES 0x128
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_IDAC_SIGN 0x12c
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_IVCM_CAL_CODE_OVERRIDE 0x130
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_IVCM_CAL_CTRL1 0x134
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_IVCM_CAL_CTRL2 0x138
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_IVCM_POSTCAL_OFFSET 0x13c
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_SUMMER_CAL_SPD_MODE 0x140
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_HIGHZ_PARRATE 0x144
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x148
+#define USB43DP_V5_5NM_QSERDES_RXA_DFE_1 0x14c
+#define USB43DP_V5_5NM_QSERDES_RXA_DFE_2 0x150
+#define USB43DP_V5_5NM_QSERDES_RXA_DFE_3 0x154
+#define USB43DP_V5_5NM_QSERDES_RXA_DFE_4 0x158
+#define USB43DP_V5_5NM_QSERDES_RXA_DFE_TAP3_CTRL 0x15c
+#define USB43DP_V5_5NM_QSERDES_RXA_DFE_TAP3_MANVAL_KTAP 0x160
+#define USB43DP_V5_5NM_QSERDES_RXA_DFE_TAP4_CTRL 0x164
+#define USB43DP_V5_5NM_QSERDES_RXA_DFE_TAP4_MANVAL_KTAP 0x168
+#define USB43DP_V5_5NM_QSERDES_RXA_DFE_TAP5_CTRL 0x16c
+#define USB43DP_V5_5NM_QSERDES_RXA_DFE_TAP5_MANVAL_KTAP 0x170
+#define USB43DP_V5_5NM_QSERDES_RXA_TX_ADPT_CTRL 0x174
+#define USB43DP_V5_5NM_QSERDES_RXA_DFE_DAC_ENABLE1 0x178
+#define USB43DP_V5_5NM_QSERDES_RXA_DFE_DAC_ENABLE2 0x17c
+#define USB43DP_V5_5NM_QSERDES_RXA_TX_ADAPT_PRE_THRESH1 0x180
+#define USB43DP_V5_5NM_QSERDES_RXA_TX_ADAPT_PRE_THRESH2 0x184
+#define USB43DP_V5_5NM_QSERDES_RXA_TX_ADAPT_POST_THRESH1 0x188
+#define USB43DP_V5_5NM_QSERDES_RXA_TX_ADAPT_POST_THRESH2 0x18c
+#define USB43DP_V5_5NM_QSERDES_RXA_TX_ADAPT_MAIN_THRESH1 0x190
+#define USB43DP_V5_5NM_QSERDES_RXA_TX_ADAPT_MAIN_THRESH2 0x194
+#define USB43DP_V5_5NM_QSERDES_RXA_VGA_CAL_CNTRL1 0x198
+#define USB43DP_V5_5NM_QSERDES_RXA_VGA_CAL_CNTRL2 0x19c
+#define USB43DP_V5_5NM_QSERDES_RXA_VGA_CAL_MAN_VAL 0x1a0
+#define USB43DP_V5_5NM_QSERDES_RXA_VTHRESH_CAL_CNTRL1 0x1a4
+#define USB43DP_V5_5NM_QSERDES_RXA_VTHRESH_CAL_CNTRL2 0x1a8
+#define USB43DP_V5_5NM_QSERDES_RXA_VTHRESH_CAL_MAN_VAL_RATE0 0x1ac
+#define USB43DP_V5_5NM_QSERDES_RXA_VTHRESH_CAL_MAN_VAL_RATE1 0x1b0
+#define USB43DP_V5_5NM_QSERDES_RXA_VTHRESH_CAL_MAN_VAL_RATE2 0x1b4
+#define USB43DP_V5_5NM_QSERDES_RXA_VTHRESH_CAL_MAN_VAL_RATE3 0x1b8
+#define USB43DP_V5_5NM_QSERDES_RXA_GM_CAL 0x1bc
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_VGA_GAIN2_BLK1 0x1c0
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_VGA_GAIN2_BLK2 0x1c4
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x1c8
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x1cc
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x1d0
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0x1d4
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_EQ_OFFSET_LSB 0x1d8
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_EQ_OFFSET_MSB 0x1dc
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1e0
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_OFFSET_ADAPTOR_CNTRL2 0x1e4
+#define USB43DP_V5_5NM_QSERDES_RXA_SIGDET_ENABLES 0x1e8
+#define USB43DP_V5_5NM_QSERDES_RXA_SIGDET_CNTRL 0x1ec
+#define USB43DP_V5_5NM_QSERDES_RXA_SIGDET_LVL 0x1f0
+#define USB43DP_V5_5NM_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x1f4
+#define USB43DP_V5_5NM_QSERDES_RXA_CDR_FREEZE_UP_DN 0x1f8
+#define USB43DP_V5_5NM_QSERDES_RXA_CDR_RESET_OVERRIDE 0x1fc
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_INTERFACE_MODE 0x200
+#define USB43DP_V5_5NM_QSERDES_RXA_JITTER_GEN_MODE 0x204
+#define USB43DP_V5_5NM_QSERDES_RXA_SJ_AMP1 0x208
+#define USB43DP_V5_5NM_QSERDES_RXA_SJ_AMP2 0x20c
+#define USB43DP_V5_5NM_QSERDES_RXA_SJ_PER1 0x210
+#define USB43DP_V5_5NM_QSERDES_RXA_SJ_PER2 0x214
+#define USB43DP_V5_5NM_QSERDES_RXA_PPM_OFFSET1 0x218
+#define USB43DP_V5_5NM_QSERDES_RXA_PPM_OFFSET2 0x21c
+#define USB43DP_V5_5NM_QSERDES_RXA_SIGN_PPM_PERIOD1 0x220
+#define USB43DP_V5_5NM_QSERDES_RXA_SIGN_PPM_PERIOD2 0x224
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE_0_1_B0 0x228
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE_0_1_B1 0x22c
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE_0_1_B2 0x230
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE_0_1_B3 0x234
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE_0_1_B4 0x238
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE_0_1_B5 0x23c
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE_0_1_B6 0x240
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE_0_1_B7 0x244
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE2_B0 0x248
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE2_B1 0x24c
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE2_B2 0x250
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE2_B3 0x254
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE2_B4 0x258
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE2_B5 0x25c
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE2_B6 0x260
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE2_B7 0x264
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE3_B0 0x268
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE3_B1 0x26c
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE3_B2 0x270
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE3_B3 0x274
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE3_B4 0x278
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE3_B5 0x27c
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE3_B6 0x280
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE3_B7 0x284
+#define USB43DP_V5_5NM_QSERDES_RXA_PHPRE_CTRL 0x288
+#define USB43DP_V5_5NM_QSERDES_RXA_PHPRE_INITVAL 0x28c
+#define USB43DP_V5_5NM_QSERDES_RXA_DFE_EN_TIMER 0x290
+#define USB43DP_V5_5NM_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x294
+#define USB43DP_V5_5NM_QSERDES_RXA_DCC_CTRL1 0x298
+#define USB43DP_V5_5NM_QSERDES_RXA_DCC_CTRL2 0x29c
+#define USB43DP_V5_5NM_QSERDES_RXA_DCC_OFFSET 0x2a0
+#define USB43DP_V5_5NM_QSERDES_RXA_DCC_CMUX_POSTCAL_OFFSET 0x2a4
+#define USB43DP_V5_5NM_QSERDES_RXA_DCC_CMUX_CAL_CTRL1 0x2a8
+#define USB43DP_V5_5NM_QSERDES_RXA_DCC_CMUX_CAL_CTRL2 0x2ac
+#define USB43DP_V5_5NM_QSERDES_RXA_ALOG_OBSV_BUS_CTRL_1 0x2b0
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_CTRL1 0x2b4
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_CTRL2 0x2b8
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_CTRL3 0x2bc
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_CTRL_4 0x2c0
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_CFG_RATE_0_1 0x2c4
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_CFG_RATE_2_3 0x2c8
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_CTRL1 0x2cc
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_CTRL2 0x2d0
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_THRESH1_RATE210 0x2d4
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_THRESH1_RATE3 0x2d8
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_THRESH2_RATE210 0x2dc
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_THRESH2_RATE3 0x2e0
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_THRESH3_RATE210 0x2e4
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_THRESH3_RATE3 0x2e8
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_THRESH4_RATE210 0x2ec
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_THRESH4_RATE3 0x2f0
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_THRESH5_RATE210 0x2f4
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_THRESH5_RATE3 0x2f8
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_THRESH6_RATE210 0x2fc
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_THRESH6_RATE3 0x300
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_THRESH7_RATE210 0x304
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_THRESH7_RATE3 0x308
+#define USB43DP_V5_5NM_QSERDES_RXA_Q_PI_INTRINSIC_BIAS_RATE10 0x30c
+#define USB43DP_V5_5NM_QSERDES_RXA_Q_PI_INTRINSIC_BIAS_RATE32 0x310
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_VERTICAL_CTRL 0x314
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_VERTICAL_CODE 0x318
+#define USB43DP_V5_5NM_QSERDES_RXA_RES_CODE_THRESH_HIGH_AND_BYP 0x31c
+#define USB43DP_V5_5NM_QSERDES_RXA_RES_CODE_THRESH_LOW 0x320
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_BKUP_CTRL1 0x324
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_BKUP_CTRL2 0x328
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_BKUP_CTRL3 0x32c
+#define USB43DP_V5_5NM_QSERDES_RXA_PI_CTRL1 0x330
+#define USB43DP_V5_5NM_QSERDES_RXA_PI_CTRL2 0x334
+#define USB43DP_V5_5NM_QSERDES_RXA_PI_QUAD 0x338
+#define USB43DP_V5_5NM_QSERDES_RXA_QPI_CTRL1 0x33c
+#define USB43DP_V5_5NM_QSERDES_RXA_QPI_CTRL2 0x340
+#define USB43DP_V5_5NM_QSERDES_RXA_QPI_QUAD 0x344
+#define USB43DP_V5_5NM_QSERDES_RXA_IDATA1 0x348
+#define USB43DP_V5_5NM_QSERDES_RXA_IDATA2 0x34c
+#define USB43DP_V5_5NM_QSERDES_RXA_IDATA3 0x350
+#define USB43DP_V5_5NM_QSERDES_RXA_AC_JTAG_OUTP 0x354
+#define USB43DP_V5_5NM_QSERDES_RXA_AC_JTAG_OUTN 0x358
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_SIGDET 0x35c
+#define USB43DP_V5_5NM_QSERDES_RXA_ALOG_OBSV_BUS_STATUS_1 0x360
+#define USB43DP_V5_5NM_QSERDES_RXA_READ_EQCODE 0x364
+#define USB43DP_V5_5NM_QSERDES_RXA_READ_OFFSETCODE 0x368
+#define USB43DP_V5_5NM_QSERDES_RXA_IA_ERROR_COUNTER_LOW 0x36c
+#define USB43DP_V5_5NM_QSERDES_RXA_IA_ERROR_COUNTER_HIGH 0x370
+#define USB43DP_V5_5NM_QSERDES_RXA_VGA_READ_CODE 0x374
+#define USB43DP_V5_5NM_QSERDES_RXA_VTHRESH_READ_CODE 0x378
+#define USB43DP_V5_5NM_QSERDES_RXA_DFE_TAP1_READ_CODE 0x37c
+#define USB43DP_V5_5NM_QSERDES_RXA_DFE_TAP2_READ_CODE 0x380
+#define USB43DP_V5_5NM_QSERDES_RXA_DFE_TAP3_READ_CODE 0x384
+#define USB43DP_V5_5NM_QSERDES_RXA_DFE_TAP4_READ_CODE 0x388
+#define USB43DP_V5_5NM_QSERDES_RXA_DFE_TAP5_READ_CODE 0x38c
+#define USB43DP_V5_5NM_QSERDES_RXA_IDAC_STATUS_I0 0x390
+#define USB43DP_V5_5NM_QSERDES_RXA_IDAC_STATUS_I0BAR 0x394
+#define USB43DP_V5_5NM_QSERDES_RXA_IDAC_STATUS_I1 0x398
+#define USB43DP_V5_5NM_QSERDES_RXA_IDAC_STATUS_I1BAR 0x39c
+#define USB43DP_V5_5NM_QSERDES_RXA_IDAC_STATUS_Q 0x3a0
+#define USB43DP_V5_5NM_QSERDES_RXA_IDAC_STATUS_QBAR 0x3a4
+#define USB43DP_V5_5NM_QSERDES_RXA_IDAC_STATUS_A 0x3a8
+#define USB43DP_V5_5NM_QSERDES_RXA_IDAC_STATUS_ABAR 0x3ac
+#define USB43DP_V5_5NM_QSERDES_RXA_IDAC_STATUS_SM_ON 0x3b0
+#define USB43DP_V5_5NM_QSERDES_RXA_IDAC_STATUS_SIGNERROR 0x3b4
+#define USB43DP_V5_5NM_QSERDES_RXA_IVCM_CAL_STATUS 0x3b8
+#define USB43DP_V5_5NM_QSERDES_RXA_IVCM_CAL_DEBUG_STATUS 0x3bc
+#define USB43DP_V5_5NM_QSERDES_RXA_DCC_CAL_STATUS 0x3c0
+#define USB43DP_V5_5NM_QSERDES_RXA_DCC_READ_CODE_STATUS 0x3c4
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_DEBUG1_STATUS 0x3c8
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_DEBUG2_STATUS 0x3cc
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_READ_CODE_STATUS 0x3d0
+#define USB43DP_V5_5NM_QSERDES_RXA_EOM_ERR_CNT_LSB_STATUS 0x3d4
+#define USB43DP_V5_5NM_QSERDES_RXA_EOM_ERR_CNT_MSB_STATUS 0x3d8
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_TUNE_STATUS 0x3dc
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_BKUP_READ_BUS1_STATUS 0x3e0
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_BKUP_READ_BUS2_STATUS 0x3e4
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_BKUP_READ_BUS3_STATUS 0x3e8
+
+/* Module: USB43DP_QSERDES_TXB_USB43DP_QSERDES_TXB_USB4_USB3_DP_QMP_TX */
+#define USB43DP_V5_5NM_QSERDES_TXB_BIST_MODE_LANENO 0x00
+#define USB43DP_V5_5NM_QSERDES_TXB_BIST_INVERT 0x04
+#define USB43DP_V5_5NM_QSERDES_TXB_CLKBUF_ENABLE 0x08
+#define USB43DP_V5_5NM_QSERDES_TXB_TX_EMP_POST1_LVL 0x0c
+#define USB43DP_V5_5NM_QSERDES_TXB_TX_IDLE_LVL_LARGE_AMP 0x10
+#define USB43DP_V5_5NM_QSERDES_TXB_TX_DRV_LVL 0x14
+#define USB43DP_V5_5NM_QSERDES_TXB_TX_DRV_LVL_OFFSET 0x18
+#define USB43DP_V5_5NM_QSERDES_TXB_RESET_TSYNC_EN 0x1c
+#define USB43DP_V5_5NM_QSERDES_TXB_PRE_STALL_LDO_BOOST_EN 0x20
+#define USB43DP_V5_5NM_QSERDES_TXB_LPB_EN 0x24
+#define USB43DP_V5_5NM_QSERDES_TXB_RES_CODE_LANE_TX 0x28
+#define USB43DP_V5_5NM_QSERDES_TXB_RES_CODE_LANE_RX 0x2c
+#define USB43DP_V5_5NM_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x30
+#define USB43DP_V5_5NM_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x34
+#define USB43DP_V5_5NM_QSERDES_TXB_PERL_LENGTH1 0x38
+#define USB43DP_V5_5NM_QSERDES_TXB_PERL_LENGTH2 0x3c
+#define USB43DP_V5_5NM_QSERDES_TXB_SERDES_BYP_EN_OUT 0x40
+#define USB43DP_V5_5NM_QSERDES_TXB_DEBUG_BUS_SEL 0x44
+#define USB43DP_V5_5NM_QSERDES_TXB_TRANSCEIVER_BIAS_EN 0x48
+#define USB43DP_V5_5NM_QSERDES_TXB_HIGHZ_DRVR_EN 0x4c
+#define USB43DP_V5_5NM_QSERDES_TXB_TX_POL_INV 0x50
+#define USB43DP_V5_5NM_QSERDES_TXB_PARRATE_REC_DETECT_IDLE_EN 0x54
+#define USB43DP_V5_5NM_QSERDES_TXB_BIST_PATTERN1 0x58
+#define USB43DP_V5_5NM_QSERDES_TXB_BIST_PATTERN2 0x5c
+#define USB43DP_V5_5NM_QSERDES_TXB_BIST_PATTERN3 0x60
+#define USB43DP_V5_5NM_QSERDES_TXB_BIST_PATTERN4 0x64
+#define USB43DP_V5_5NM_QSERDES_TXB_BIST_PATTERN5 0x68
+#define USB43DP_V5_5NM_QSERDES_TXB_BIST_PATTERN6 0x6c
+#define USB43DP_V5_5NM_QSERDES_TXB_BIST_PATTERN7 0x70
+#define USB43DP_V5_5NM_QSERDES_TXB_BIST_PATTERN8 0x74
+#define USB43DP_V5_5NM_QSERDES_TXB_LANE_MODE_1 0x78
+#define USB43DP_V5_5NM_QSERDES_TXB_LANE_MODE_2 0x7c
+#define USB43DP_V5_5NM_QSERDES_TXB_LANE_MODE_3 0x80
+#define USB43DP_V5_5NM_QSERDES_TXB_ATB_SEL1 0x84
+#define USB43DP_V5_5NM_QSERDES_TXB_ATB_SEL2 0x88
+#define USB43DP_V5_5NM_QSERDES_TXB_RCV_DETECT_LVL 0x8c
+#define USB43DP_V5_5NM_QSERDES_TXB_RCV_DETECT_LVL_2 0x90
+#define USB43DP_V5_5NM_QSERDES_TXB_PRBS_SEED1 0x94
+#define USB43DP_V5_5NM_QSERDES_TXB_PRBS_SEED2 0x98
+#define USB43DP_V5_5NM_QSERDES_TXB_PRBS_SEED3 0x9c
+#define USB43DP_V5_5NM_QSERDES_TXB_PRBS_SEED4 0xa0
+#define USB43DP_V5_5NM_QSERDES_TXB_RESET_GEN 0xa4
+#define USB43DP_V5_5NM_QSERDES_TXB_RESET_GEN_MUXES 0xa8
+#define USB43DP_V5_5NM_QSERDES_TXB_TRAN_DRVR_EMP_EN 0xac
+#define USB43DP_V5_5NM_QSERDES_TXB_VMODE_CTRL1 0xb0
+#define USB43DP_V5_5NM_QSERDES_TXB_ALOG_OBSV_BUS_CTRL_1 0xb4
+#define USB43DP_V5_5NM_QSERDES_TXB_BIST_STATUS 0xb8
+#define USB43DP_V5_5NM_QSERDES_TXB_BIST_ERROR_COUNT1 0xbc
+#define USB43DP_V5_5NM_QSERDES_TXB_BIST_ERROR_COUNT2 0xc0
+#define USB43DP_V5_5NM_QSERDES_TXB_ALOG_OBSV_BUS_STATUS_1 0xc4
+#define USB43DP_V5_5NM_QSERDES_TXB_LANE_DIG_CONFIG 0xc8
+#define USB43DP_V5_5NM_QSERDES_TXB_PI_QEC_CTRL 0xcc
+#define USB43DP_V5_5NM_QSERDES_TXB_PRE_EMPH 0xd0
+#define USB43DP_V5_5NM_QSERDES_TXB_SW_RESET 0xd4
+#define USB43DP_V5_5NM_QSERDES_TXB_TX_BAND 0xd8
+#define USB43DP_V5_5NM_QSERDES_TXB_SLEW_CNTL0 0xdc
+#define USB43DP_V5_5NM_QSERDES_TXB_SLEW_CNTL1 0xe0
+#define USB43DP_V5_5NM_QSERDES_TXB_INTERFACE_SELECT 0xe4
+#define USB43DP_V5_5NM_QSERDES_TXB_DIG_BKUP_CTRL 0xe8
+#define USB43DP_V5_5NM_QSERDES_TXB_DEBUG_BUS0 0xec
+#define USB43DP_V5_5NM_QSERDES_TXB_DEBUG_BUS1 0xf0
+#define USB43DP_V5_5NM_QSERDES_TXB_DEBUG_BUS2 0xf4
+#define USB43DP_V5_5NM_QSERDES_TXB_DEBUG_BUS3 0xf8
+#define USB43DP_V5_5NM_QSERDES_TXB_TX_BKUP_RO_BUS 0xfc
+
+/* Module: USB43DP_QSERDES_RXB_USB43DP_QSERDES_RXB_USB4_USB3_DP_QMP_RX */
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN_RATE0 0x000
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN_RATE1 0x004
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN_RATE2 0x008
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN_RATE3 0x00c
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FASTLOCK_SO_GAIN_RATE0 0x010
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FASTLOCK_SO_GAIN_RATE1 0x014
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FASTLOCK_SO_GAIN_RATE2 0x018
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FASTLOCK_SO_GAIN_RATE3 0x01c
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SO_SATURATION 0x020
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FO_TO_SO_DELAY 0x024
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW_RATE0 0x028
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH_RATE0 0x02c
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW_RATE1 0x030
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH_RATE1 0x034
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW_RATE2 0x038
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH_RATE2 0x03c
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW_RATE3 0x040
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH_RATE3 0x044
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_PI_CTRL1 0x048
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_PI_CTRL2 0x04c
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SB2_THRESH1_RATE0 0x050
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SB2_THRESH1_RATE1 0x054
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SB2_THRESH1_RATE2 0x058
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SB2_THRESH1_RATE3 0x05c
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SB2_THRESH2_RATE0 0x060
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SB2_THRESH2_RATE1 0x064
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SB2_THRESH2_RATE2 0x068
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SB2_THRESH2_RATE3 0x06c
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SB2_GAIN1_RATE0 0x070
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SB2_GAIN1_RATE1 0x074
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SB2_GAIN1_RATE2 0x078
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SB2_GAIN1_RATE3 0x07c
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SB2_GAIN2_RATE0 0x080
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SB2_GAIN2_RATE1 0x084
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SB2_GAIN2_RATE2 0x088
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SB2_GAIN2_RATE3 0x08c
+#define USB43DP_V5_5NM_QSERDES_RXB_RXCLK_DIV2_CTRL 0x090
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_BAND 0x094
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_TERM_BW 0x098
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FO_GAIN_RATE0 0x09c
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FO_GAIN_RATE1 0x0a0
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FO_GAIN_RATE2 0x0a4
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FO_GAIN_RATE3 0x0a8
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SO_GAIN_RATE0 0x0ac
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SO_GAIN_RATE1 0x0b0
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SO_GAIN_RATE2 0x0b4
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SO_GAIN_RATE3 0x0b8
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_PI_CONTROLS 0x0bc
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_PD_DATA_FILTER_ENABLES 0x0c0
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SO_ACC_DEFAULT_VAL_RATE0 0x0c4
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SO_ACC_DEFAULT_VAL_RATE1 0x0c8
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SO_ACC_DEFAULT_VAL_RATE2 0x0cc
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SO_ACC_DEFAULT_VAL_RATE3 0x0d0
+#define USB43DP_V5_5NM_QSERDES_RXB_AUX_CONTROL 0x0d4
+#define USB43DP_V5_5NM_QSERDES_RXB_AUXDATA_TB 0x0d8
+#define USB43DP_V5_5NM_QSERDES_RXB_RCLK_AUXDATA_SEL 0x0dc
+#define USB43DP_V5_5NM_QSERDES_RXB_EOM_CTRL 0x0e0
+#define USB43DP_V5_5NM_QSERDES_RXB_AC_JTAG_ENABLE 0x0e4
+#define USB43DP_V5_5NM_QSERDES_RXB_AC_JTAG_INITP 0x0e8
+#define USB43DP_V5_5NM_QSERDES_RXB_AC_JTAG_INITN 0x0ec
+#define USB43DP_V5_5NM_QSERDES_RXB_AC_JTAG_LVL 0x0f0
+#define USB43DP_V5_5NM_QSERDES_RXB_AC_JTAG_MODE 0x0f4
+#define USB43DP_V5_5NM_QSERDES_RXB_AC_JTAG_RESET 0x0f8
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_RCVR_IQ_EN 0x0fc
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_Q_EN_RATES 0x100
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_IDAC_I0_DC_OFFSETS 0x104
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_IDAC_I0BAR_DC_OFFSETS 0x108
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_IDAC_I1_DC_OFFSETS 0x10c
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_IDAC_I1BAR_DC_OFFSETS 0x110
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_IDAC_Q_DC_OFFSETS 0x114
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_IDAC_QBAR_DC_OFFSETS 0x118
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_IDAC_A_DC_OFFSETS 0x11c
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_IDAC_ABAR_DC_OFFSETS 0x120
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_IDAC_EN 0x124
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_IDAC_ENABLES 0x128
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_IDAC_SIGN 0x12c
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_IVCM_CAL_CODE_OVERRIDE 0x130
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_IVCM_CAL_CTRL1 0x134
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_IVCM_CAL_CTRL2 0x138
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_IVCM_POSTCAL_OFFSET 0x13c
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_SUMMER_CAL_SPD_MODE 0x140
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_HIGHZ_PARRATE 0x144
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x148
+#define USB43DP_V5_5NM_QSERDES_RXB_DFE_1 0x14c
+#define USB43DP_V5_5NM_QSERDES_RXB_DFE_2 0x150
+#define USB43DP_V5_5NM_QSERDES_RXB_DFE_3 0x154
+#define USB43DP_V5_5NM_QSERDES_RXB_DFE_4 0x158
+#define USB43DP_V5_5NM_QSERDES_RXB_DFE_TAP3_CTRL 0x15c
+#define USB43DP_V5_5NM_QSERDES_RXB_DFE_TAP3_MANVAL_KTAP 0x160
+#define USB43DP_V5_5NM_QSERDES_RXB_DFE_TAP4_CTRL 0x164
+#define USB43DP_V5_5NM_QSERDES_RXB_DFE_TAP4_MANVAL_KTAP 0x168
+#define USB43DP_V5_5NM_QSERDES_RXB_DFE_TAP5_CTRL 0x16c
+#define USB43DP_V5_5NM_QSERDES_RXB_DFE_TAP5_MANVAL_KTAP 0x170
+#define USB43DP_V5_5NM_QSERDES_RXB_TX_ADPT_CTRL 0x174
+#define USB43DP_V5_5NM_QSERDES_RXB_DFE_DAC_ENABLE1 0x178
+#define USB43DP_V5_5NM_QSERDES_RXB_DFE_DAC_ENABLE2 0x17c
+#define USB43DP_V5_5NM_QSERDES_RXB_TX_ADAPT_PRE_THRESH1 0x180
+#define USB43DP_V5_5NM_QSERDES_RXB_TX_ADAPT_PRE_THRESH2 0x184
+#define USB43DP_V5_5NM_QSERDES_RXB_TX_ADAPT_POST_THRESH1 0x188
+#define USB43DP_V5_5NM_QSERDES_RXB_TX_ADAPT_POST_THRESH2 0x18c
+#define USB43DP_V5_5NM_QSERDES_RXB_TX_ADAPT_MAIN_THRESH1 0x190
+#define USB43DP_V5_5NM_QSERDES_RXB_TX_ADAPT_MAIN_THRESH2 0x194
+#define USB43DP_V5_5NM_QSERDES_RXB_VGA_CAL_CNTRL1 0x198
+#define USB43DP_V5_5NM_QSERDES_RXB_VGA_CAL_CNTRL2 0x19c
+#define USB43DP_V5_5NM_QSERDES_RXB_VGA_CAL_MAN_VAL 0x1a0
+#define USB43DP_V5_5NM_QSERDES_RXB_VTHRESH_CAL_CNTRL1 0x1a4
+#define USB43DP_V5_5NM_QSERDES_RXB_VTHRESH_CAL_CNTRL2 0x1a8
+#define USB43DP_V5_5NM_QSERDES_RXB_VTHRESH_CAL_MAN_VAL_RATE0 0x1ac
+#define USB43DP_V5_5NM_QSERDES_RXB_VTHRESH_CAL_MAN_VAL_RATE1 0x1b0
+#define USB43DP_V5_5NM_QSERDES_RXB_VTHRESH_CAL_MAN_VAL_RATE2 0x1b4
+#define USB43DP_V5_5NM_QSERDES_RXB_VTHRESH_CAL_MAN_VAL_RATE3 0x1b8
+#define USB43DP_V5_5NM_QSERDES_RXB_GM_CAL 0x1bc
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_VGA_GAIN2_BLK1 0x1c0
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_VGA_GAIN2_BLK2 0x1c4
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x1c8
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x1cc
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x1d0
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0x1d4
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_EQ_OFFSET_LSB 0x1d8
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_EQ_OFFSET_MSB 0x1dc
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1e0
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_OFFSET_ADAPTOR_CNTRL2 0x1e4
+#define USB43DP_V5_5NM_QSERDES_RXB_SIGDET_ENABLES 0x1e8
+#define USB43DP_V5_5NM_QSERDES_RXB_SIGDET_CNTRL 0x1ec
+#define USB43DP_V5_5NM_QSERDES_RXB_SIGDET_LVL 0x1f0
+#define USB43DP_V5_5NM_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x1f4
+#define USB43DP_V5_5NM_QSERDES_RXB_CDR_FREEZE_UP_DN 0x1f8
+#define USB43DP_V5_5NM_QSERDES_RXB_CDR_RESET_OVERRIDE 0x1fc
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_INTERFACE_MODE 0x200
+#define USB43DP_V5_5NM_QSERDES_RXB_JITTER_GEN_MODE 0x204
+#define USB43DP_V5_5NM_QSERDES_RXB_SJ_AMP1 0x208
+#define USB43DP_V5_5NM_QSERDES_RXB_SJ_AMP2 0x20c
+#define USB43DP_V5_5NM_QSERDES_RXB_SJ_PER1 0x210
+#define USB43DP_V5_5NM_QSERDES_RXB_SJ_PER2 0x214
+#define USB43DP_V5_5NM_QSERDES_RXB_PPM_OFFSET1 0x218
+#define USB43DP_V5_5NM_QSERDES_RXB_PPM_OFFSET2 0x21c
+#define USB43DP_V5_5NM_QSERDES_RXB_SIGN_PPM_PERIOD1 0x220
+#define USB43DP_V5_5NM_QSERDES_RXB_SIGN_PPM_PERIOD2 0x224
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE_0_1_B0 0x228
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE_0_1_B1 0x22c
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE_0_1_B2 0x230
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE_0_1_B3 0x234
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE_0_1_B4 0x238
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE_0_1_B5 0x23c
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE_0_1_B6 0x240
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE_0_1_B7 0x244
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE2_B0 0x248
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE2_B1 0x24c
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE2_B2 0x250
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE2_B3 0x254
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE2_B4 0x258
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE2_B5 0x25c
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE2_B6 0x260
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE2_B7 0x264
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE3_B0 0x268
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE3_B1 0x26c
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE3_B2 0x270
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE3_B3 0x274
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE3_B4 0x278
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE3_B5 0x27c
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE3_B6 0x280
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE3_B7 0x284
+#define USB43DP_V5_5NM_QSERDES_RXB_PHPRE_CTRL 0x288
+#define USB43DP_V5_5NM_QSERDES_RXB_PHPRE_INITVAL 0x28c
+#define USB43DP_V5_5NM_QSERDES_RXB_DFE_EN_TIMER 0x290
+#define USB43DP_V5_5NM_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x294
+#define USB43DP_V5_5NM_QSERDES_RXB_DCC_CTRL1 0x298
+#define USB43DP_V5_5NM_QSERDES_RXB_DCC_CTRL2 0x29c
+#define USB43DP_V5_5NM_QSERDES_RXB_DCC_OFFSET 0x2a0
+#define USB43DP_V5_5NM_QSERDES_RXB_DCC_CMUX_POSTCAL_OFFSET 0x2a4
+#define USB43DP_V5_5NM_QSERDES_RXB_DCC_CMUX_CAL_CTRL1 0x2a8
+#define USB43DP_V5_5NM_QSERDES_RXB_DCC_CMUX_CAL_CTRL2 0x2ac
+#define USB43DP_V5_5NM_QSERDES_RXB_ALOG_OBSV_BUS_CTRL_1 0x2b0
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_CTRL1 0x2b4
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_CTRL2 0x2b8
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_CTRL3 0x2bc
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_CTRL_4 0x2c0
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_CFG_RATE_0_1 0x2c4
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_CFG_RATE_2_3 0x2c8
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_CTRL1 0x2cc
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_CTRL2 0x2d0
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_THRESH1_RATE210 0x2d4
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_THRESH1_RATE3 0x2d8
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_THRESH2_RATE210 0x2dc
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_THRESH2_RATE3 0x2e0
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_THRESH3_RATE210 0x2e4
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_THRESH3_RATE3 0x2e8
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_THRESH4_RATE210 0x2ec
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_THRESH4_RATE3 0x2f0
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_THRESH5_RATE210 0x2f4
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_THRESH5_RATE3 0x2f8
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_THRESH6_RATE210 0x2fc
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_THRESH6_RATE3 0x300
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_THRESH7_RATE210 0x304
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_THRESH7_RATE3 0x308
+#define USB43DP_V5_5NM_QSERDES_RXB_Q_PI_INTRINSIC_BIAS_RATE10 0x30c
+#define USB43DP_V5_5NM_QSERDES_RXB_Q_PI_INTRINSIC_BIAS_RATE32 0x310
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_VERTICAL_CTRL 0x314
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_VERTICAL_CODE 0x318
+#define USB43DP_V5_5NM_QSERDES_RXB_RES_CODE_THRESH_HIGH_AND_BYP 0x31c
+#define USB43DP_V5_5NM_QSERDES_RXB_RES_CODE_THRESH_LOW 0x320
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_BKUP_CTRL1 0x324
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_BKUP_CTRL2 0x328
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_BKUP_CTRL3 0x32c
+#define USB43DP_V5_5NM_QSERDES_RXB_PI_CTRL1 0x330
+#define USB43DP_V5_5NM_QSERDES_RXB_PI_CTRL2 0x334
+#define USB43DP_V5_5NM_QSERDES_RXB_PI_QUAD 0x338
+#define USB43DP_V5_5NM_QSERDES_RXB_QPI_CTRL1 0x33c
+#define USB43DP_V5_5NM_QSERDES_RXB_QPI_CTRL2 0x340
+#define USB43DP_V5_5NM_QSERDES_RXB_QPI_QUAD 0x344
+#define USB43DP_V5_5NM_QSERDES_RXB_IDATA1 0x348
+#define USB43DP_V5_5NM_QSERDES_RXB_IDATA2 0x34c
+#define USB43DP_V5_5NM_QSERDES_RXB_IDATA3 0x350
+#define USB43DP_V5_5NM_QSERDES_RXB_AC_JTAG_OUTP 0x354
+#define USB43DP_V5_5NM_QSERDES_RXB_AC_JTAG_OUTN 0x358
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_SIGDET 0x35c
+#define USB43DP_V5_5NM_QSERDES_RXB_ALOG_OBSV_BUS_STATUS_1 0x360
+#define USB43DP_V5_5NM_QSERDES_RXB_READ_EQCODE 0x364
+#define USB43DP_V5_5NM_QSERDES_RXB_READ_OFFSETCODE 0x368
+#define USB43DP_V5_5NM_QSERDES_RXB_IA_ERROR_COUNTER_LOW 0x36c
+#define USB43DP_V5_5NM_QSERDES_RXB_IA_ERROR_COUNTER_HIGH 0x370
+#define USB43DP_V5_5NM_QSERDES_RXB_VGA_READ_CODE 0x374
+#define USB43DP_V5_5NM_QSERDES_RXB_VTHRESH_READ_CODE 0x378
+#define USB43DP_V5_5NM_QSERDES_RXB_DFE_TAP1_READ_CODE 0x37c
+#define USB43DP_V5_5NM_QSERDES_RXB_DFE_TAP2_READ_CODE 0x380
+#define USB43DP_V5_5NM_QSERDES_RXB_DFE_TAP3_READ_CODE 0x384
+#define USB43DP_V5_5NM_QSERDES_RXB_DFE_TAP4_READ_CODE 0x388
+#define USB43DP_V5_5NM_QSERDES_RXB_DFE_TAP5_READ_CODE 0x38c
+#define USB43DP_V5_5NM_QSERDES_RXB_IDAC_STATUS_I0 0x390
+#define USB43DP_V5_5NM_QSERDES_RXB_IDAC_STATUS_I0BAR 0x394
+#define USB43DP_V5_5NM_QSERDES_RXB_IDAC_STATUS_I1 0x398
+#define USB43DP_V5_5NM_QSERDES_RXB_IDAC_STATUS_I1BAR 0x39c
+#define USB43DP_V5_5NM_QSERDES_RXB_IDAC_STATUS_Q 0x3a0
+#define USB43DP_V5_5NM_QSERDES_RXB_IDAC_STATUS_QBAR 0x3a4
+#define USB43DP_V5_5NM_QSERDES_RXB_IDAC_STATUS_A 0x3a8
+#define USB43DP_V5_5NM_QSERDES_RXB_IDAC_STATUS_ABAR 0x3ac
+#define USB43DP_V5_5NM_QSERDES_RXB_IDAC_STATUS_SM_ON 0x3b0
+#define USB43DP_V5_5NM_QSERDES_RXB_IDAC_STATUS_SIGNERROR 0x3b4
+#define USB43DP_V5_5NM_QSERDES_RXB_IVCM_CAL_STATUS 0x3b8
+#define USB43DP_V5_5NM_QSERDES_RXB_IVCM_CAL_DEBUG_STATUS 0x3bc
+#define USB43DP_V5_5NM_QSERDES_RXB_DCC_CAL_STATUS 0x3c0
+#define USB43DP_V5_5NM_QSERDES_RXB_DCC_READ_CODE_STATUS 0x3c4
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_DEBUG1_STATUS 0x3c8
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_DEBUG2_STATUS 0x3cc
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_READ_CODE_STATUS 0x3d0
+#define USB43DP_V5_5NM_QSERDES_RXB_EOM_ERR_CNT_LSB_STATUS 0x3d4
+#define USB43DP_V5_5NM_QSERDES_RXB_EOM_ERR_CNT_MSB_STATUS 0x3d8
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_TUNE_STATUS 0x3dc
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_BKUP_READ_BUS1_STATUS 0x3e0
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_BKUP_READ_BUS2_STATUS 0x3e4
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_BKUP_READ_BUS3_STATUS 0x3e8
+
+/* Module: USB3_QSERDES_PLL_USB3_QSERDES_PLL_USB4_USB3_DP_QMP_PLL_20G */
+#define USB3_V5_5NM_QSERDES_PLL_ATB_SEL1 0x000
+#define USB3_V5_5NM_QSERDES_PLL_ATB_SEL2 0x004
+#define USB3_V5_5NM_QSERDES_PLL_FREQ_UPDATE 0x008
+#define USB3_V5_5NM_QSERDES_PLL_BG_TIMER 0x00c
+#define USB3_V5_5NM_QSERDES_PLL_SSC_EN_CENTER 0x010
+#define USB3_V5_5NM_QSERDES_PLL_SSC_ADJ_PER1 0x014
+#define USB3_V5_5NM_QSERDES_PLL_SSC_ADJ_PER2 0x018
+#define USB3_V5_5NM_QSERDES_PLL_SSC_PER1 0x01c
+#define USB3_V5_5NM_QSERDES_PLL_SSC_PER2 0x020
+#define USB3_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024
+#define USB3_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x028
+#define USB3_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE3_MODE0 0x02c
+#define USB3_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x030
+#define USB3_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x034
+#define USB3_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE3_MODE1 0x038
+#define USB3_V5_5NM_QSERDES_PLL_POST_DIV 0x03c
+#define USB3_V5_5NM_QSERDES_PLL_POST_DIV_MUX 0x040
+#define USB3_V5_5NM_QSERDES_PLL_BIAS_EN_CLKBUFLR_EN 0x044
+#define USB3_V5_5NM_QSERDES_PLL_CLK_ENABLE1 0x048
+#define USB3_V5_5NM_QSERDES_PLL_SYS_CLK_CTRL 0x04c
+#define USB3_V5_5NM_QSERDES_PLL_SYSCLK_BUF_ENABLE 0x050
+#define USB3_V5_5NM_QSERDES_PLL_PLL_EN 0x054
+#define USB3_V5_5NM_QSERDES_PLL_PLL_IVCO 0x058
+#define USB3_V5_5NM_QSERDES_PLL_CMN_IETRIM 0x05c
+#define USB3_V5_5NM_QSERDES_PLL_CMN_IPTRIM 0x060
+#define USB3_V5_5NM_QSERDES_PLL_EP_CLOCK_DETECT_CTRL 0x064
+#define USB3_V5_5NM_QSERDES_PLL_SYSCLK_DET_COMP_STATUS 0x068
+#define USB3_V5_5NM_QSERDES_PLL_CLK_EP_DIV_MODE0 0x06c
+#define USB3_V5_5NM_QSERDES_PLL_CLK_EP_DIV_MODE1 0x070
+#define USB3_V5_5NM_QSERDES_PLL_CP_CTRL_MODE0 0x074
+#define USB3_V5_5NM_QSERDES_PLL_CP_CTRL_MODE1 0x078
+#define USB3_V5_5NM_QSERDES_PLL_PLL_RCTRL_MODE0 0x07c
+#define USB3_V5_5NM_QSERDES_PLL_PLL_RCTRL_MODE1 0x080
+#define USB3_V5_5NM_QSERDES_PLL_PLL_CCTRL_MODE0 0x084
+#define USB3_V5_5NM_QSERDES_PLL_PLL_CCTRL_MODE1 0x088
+#define USB3_V5_5NM_QSERDES_PLL_PLL_CNTRL 0x08c
+#define USB3_V5_5NM_QSERDES_PLL_BIAS_EN_CTRL_BY_PSM 0x090
+#define USB3_V5_5NM_QSERDES_PLL_SYSCLK_EN_SEL 0x094
+#define USB3_V5_5NM_QSERDES_PLL_CML_SYSCLK_SEL 0x098
+#define USB3_V5_5NM_QSERDES_PLL_RESETSM_CNTRL 0x09c
+#define USB3_V5_5NM_QSERDES_PLL_RESETSM_CNTRL2 0x0a0
+#define USB3_V5_5NM_QSERDES_PLL_LOCK_CMP_EN 0x0a4
+#define USB3_V5_5NM_QSERDES_PLL_LOCK_CMP_CFG 0x0a8
+#define USB3_V5_5NM_QSERDES_PLL_LOCK_CMP1_MODE0 0x0ac
+#define USB3_V5_5NM_QSERDES_PLL_LOCK_CMP2_MODE0 0x0b0
+#define USB3_V5_5NM_QSERDES_PLL_LOCK_CMP1_MODE1 0x0b4
+#define USB3_V5_5NM_QSERDES_PLL_LOCK_CMP2_MODE1 0x0b8
+#define USB3_V5_5NM_QSERDES_PLL_DEC_START_MODE0 0x0bc
+#define USB3_V5_5NM_QSERDES_PLL_DEC_START_MSB_MODE0 0x0c0
+#define USB3_V5_5NM_QSERDES_PLL_DEC_START_MODE1 0x0c4
+#define USB3_V5_5NM_QSERDES_PLL_DEC_START_MSB_MODE1 0x0c8
+#define USB3_V5_5NM_QSERDES_PLL_DIV_FRAC_START1_MODE0 0x0cc
+#define USB3_V5_5NM_QSERDES_PLL_DIV_FRAC_START2_MODE0 0x0d0
+#define USB3_V5_5NM_QSERDES_PLL_DIV_FRAC_START3_MODE0 0x0d4
+#define USB3_V5_5NM_QSERDES_PLL_DIV_FRAC_START1_MODE1 0x0d8
+#define USB3_V5_5NM_QSERDES_PLL_DIV_FRAC_START2_MODE1 0x0dc
+#define USB3_V5_5NM_QSERDES_PLL_DIV_FRAC_START3_MODE1 0x0e0
+#define USB3_V5_5NM_QSERDES_PLL_INTEGLOOP_INITVAL 0x0e4
+#define USB3_V5_5NM_QSERDES_PLL_INTEGLOOP_EN 0x0e8
+#define USB3_V5_5NM_QSERDES_PLL_INTEGLOOP_GAIN0_MODE0 0x0ec
+#define USB3_V5_5NM_QSERDES_PLL_INTEGLOOP_GAIN1_MODE0 0x0f0
+#define USB3_V5_5NM_QSERDES_PLL_INTEGLOOP_GAIN0_MODE1 0x0f4
+#define USB3_V5_5NM_QSERDES_PLL_INTEGLOOP_GAIN1_MODE1 0x0f8
+#define USB3_V5_5NM_QSERDES_PLL_INTEGLOOP_P_PATH_GAIN0 0x0fc
+#define USB3_V5_5NM_QSERDES_PLL_INTEGLOOP_P_PATH_GAIN1 0x100
+#define USB3_V5_5NM_QSERDES_PLL_VCOCAL_DEADMAN_CTRL 0x104
+#define USB3_V5_5NM_QSERDES_PLL_VCO_TUNE_CTRL 0x108
+#define USB3_V5_5NM_QSERDES_PLL_VCO_TUNE_MAP 0x10c
+#define USB3_V5_5NM_QSERDES_PLL_VCO_TUNE1_MODE0 0x110
+#define USB3_V5_5NM_QSERDES_PLL_VCO_TUNE2_MODE0 0x114
+#define USB3_V5_5NM_QSERDES_PLL_VCO_TUNE1_MODE1 0x118
+#define USB3_V5_5NM_QSERDES_PLL_VCO_TUNE2_MODE1 0x11c
+#define USB3_V5_5NM_QSERDES_PLL_VCO_TUNE_INITVAL1 0x120
+#define USB3_V5_5NM_QSERDES_PLL_VCO_TUNE_INITVAL2 0x124
+#define USB3_V5_5NM_QSERDES_PLL_VCO_TUNE_MINVAL1 0x128
+#define USB3_V5_5NM_QSERDES_PLL_VCO_TUNE_MINVAL2 0x12c
+#define USB3_V5_5NM_QSERDES_PLL_VCO_TUNE_MAXVAL1 0x130
+#define USB3_V5_5NM_QSERDES_PLL_VCO_TUNE_MAXVAL2 0x134
+#define USB3_V5_5NM_QSERDES_PLL_VCO_TUNE_TIMER1 0x138
+#define USB3_V5_5NM_QSERDES_PLL_VCO_TUNE_TIMER2 0x13c
+#define USB3_V5_5NM_QSERDES_PLL_CMN_STATUS 0x140
+#define USB3_V5_5NM_QSERDES_PLL_RESET_SM_STATUS 0x144
+#define USB3_V5_5NM_QSERDES_PLL_RESTRIM_CODE_STATUS 0x148
+#define USB3_V5_5NM_QSERDES_PLL_PLLCAL_CODE1_STATUS 0x14c
+#define USB3_V5_5NM_QSERDES_PLL_PLLCAL_CODE2_STATUS 0x150
+#define USB3_V5_5NM_QSERDES_PLL_CLK_SELECT 0x154
+#define USB3_V5_5NM_QSERDES_PLL_HSCLK_SEL 0x158
+#define USB3_V5_5NM_QSERDES_PLL_HSCLK_HS_SWITCH_SEL 0x15c
+#define USB3_V5_5NM_QSERDES_PLL_INTEGLOOP_BINCODE_STATUS 0x160
+#define USB3_V5_5NM_QSERDES_PLL_PLL_ANALOG 0x164
+#define USB3_V5_5NM_QSERDES_PLL_CORECLK_DIV_MODE0 0x168
+#define USB3_V5_5NM_QSERDES_PLL_CORECLK_DIV_MODE1 0x16c
+#define USB3_V5_5NM_QSERDES_PLL_SW_RESET 0x170
+#define USB3_V5_5NM_QSERDES_PLL_CORE_CLK_EN 0x174
+#define USB3_V5_5NM_QSERDES_PLL_C_READY_STATUS 0x178
+#define USB3_V5_5NM_QSERDES_PLL_CMN_CONFIG 0x17c
+#define USB3_V5_5NM_QSERDES_PLL_CMN_RATE_OVERRIDE 0x180
+#define USB3_V5_5NM_QSERDES_PLL_SVS_MODE_CLK_SEL 0x184
+#define USB3_V5_5NM_QSERDES_PLL_DEBUG_BUS0 0x188
+#define USB3_V5_5NM_QSERDES_PLL_DEBUG_BUS1 0x18c
+#define USB3_V5_5NM_QSERDES_PLL_DEBUG_BUS2 0x190
+#define USB3_V5_5NM_QSERDES_PLL_DEBUG_BUS3 0x194
+#define USB3_V5_5NM_QSERDES_PLL_DEBUG_BUS_SEL 0x198
+#define USB3_V5_5NM_QSERDES_PLL_CMN_MISC1 0x19c
+#define USB3_V5_5NM_QSERDES_PLL_CMN_MODE 0x1a0
+#define USB3_V5_5NM_QSERDES_PLL_CMN_MODE_CONTD 0x1a4
+#define USB3_V5_5NM_QSERDES_PLL_VCO_DC_LEVEL_CTRL 0x1a8
+#define USB3_V5_5NM_QSERDES_PLL_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac
+#define USB3_V5_5NM_QSERDES_PLL_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0
+#define USB3_V5_5NM_QSERDES_PLL_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4
+#define USB3_V5_5NM_QSERDES_PLL_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8
+#define USB3_V5_5NM_QSERDES_PLL_BIN_VCOCAL_HSCLK_SEL 0x1bc
+#define USB3_V5_5NM_QSERDES_PLL_ADDITIONAL_CTRL_1 0x1c0
+#define USB3_V5_5NM_QSERDES_PLL_MODE_OPERATION_STATUS 0x1c4
+#define USB3_V5_5NM_QSERDES_PLL_AUTO_GAIN_ADJ_CTRL_1 0x1c8
+#define USB3_V5_5NM_QSERDES_PLL_AUTO_GAIN_ADJ_CTRL_2 0x1cc
+#define USB3_V5_5NM_QSERDES_PLL_AUTO_GAIN_ADJ_CTRL_3 0x1d0
+#define USB3_V5_5NM_QSERDES_PLL_AUTO_GAIN_ADJ_CTRL_4 0x1d4
+#define USB3_V5_5NM_QSERDES_PLL_ADDITIONAL_MISC 0x1d8
+#define USB3_V5_5NM_QSERDES_PLL_ADDITIONAL_MISC_2 0x1dc
+#define USB3_V5_5NM_QSERDES_PLL_ADDITIONAL_MISC_3 0x1e0
+
+/* Module: USB3_PCS_MISC_USB3_PCS_MISC_USB3_PCS_MISC */
+#define USB3_V5_5NM_PCS_MISC_TYPEC_CTRL 0x00
+#define USB3_V5_5NM_PCS_MISC_TYPEC_PWRDN_CTRL 0x04
+#define USB3_V5_5NM_PCS_MISC_PCS_MISC_CONFIG1 0x08
+#define USB3_V5_5NM_PCS_MISC_CLAMP_ENABLE 0x0c
+#define USB3_V5_5NM_PCS_MISC_TYPEC_STATUS 0x10
+#define USB3_V5_5NM_PCS_MISC_PLACEHOLDER_STATUS 0x14
+
+/* Module: USB3_PCS_LN_USB3_PCS_LN_USB3_PCS_LANE */
+#define USB3_V5_5NM_PCS_LN_PCS_STATUS1 0x00
+#define USB3_V5_5NM_PCS_LN_PCS_STATUS2 0x04
+#define USB3_V5_5NM_PCS_LN_PCS_STATUS2_CLEAR 0x08
+#define USB3_V5_5NM_PCS_LN_PCS_STATUS3 0x0c
+#define USB3_V5_5NM_PCS_LN_BIST_CHK_ERR_CNT_L_STATUS 0x10
+#define USB3_V5_5NM_PCS_LN_BIST_CHK_ERR_CNT_H_STATUS 0x14
+#define USB3_V5_5NM_PCS_LN_BIST_CHK_STATUS 0x18
+#define USB3_V5_5NM_PCS_LN_INSIG_SW_CTRL1 0x1c
+#define USB3_V5_5NM_PCS_LN_INSIG_MX_CTRL1 0x20
+#define USB3_V5_5NM_PCS_LN_OUTSIG_SW_CTRL1 0x24
+#define USB3_V5_5NM_PCS_LN_OUTSIG_MX_CTRL1 0x28
+#define USB3_V5_5NM_PCS_LN_TEST_CONTROL1 0x2c
+#define USB3_V5_5NM_PCS_LN_BIST_CTRL 0x30
+#define USB3_V5_5NM_PCS_LN_PRBS_SEED0 0x34
+#define USB3_V5_5NM_PCS_LN_PRBS_SEED1 0x38
+#define USB3_V5_5NM_PCS_LN_FIXED_PAT_CTRL 0x3c
+#define USB3_V5_5NM_PCS_LN_EQ_CONFIG 0x40
+#define USB3_V5_5NM_PCS_LN_TEST_CONTROL2 0x44
+#define USB3_V5_5NM_PCS_LN_TEST_CONTROL3 0x48
+
+/* Module: USB3_PCS_USB3_PCS_USB3_PCS */
+#define USB3_V5_5NM_PCS_SW_RESET 0x000
+#define USB3_V5_5NM_PCS_REVISION_ID0 0x004
+#define USB3_V5_5NM_PCS_REVISION_ID1 0x008
+#define USB3_V5_5NM_PCS_REVISION_ID2 0x00c
+#define USB3_V5_5NM_PCS_REVISION_ID3 0x010
+#define USB3_V5_5NM_PCS_PCS_STATUS1 0x014
+#define USB3_V5_5NM_PCS_PCS_STATUS2 0x018
+#define USB3_V5_5NM_PCS_PCS_STATUS3 0x01c
+#define USB3_V5_5NM_PCS_PCS_STATUS4 0x020
+#define USB3_V5_5NM_PCS_PCS_STATUS5 0x024
+#define USB3_V5_5NM_PCS_PCS_STATUS6 0x028
+#define USB3_V5_5NM_PCS_PCS_STATUS7 0x02c
+#define USB3_V5_5NM_PCS_DEBUG_BUS_0_STATUS 0x030
+#define USB3_V5_5NM_PCS_DEBUG_BUS_1_STATUS 0x034
+#define USB3_V5_5NM_PCS_DEBUG_BUS_2_STATUS 0x038
+#define USB3_V5_5NM_PCS_DEBUG_BUS_3_STATUS 0x03c
+#define USB3_V5_5NM_PCS_POWER_DOWN_CONTROL 0x040
+#define USB3_V5_5NM_PCS_START_CONTROL 0x044
+#define USB3_V5_5NM_PCS_INSIG_SW_CTRL1 0x048
+#define USB3_V5_5NM_PCS_INSIG_SW_CTRL2 0x04c
+#define USB3_V5_5NM_PCS_INSIG_SW_CTRL3 0x050
+#define USB3_V5_5NM_PCS_INSIG_SW_CTRL4 0x054
+#define USB3_V5_5NM_PCS_INSIG_SW_CTRL5 0x058
+#define USB3_V5_5NM_PCS_INSIG_SW_CTRL6 0x05c
+#define USB3_V5_5NM_PCS_INSIG_SW_CTRL7 0x060
+#define USB3_V5_5NM_PCS_INSIG_SW_CTRL8 0x064
+#define USB3_V5_5NM_PCS_INSIG_MX_CTRL1 0x068
+#define USB3_V5_5NM_PCS_INSIG_MX_CTRL2 0x06c
+#define USB3_V5_5NM_PCS_INSIG_MX_CTRL3 0x070
+#define USB3_V5_5NM_PCS_INSIG_MX_CTRL4 0x074
+#define USB3_V5_5NM_PCS_INSIG_MX_CTRL5 0x078
+#define USB3_V5_5NM_PCS_INSIG_MX_CTRL7 0x07c
+#define USB3_V5_5NM_PCS_INSIG_MX_CTRL8 0x080
+#define USB3_V5_5NM_PCS_OUTSIG_SW_CTRL1 0x084
+#define USB3_V5_5NM_PCS_OUTSIG_MX_CTRL1 0x088
+#define USB3_V5_5NM_PCS_CLAMP_ENABLE 0x08c
+#define USB3_V5_5NM_PCS_POWER_STATE_CONFIG1 0x090
+#define USB3_V5_5NM_PCS_POWER_STATE_CONFIG2 0x094
+#define USB3_V5_5NM_PCS_FLL_CNTRL1 0x098
+#define USB3_V5_5NM_PCS_FLL_CNTRL2 0x09c
+#define USB3_V5_5NM_PCS_FLL_CNT_VAL_L 0x0a0
+#define USB3_V5_5NM_PCS_FLL_CNT_VAL_H_TOL 0x0a4
+#define USB3_V5_5NM_PCS_FLL_MAN_CODE 0x0a8
+#define USB3_V5_5NM_PCS_TEST_CONTROL1 0x0ac
+#define USB3_V5_5NM_PCS_TEST_CONTROL2 0x0b0
+#define USB3_V5_5NM_PCS_TEST_CONTROL3 0x0b4
+#define USB3_V5_5NM_PCS_TEST_CONTROL4 0x0b8
+#define USB3_V5_5NM_PCS_TEST_CONTROL5 0x0bc
+#define USB3_V5_5NM_PCS_TEST_CONTROL6 0x0c0
+#define USB3_V5_5NM_PCS_LOCK_DETECT_CONFIG1 0x0c4
+#define USB3_V5_5NM_PCS_LOCK_DETECT_CONFIG2 0x0c8
+#define USB3_V5_5NM_PCS_LOCK_DETECT_CONFIG3 0x0cc
+#define USB3_V5_5NM_PCS_LOCK_DETECT_CONFIG4 0x0d0
+#define USB3_V5_5NM_PCS_LOCK_DETECT_CONFIG5 0x0d4
+#define USB3_V5_5NM_PCS_LOCK_DETECT_CONFIG6 0x0d8
+#define USB3_V5_5NM_PCS_REFGEN_REQ_CONFIG1 0x0dc
+#define USB3_V5_5NM_PCS_REFGEN_REQ_CONFIG2 0x0e0
+#define USB3_V5_5NM_PCS_REFGEN_REQ_CONFIG3 0x0e4
+#define USB3_V5_5NM_PCS_BIST_CTRL 0x0e8
+#define USB3_V5_5NM_PCS_PRBS_POLY0 0x0ec
+#define USB3_V5_5NM_PCS_PRBS_POLY1 0x0f0
+#define USB3_V5_5NM_PCS_FIXED_PAT0 0x0f4
+#define USB3_V5_5NM_PCS_FIXED_PAT1 0x0f8
+#define USB3_V5_5NM_PCS_FIXED_PAT2 0x0fc
+#define USB3_V5_5NM_PCS_FIXED_PAT3 0x100
+#define USB3_V5_5NM_PCS_FIXED_PAT4 0x104
+#define USB3_V5_5NM_PCS_FIXED_PAT5 0x108
+#define USB3_V5_5NM_PCS_FIXED_PAT6 0x10c
+#define USB3_V5_5NM_PCS_FIXED_PAT7 0x110
+#define USB3_V5_5NM_PCS_FIXED_PAT8 0x114
+#define USB3_V5_5NM_PCS_FIXED_PAT9 0x118
+#define USB3_V5_5NM_PCS_FIXED_PAT10 0x11c
+#define USB3_V5_5NM_PCS_FIXED_PAT11 0x120
+#define USB3_V5_5NM_PCS_FIXED_PAT12 0x124
+#define USB3_V5_5NM_PCS_FIXED_PAT13 0x128
+#define USB3_V5_5NM_PCS_FIXED_PAT14 0x12c
+#define USB3_V5_5NM_PCS_FIXED_PAT15 0x130
+#define USB3_V5_5NM_PCS_TXMGN_CONFIG 0x134
+#define USB3_V5_5NM_PCS_G12S1_TXMGN_V0 0x138
+#define USB3_V5_5NM_PCS_G12S1_TXMGN_V1 0x13c
+#define USB3_V5_5NM_PCS_G12S1_TXMGN_V2 0x140
+#define USB3_V5_5NM_PCS_G12S1_TXMGN_V3 0x144
+#define USB3_V5_5NM_PCS_G12S1_TXMGN_V4 0x148
+#define USB3_V5_5NM_PCS_G12S1_TXMGN_V0_RS 0x14c
+#define USB3_V5_5NM_PCS_G12S1_TXMGN_V1_RS 0x150
+#define USB3_V5_5NM_PCS_G12S1_TXMGN_V2_RS 0x154
+#define USB3_V5_5NM_PCS_G12S1_TXMGN_V3_RS 0x158
+#define USB3_V5_5NM_PCS_G12S1_TXMGN_V4_RS 0x15c
+#define USB3_V5_5NM_PCS_G3S2_TXMGN_MAIN 0x160
+#define USB3_V5_5NM_PCS_G3S2_TXMGN_MAIN_RS 0x164
+#define USB3_V5_5NM_PCS_G12S1_TXDEEMPH_M6DB 0x168
+#define USB3_V5_5NM_PCS_G12S1_TXDEEMPH_M3P5DB 0x16c
+#define USB3_V5_5NM_PCS_G3S2_PRE_GAIN 0x170
+#define USB3_V5_5NM_PCS_G3S2_POST_GAIN 0x174
+#define USB3_V5_5NM_PCS_G3S2_PRE_POST_OFFSET 0x178
+#define USB3_V5_5NM_PCS_G3S2_PRE_GAIN_RS 0x17c
+#define USB3_V5_5NM_PCS_G3S2_POST_GAIN_RS 0x180
+#define USB3_V5_5NM_PCS_G3S2_PRE_POST_OFFSET_RS 0x184
+#define USB3_V5_5NM_PCS_RX_SIGDET_LVL 0x188
+#define USB3_V5_5NM_PCS_RX_SIGDET_DTCT_CNTRL 0x18c
+#define USB3_V5_5NM_PCS_RCVR_DTCT_DLY_P1U2_L 0x190
+#define USB3_V5_5NM_PCS_RCVR_DTCT_DLY_P1U2_H 0x194
+#define USB3_V5_5NM_PCS_RATE_SLEW_CNTRL1 0x198
+#define USB3_V5_5NM_PCS_RATE_SLEW_CNTRL2 0x19c
+#define USB3_V5_5NM_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x1a0
+#define USB3_V5_5NM_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4
+#define USB3_V5_5NM_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8
+#define USB3_V5_5NM_PCS_TSYNC_RSYNC_TIME 0x1ac
+#define USB3_V5_5NM_PCS_RX_CONFIG 0x1b0
+#define USB3_V5_5NM_PCS_TSYNC_DLY_TIME 0x1b4
+#define USB3_V5_5NM_PCS_ELECIDLE_DLY_SEL 0x1b8
+#define USB3_V5_5NM_PCS_CMN_ACK_OUT_SEL 0x1bc
+#define USB3_V5_5NM_PCS_ALIGN_DETECT_CONFIG1 0x1c0
+#define USB3_V5_5NM_PCS_ALIGN_DETECT_CONFIG2 0x1c4
+#define USB3_V5_5NM_PCS_ALIGN_DETECT_CONFIG3 0x1c8
+#define USB3_V5_5NM_PCS_ALIGN_DETECT_CONFIG4 0x1cc
+#define USB3_V5_5NM_PCS_PCS_TX_RX_CONFIG 0x1d0
+#define USB3_V5_5NM_PCS_RX_IDLE_DTCT_CNTRL 0x1d4
+#define USB3_V5_5NM_PCS_RX_DCC_CAL_CONFIG 0x1d8
+#define USB3_V5_5NM_PCS_EQ_CONFIG1 0x1dc
+#define USB3_V5_5NM_PCS_EQ_CONFIG2 0x1e0
+#define USB3_V5_5NM_PCS_EQ_CONFIG3 0x1e4
+#define USB3_V5_5NM_PCS_EQ_CONFIG4 0x1E8
+#define USB3_V5_5NM_PCS_EQ_CONFIG5 0x1EC
+
+/* Module: USB3_PCS_USB3_USB3_PCS_USB3_USB3_PCS_USB3 */
+#define USB3_V5_5NM_PCS_USB3_POWER_STATE_CONFIG1 0x00
+#define USB3_V5_5NM_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x04
+#define USB3_V5_5NM_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x08
+#define USB3_V5_5NM_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x0c
+#define USB3_V5_5NM_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x10
+#define USB3_V5_5NM_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x14
+#define USB3_V5_5NM_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x18
+#define USB3_V5_5NM_PCS_USB3_LFPS_TX_ECSTART 0x1c
+#define USB3_V5_5NM_PCS_USB3_LFPS_PER_TIMER_VAL 0x20
+#define USB3_V5_5NM_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x24
+#define USB3_V5_5NM_PCS_USB3_LFPS_CONFIG1 0x28
+#define USB3_V5_5NM_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x2c
+#define USB3_V5_5NM_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x30
+#define USB3_V5_5NM_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x34
+#define USB3_V5_5NM_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x38
+#define USB3_V5_5NM_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x3c
+#define USB3_V5_5NM_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x40
+#define USB3_V5_5NM_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x44
+#define USB3_V5_5NM_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x48
+#define USB3_V5_5NM_PCS_USB3_ARCVR_DTCT_CM_DLY 0x4c
+#define USB3_V5_5NM_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x50
+#define USB3_V5_5NM_PCS_USB3_ALFPS_DEGLITCH_VAL 0x54
+#define USB3_V5_5NM_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x58
+#define USB3_V5_5NM_PCS_USB3_TEST_CONTROL 0x5c
+#define USB3_V5_5NM_PCS_USB3_RXTERMINATION_DLY_SEL 0x60
+
+/* Module: DP_QSERDES_PLL_DP_QSERDES_PLL_USB4_USB3_DP_QMP_PLL */
+#define DP_V5_5NM_QSERDES_PLL_ATB_SEL1 0x000
+#define DP_V5_5NM_QSERDES_PLL_ATB_SEL2 0x004
+#define DP_V5_5NM_QSERDES_PLL_FREQ_UPDATE 0x008
+#define DP_V5_5NM_QSERDES_PLL_BG_TIMER 0x00c
+#define DP_V5_5NM_QSERDES_PLL_SSC_EN_CENTER 0x010
+#define DP_V5_5NM_QSERDES_PLL_SSC_ADJ_PER1 0x014
+#define DP_V5_5NM_QSERDES_PLL_SSC_ADJ_PER2 0x018
+#define DP_V5_5NM_QSERDES_PLL_SSC_PER1 0x01c
+#define DP_V5_5NM_QSERDES_PLL_SSC_PER2 0x020
+#define DP_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024
+#define DP_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x028
+#define DP_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE3_MODE0 0x02c
+#define DP_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x030
+#define DP_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x034
+#define DP_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE3_MODE1 0x038
+#define DP_V5_5NM_QSERDES_PLL_POST_DIV 0x03c
+#define DP_V5_5NM_QSERDES_PLL_POST_DIV_MUX 0x040
+#define DP_V5_5NM_QSERDES_PLL_BIAS_EN_CLKBUFLR_EN 0x044
+#define DP_V5_5NM_QSERDES_PLL_CLK_ENABLE1 0x048
+#define DP_V5_5NM_QSERDES_PLL_SYS_CLK_CTRL 0x04c
+#define DP_V5_5NM_QSERDES_PLL_SYSCLK_BUF_ENABLE 0x050
+#define DP_V5_5NM_QSERDES_PLL_PLL_EN 0x054
+#define DP_V5_5NM_QSERDES_PLL_PLL_IVCO 0x058
+#define DP_V5_5NM_QSERDES_PLL_CMN_IETRIM 0x05c
+#define DP_V5_5NM_QSERDES_PLL_CMN_IPTRIM 0x060
+#define DP_V5_5NM_QSERDES_PLL_EP_CLOCK_DETECT_CTRL 0x064
+#define DP_V5_5NM_QSERDES_PLL_SYSCLK_DET_COMP_STATUS 0x068
+#define DP_V5_5NM_QSERDES_PLL_CLK_EP_DIV_MODE0 0x06c
+#define DP_V5_5NM_QSERDES_PLL_CLK_EP_DIV_MODE1 0x070
+#define DP_V5_5NM_QSERDES_PLL_CP_CTRL_MODE0 0x074
+#define DP_V5_5NM_QSERDES_PLL_CP_CTRL_MODE1 0x078
+#define DP_V5_5NM_QSERDES_PLL_PLL_RCTRL_MODE0 0x07c
+#define DP_V5_5NM_QSERDES_PLL_PLL_RCTRL_MODE1 0x080
+#define DP_V5_5NM_QSERDES_PLL_PLL_CCTRL_MODE0 0x084
+#define DP_V5_5NM_QSERDES_PLL_PLL_CCTRL_MODE1 0x088
+#define DP_V5_5NM_QSERDES_PLL_PLL_CNTRL 0x08c
+#define DP_V5_5NM_QSERDES_PLL_BIAS_EN_CTRL_BY_PSM 0x090
+#define DP_V5_5NM_QSERDES_PLL_SYSCLK_EN_SEL 0x094
+#define DP_V5_5NM_QSERDES_PLL_CML_SYSCLK_SEL 0x098
+#define DP_V5_5NM_QSERDES_PLL_RESETSM_CNTRL 0x09c
+#define DP_V5_5NM_QSERDES_PLL_RESETSM_CNTRL2 0x0a0
+#define DP_V5_5NM_QSERDES_PLL_LOCK_CMP_EN 0x0a4
+#define DP_V5_5NM_QSERDES_PLL_LOCK_CMP_CFG 0x0a8
+#define DP_V5_5NM_QSERDES_PLL_LOCK_CMP1_MODE0 0x0ac
+#define DP_V5_5NM_QSERDES_PLL_LOCK_CMP2_MODE0 0x0b0
+#define DP_V5_5NM_QSERDES_PLL_LOCK_CMP1_MODE1 0x0b4
+#define DP_V5_5NM_QSERDES_PLL_LOCK_CMP2_MODE1 0x0b8
+#define DP_V5_5NM_QSERDES_PLL_DEC_START_MODE0 0x0bc
+#define DP_V5_5NM_QSERDES_PLL_DEC_START_MSB_MODE0 0x0c0
+#define DP_V5_5NM_QSERDES_PLL_DEC_START_MODE1 0x0c4
+#define DP_V5_5NM_QSERDES_PLL_DEC_START_MSB_MODE1 0x0c8
+#define DP_V5_5NM_QSERDES_PLL_DIV_FRAC_START1_MODE0 0x0cc
+#define DP_V5_5NM_QSERDES_PLL_DIV_FRAC_START2_MODE0 0x0d0
+#define DP_V5_5NM_QSERDES_PLL_DIV_FRAC_START3_MODE0 0x0d4
+#define DP_V5_5NM_QSERDES_PLL_DIV_FRAC_START1_MODE1 0x0d8
+#define DP_V5_5NM_QSERDES_PLL_DIV_FRAC_START2_MODE1 0x0dc
+#define DP_V5_5NM_QSERDES_PLL_DIV_FRAC_START3_MODE1 0x0e0
+#define DP_V5_5NM_QSERDES_PLL_INTEGLOOP_INITVAL 0x0e4
+#define DP_V5_5NM_QSERDES_PLL_INTEGLOOP_EN 0x0e8
+#define DP_V5_5NM_QSERDES_PLL_INTEGLOOP_GAIN0_MODE0 0x0ec
+#define DP_V5_5NM_QSERDES_PLL_INTEGLOOP_GAIN1_MODE0 0x0f0
+#define DP_V5_5NM_QSERDES_PLL_INTEGLOOP_GAIN0_MODE1 0x0f4
+#define DP_V5_5NM_QSERDES_PLL_INTEGLOOP_GAIN1_MODE1 0x0f8
+#define DP_V5_5NM_QSERDES_PLL_INTEGLOOP_P_PATH_GAIN0 0x0fc
+#define DP_V5_5NM_QSERDES_PLL_INTEGLOOP_P_PATH_GAIN1 0x100
+#define DP_V5_5NM_QSERDES_PLL_VCOCAL_DEADMAN_CTRL 0x104
+#define DP_V5_5NM_QSERDES_PLL_VCO_TUNE_CTRL 0x108
+#define DP_V5_5NM_QSERDES_PLL_VCO_TUNE_MAP 0x10c
+#define DP_V5_5NM_QSERDES_PLL_VCO_TUNE1_MODE0 0x110
+#define DP_V5_5NM_QSERDES_PLL_VCO_TUNE2_MODE0 0x114
+#define DP_V5_5NM_QSERDES_PLL_VCO_TUNE1_MODE1 0x118
+#define DP_V5_5NM_QSERDES_PLL_VCO_TUNE2_MODE1 0x11c
+#define DP_V5_5NM_QSERDES_PLL_VCO_TUNE_INITVAL1 0x120
+#define DP_V5_5NM_QSERDES_PLL_VCO_TUNE_INITVAL2 0x124
+#define DP_V5_5NM_QSERDES_PLL_VCO_TUNE_MINVAL1 0x128
+#define DP_V5_5NM_QSERDES_PLL_VCO_TUNE_MINVAL2 0x12c
+#define DP_V5_5NM_QSERDES_PLL_VCO_TUNE_MAXVAL1 0x130
+#define DP_V5_5NM_QSERDES_PLL_VCO_TUNE_MAXVAL2 0x134
+#define DP_V5_5NM_QSERDES_PLL_VCO_TUNE_TIMER1 0x138
+#define DP_V5_5NM_QSERDES_PLL_VCO_TUNE_TIMER2 0x13c
+#define DP_V5_5NM_QSERDES_PLL_CMN_STATUS 0x140
+#define DP_V5_5NM_QSERDES_PLL_RESET_SM_STATUS 0x144
+#define DP_V5_5NM_QSERDES_PLL_RESTRIM_CODE_STATUS 0x148
+#define DP_V5_5NM_QSERDES_PLL_PLLCAL_CODE1_STATUS 0x14c
+#define DP_V5_5NM_QSERDES_PLL_PLLCAL_CODE2_STATUS 0x150
+#define DP_V5_5NM_QSERDES_PLL_CLK_SELECT 0x154
+#define DP_V5_5NM_QSERDES_PLL_HSCLK_SEL 0x158
+#define DP_V5_5NM_QSERDES_PLL_HSCLK_HS_SWITCH_SEL 0x15c
+#define DP_V5_5NM_QSERDES_PLL_INTEGLOOP_BINCODE_STATUS 0x160
+#define DP_V5_5NM_QSERDES_PLL_PLL_ANALOG 0x164
+#define DP_V5_5NM_QSERDES_PLL_CORECLK_DIV_MODE0 0x168
+#define DP_V5_5NM_QSERDES_PLL_CORECLK_DIV_MODE1 0x16c
+#define DP_V5_5NM_QSERDES_PLL_SW_RESET 0x170
+#define DP_V5_5NM_QSERDES_PLL_CORE_CLK_EN 0x174
+#define DP_V5_5NM_QSERDES_PLL_C_READY_STATUS 0x178
+#define DP_V5_5NM_QSERDES_PLL_CMN_CONFIG 0x17c
+#define DP_V5_5NM_QSERDES_PLL_CMN_RATE_OVERRIDE 0x180
+#define DP_V5_5NM_QSERDES_PLL_SVS_MODE_CLK_SEL 0x184
+#define DP_V5_5NM_QSERDES_PLL_DEBUG_BUS0 0x188
+#define DP_V5_5NM_QSERDES_PLL_DEBUG_BUS1 0x18c
+#define DP_V5_5NM_QSERDES_PLL_DEBUG_BUS2 0x190
+#define DP_V5_5NM_QSERDES_PLL_DEBUG_BUS3 0x194
+#define DP_V5_5NM_QSERDES_PLL_DEBUG_BUS_SEL 0x198
+#define DP_V5_5NM_QSERDES_PLL_CMN_MISC1 0x19c
+#define DP_V5_5NM_QSERDES_PLL_CMN_MODE 0x1a0
+#define DP_V5_5NM_QSERDES_PLL_CMN_MODE_CONTD 0x1a4
+#define DP_V5_5NM_QSERDES_PLL_VCO_DC_LEVEL_CTRL 0x1a8
+#define DP_V5_5NM_QSERDES_PLL_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac
+#define DP_V5_5NM_QSERDES_PLL_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0
+#define DP_V5_5NM_QSERDES_PLL_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4
+#define DP_V5_5NM_QSERDES_PLL_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8
+#define DP_V5_5NM_QSERDES_PLL_BIN_VCOCAL_HSCLK_SEL 0x1bc
+#define DP_V5_5NM_QSERDES_PLL_RESERVED_1 0x1c0
+#define DP_V5_5NM_QSERDES_PLL_MODE_OPERATION_STATUS 0x1c4
+
+/* Module: DP_DP_DP_PHY */
+#define DP_V5_5NM_DP_PHY_REVISION_ID0 0x000
+#define DP_V5_5NM_DP_PHY_REVISION_ID1 0x004
+#define DP_V5_5NM_DP_PHY_REVISION_ID2 0x008
+#define DP_V5_5NM_DP_PHY_REVISION_ID3 0x00c
+#define DP_V5_5NM_DP_PHY_CFG 0x010
+#define DP_V5_5NM_DP_PHY_CFG_1 0x014
+#define DP_V5_5NM_DP_PHY_PD_CTL 0x018
+#define DP_V5_5NM_DP_PHY_MODE 0x01c
+#define DP_V5_5NM_DP_PHY_AUX_CFG0 0x020
+#define DP_V5_5NM_DP_PHY_AUX_CFG1 0x024
+#define DP_V5_5NM_DP_PHY_AUX_CFG2 0x028
+#define DP_V5_5NM_DP_PHY_AUX_CFG3 0x02c
+#define DP_V5_5NM_DP_PHY_AUX_CFG4 0x030
+#define DP_V5_5NM_DP_PHY_AUX_CFG5 0x034
+#define DP_V5_5NM_DP_PHY_AUX_CFG6 0x038
+#define DP_V5_5NM_DP_PHY_AUX_CFG7 0x03c
+#define DP_V5_5NM_DP_PHY_AUX_CFG8 0x040
+#define DP_V5_5NM_DP_PHY_AUX_CFG9 0x044
+#define DP_V5_5NM_DP_PHY_AUX_CFG10 0x048
+#define DP_V5_5NM_DP_PHY_AUX_CFG11 0x04c
+#define DP_V5_5NM_DP_PHY_AUX_CFG12 0x050
+#define DP_V5_5NM_DP_PHY_AUX_INTERRUPT_MASK 0x054
+#define DP_V5_5NM_DP_PHY_AUX_INTERRUPT_CLEAR 0x058
+#define DP_V5_5NM_DP_PHY_AUX_BIST_CFG 0x05c
+#define DP_V5_5NM_DP_PHY_AUX_BIST_PRBS_SEED 0x060
+#define DP_V5_5NM_DP_PHY_AUX_BIST_PRBS_POLY 0x064
+#define DP_V5_5NM_DP_PHY_AUX_TX_PROG_PAT_16B_LSB 0x068
+#define DP_V5_5NM_DP_PHY_AUX_TX_PROG_PAT_16B_MSB 0x06c
+#define DP_V5_5NM_DP_PHY_VCO_DIV 0x070
+#define DP_V5_5NM_DP_PHY_TSYNC_OVRD 0x074
+#define DP_V5_5NM_DP_PHY_TX0_TX1_LANE_CTL 0x078
+#define DP_V5_5NM_DP_PHY_TX0_TX1_BIST_CFG0 0x07c
+#define DP_V5_5NM_DP_PHY_TX0_TX1_BIST_CFG1 0x080
+#define DP_V5_5NM_DP_PHY_TX0_TX1_BIST_CFG2 0x084
+#define DP_V5_5NM_DP_PHY_TX0_TX1_BIST_CFG3 0x088
+#define DP_V5_5NM_DP_PHY_TX0_TX1_PRBS_SEED_BYTE0 0x08c
+#define DP_V5_5NM_DP_PHY_TX0_TX1_PRBS_SEED_BYTE1 0x090
+#define DP_V5_5NM_DP_PHY_TX0_TX1_BIST_PATTERN0 0x094
+#define DP_V5_5NM_DP_PHY_TX0_TX1_BIST_PATTERN1 0x098
+#define DP_V5_5NM_DP_PHY_TX2_TX3_LANE_CTL 0x09c
+#define DP_V5_5NM_DP_PHY_TX2_TX3_BIST_CFG0 0x0a0
+#define DP_V5_5NM_DP_PHY_TX2_TX3_BIST_CFG1 0x0a4
+#define DP_V5_5NM_DP_PHY_TX2_TX3_BIST_CFG2 0x0a8
+#define DP_V5_5NM_DP_PHY_TX2_TX3_BIST_CFG3 0x0ac
+#define DP_V5_5NM_DP_PHY_TX2_TX3_PRBS_SEED_BYTE0 0x0b0
+#define DP_V5_5NM_DP_PHY_TX2_TX3_PRBS_SEED_BYTE1 0x0b4
+#define DP_V5_5NM_DP_PHY_TX2_TX3_BIST_PATTERN0 0x0b8
+#define DP_V5_5NM_DP_PHY_TX2_TX3_BIST_PATTERN1 0x0bc
+#define DP_V5_5NM_DP_PHY_MISR_CTRL 0x0c0
+#define DP_V5_5NM_DP_PHY_DEBUG_BUS_SEL 0x0c4
+#define DP_V5_5NM_DP_PHY_SPARE0 0x0c8
+#define DP_V5_5NM_DP_PHY_SPARE1 0x0cc
+#define DP_V5_5NM_DP_PHY_SPARE2 0x0d0
+#define DP_V5_5NM_DP_PHY_SPARE3 0x0d4
+#define DP_V5_5NM_DP_PHY_AUX_INTERRUPT_STATUS 0x0d8
+#define DP_V5_5NM_DP_PHY_STATUS 0x0dc
+#define DP_V5_5NM_DP_PHY_AUX_BIST_STATUS0 0x0e0
+#define DP_V5_5NM_DP_PHY_AUX_BIST_STATUS1 0x0e4
+#define DP_V5_5NM_DP_PHY_AUX_BIST_STATUS2 0x0e8
+#define DP_V5_5NM_DP_PHY_TX0_TX1_BIST_STATUS0 0x0ec
+#define DP_V5_5NM_DP_PHY_TX0_TX1_BIST_STATUS1 0x0f0
+#define DP_V5_5NM_DP_PHY_TX0_TX1_BIST_STATUS2 0x0f4
+#define DP_V5_5NM_DP_PHY_TX2_TX3_BIST_STATUS0 0x0f8
+#define DP_V5_5NM_DP_PHY_TX2_TX3_BIST_STATUS1 0x0fc
+#define DP_V5_5NM_DP_PHY_TX2_TX3_BIST_STATUS2 0x100
+#define DP_V5_5NM_DP_PHY_MISR_STATUS 0x104
+#define DP_V5_5NM_DP_PHY_TX0_MISR_STATUS000 0x108
+#define DP_V5_5NM_DP_PHY_TX0_MISR_STATUS001 0x10c
+#define DP_V5_5NM_DP_PHY_TX0_MISR_STATUS010 0x110
+#define DP_V5_5NM_DP_PHY_TX0_MISR_STATUS011 0x114
+#define DP_V5_5NM_DP_PHY_TX0_MISR_STATUS100 0x118
+#define DP_V5_5NM_DP_PHY_TX0_MISR_STATUS101 0x11c
+#define DP_V5_5NM_DP_PHY_TX0_MISR_STATUS110 0x120
+#define DP_V5_5NM_DP_PHY_TX0_MISR_STATUS111 0x124
+#define DP_V5_5NM_DP_PHY_TX1_MISR_STATUS000 0x128
+#define DP_V5_5NM_DP_PHY_TX1_MISR_STATUS001 0x12c
+#define DP_V5_5NM_DP_PHY_TX1_MISR_STATUS010 0x130
+#define DP_V5_5NM_DP_PHY_TX1_MISR_STATUS011 0x134
+#define DP_V5_5NM_DP_PHY_TX1_MISR_STATUS100 0x138
+#define DP_V5_5NM_DP_PHY_TX1_MISR_STATUS101 0x13c
+#define DP_V5_5NM_DP_PHY_TX1_MISR_STATUS110 0x140
+#define DP_V5_5NM_DP_PHY_TX1_MISR_STATUS111 0x144
+#define DP_V5_5NM_DP_PHY_TX2_MISR_STATUS000 0x148
+#define DP_V5_5NM_DP_PHY_TX2_MISR_STATUS001 0x14c
+#define DP_V5_5NM_DP_PHY_TX2_MISR_STATUS010 0x150
+#define DP_V5_5NM_DP_PHY_TX2_MISR_STATUS011 0x154
+#define DP_V5_5NM_DP_PHY_TX2_MISR_STATUS100 0x158
+#define DP_V5_5NM_DP_PHY_TX2_MISR_STATUS101 0x15c
+#define DP_V5_5NM_DP_PHY_TX2_MISR_STATUS110 0x160
+#define DP_V5_5NM_DP_PHY_TX2_MISR_STATUS111 0x164
+#define DP_V5_5NM_DP_PHY_TX3_MISR_STATUS000 0x168
+#define DP_V5_5NM_DP_PHY_TX3_MISR_STATUS001 0x16c
+#define DP_V5_5NM_DP_PHY_TX3_MISR_STATUS010 0x170
+#define DP_V5_5NM_DP_PHY_TX3_MISR_STATUS011 0x174
+#define DP_V5_5NM_DP_PHY_TX3_MISR_STATUS100 0x178
+#define DP_V5_5NM_DP_PHY_TX3_MISR_STATUS101 0x17c
+#define DP_V5_5NM_DP_PHY_TX3_MISR_STATUS110 0x180
+#define DP_V5_5NM_DP_PHY_TX3_MISR_STATUS111 0x184
+#define DP_V5_5NM_DP_PHY_DEBUG_BUS0 0x188
+#define DP_V5_5NM_DP_PHY_DEBUG_BUS1 0x18c
+#define DP_V5_5NM_DP_PHY_DEBUG_BUS2 0x190
+#define DP_V5_5NM_DP_PHY_DEBUG_BUS3 0x194
+
+/* Module: USB4_QSERDES_PLL_USB4_QSERDES_PLL_USB4_USB3_DP_QMP_PLL_20G */
+#define USB4_V5_5NM_QSERDES_PLL_ATB_SEL1 0x000
+#define USB4_V5_5NM_QSERDES_PLL_ATB_SEL2 0x004
+#define USB4_V5_5NM_QSERDES_PLL_FREQ_UPDATE 0x008
+#define USB4_V5_5NM_QSERDES_PLL_BG_TIMER 0x00c
+#define USB4_V5_5NM_QSERDES_PLL_SSC_EN_CENTER 0x010
+#define USB4_V5_5NM_QSERDES_PLL_SSC_ADJ_PER1 0x014
+#define USB4_V5_5NM_QSERDES_PLL_SSC_ADJ_PER2 0x018
+#define USB4_V5_5NM_QSERDES_PLL_SSC_PER1 0x01c
+#define USB4_V5_5NM_QSERDES_PLL_SSC_PER2 0x020
+#define USB4_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024
+#define USB4_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x028
+#define USB4_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE3_MODE0 0x02c
+#define USB4_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x030
+#define USB4_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x034
+#define USB4_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE3_MODE1 0x038
+#define USB4_V5_5NM_QSERDES_PLL_POST_DIV 0x03c
+#define USB4_V5_5NM_QSERDES_PLL_POST_DIV_MUX 0x040
+#define USB4_V5_5NM_QSERDES_PLL_BIAS_EN_CLKBUFLR_EN 0x044
+#define USB4_V5_5NM_QSERDES_PLL_CLK_ENABLE1 0x048
+#define USB4_V5_5NM_QSERDES_PLL_SYS_CLK_CTRL 0x04c
+#define USB4_V5_5NM_QSERDES_PLL_SYSCLK_BUF_ENABLE 0x050
+#define USB4_V5_5NM_QSERDES_PLL_PLL_EN 0x054
+#define USB4_V5_5NM_QSERDES_PLL_PLL_IVCO 0x058
+#define USB4_V5_5NM_QSERDES_PLL_CMN_IETRIM 0x05c
+#define USB4_V5_5NM_QSERDES_PLL_CMN_IPTRIM 0x060
+#define USB4_V5_5NM_QSERDES_PLL_EP_CLOCK_DETECT_CTRL 0x064
+#define USB4_V5_5NM_QSERDES_PLL_SYSCLK_DET_COMP_STATUS 0x068
+#define USB4_V5_5NM_QSERDES_PLL_CLK_EP_DIV_MODE0 0x06c
+#define USB4_V5_5NM_QSERDES_PLL_CLK_EP_DIV_MODE1 0x070
+#define USB4_V5_5NM_QSERDES_PLL_CP_CTRL_MODE0 0x074
+#define USB4_V5_5NM_QSERDES_PLL_CP_CTRL_MODE1 0x078
+#define USB4_V5_5NM_QSERDES_PLL_PLL_RCTRL_MODE0 0x07c
+#define USB4_V5_5NM_QSERDES_PLL_PLL_RCTRL_MODE1 0x080
+#define USB4_V5_5NM_QSERDES_PLL_PLL_CCTRL_MODE0 0x084
+#define USB4_V5_5NM_QSERDES_PLL_PLL_CCTRL_MODE1 0x088
+#define USB4_V5_5NM_QSERDES_PLL_PLL_CNTRL 0x08c
+#define USB4_V5_5NM_QSERDES_PLL_BIAS_EN_CTRL_BY_PSM 0x090
+#define USB4_V5_5NM_QSERDES_PLL_SYSCLK_EN_SEL 0x094
+#define USB4_V5_5NM_QSERDES_PLL_CML_SYSCLK_SEL 0x098
+#define USB4_V5_5NM_QSERDES_PLL_RESETSM_CNTRL 0x09c
+#define USB4_V5_5NM_QSERDES_PLL_RESETSM_CNTRL2 0x0a0
+#define USB4_V5_5NM_QSERDES_PLL_LOCK_CMP_EN 0x0a4
+#define USB4_V5_5NM_QSERDES_PLL_LOCK_CMP_CFG 0x0a8
+#define USB4_V5_5NM_QSERDES_PLL_LOCK_CMP1_MODE0 0x0ac
+#define USB4_V5_5NM_QSERDES_PLL_LOCK_CMP2_MODE0 0x0b0
+#define USB4_V5_5NM_QSERDES_PLL_LOCK_CMP1_MODE1 0x0b4
+#define USB4_V5_5NM_QSERDES_PLL_LOCK_CMP2_MODE1 0x0b8
+#define USB4_V5_5NM_QSERDES_PLL_DEC_START_MODE0 0x0bc
+#define USB4_V5_5NM_QSERDES_PLL_DEC_START_MSB_MODE0 0x0c0
+#define USB4_V5_5NM_QSERDES_PLL_DEC_START_MODE1 0x0c4
+#define USB4_V5_5NM_QSERDES_PLL_DEC_START_MSB_MODE1 0x0c8
+#define USB4_V5_5NM_QSERDES_PLL_DIV_FRAC_START1_MODE0 0x0cc
+#define USB4_V5_5NM_QSERDES_PLL_DIV_FRAC_START2_MODE0 0x0d0
+#define USB4_V5_5NM_QSERDES_PLL_DIV_FRAC_START3_MODE0 0x0d4
+#define USB4_V5_5NM_QSERDES_PLL_DIV_FRAC_START1_MODE1 0x0d8
+#define USB4_V5_5NM_QSERDES_PLL_DIV_FRAC_START2_MODE1 0x0dc
+#define USB4_V5_5NM_QSERDES_PLL_DIV_FRAC_START3_MODE1 0x0e0
+#define USB4_V5_5NM_QSERDES_PLL_INTEGLOOP_INITVAL 0x0e4
+#define USB4_V5_5NM_QSERDES_PLL_INTEGLOOP_EN 0x0e8
+#define USB4_V5_5NM_QSERDES_PLL_INTEGLOOP_GAIN0_MODE0 0x0ec
+#define USB4_V5_5NM_QSERDES_PLL_INTEGLOOP_GAIN1_MODE0 0x0f0
+#define USB4_V5_5NM_QSERDES_PLL_INTEGLOOP_GAIN0_MODE1 0x0f4
+#define USB4_V5_5NM_QSERDES_PLL_INTEGLOOP_GAIN1_MODE1 0x0f8
+#define USB4_V5_5NM_QSERDES_PLL_INTEGLOOP_P_PATH_GAIN0 0x0fc
+#define USB4_V5_5NM_QSERDES_PLL_INTEGLOOP_P_PATH_GAIN1 0x100
+#define USB4_V5_5NM_QSERDES_PLL_VCOCAL_DEADMAN_CTRL 0x104
+#define USB4_V5_5NM_QSERDES_PLL_VCO_TUNE_CTRL 0x108
+#define USB4_V5_5NM_QSERDES_PLL_VCO_TUNE_MAP 0x10c
+#define USB4_V5_5NM_QSERDES_PLL_VCO_TUNE1_MODE0 0x110
+#define USB4_V5_5NM_QSERDES_PLL_VCO_TUNE2_MODE0 0x114
+#define USB4_V5_5NM_QSERDES_PLL_VCO_TUNE1_MODE1 0x118
+#define USB4_V5_5NM_QSERDES_PLL_VCO_TUNE2_MODE1 0x11c
+#define USB4_V5_5NM_QSERDES_PLL_VCO_TUNE_INITVAL1 0x120
+#define USB4_V5_5NM_QSERDES_PLL_VCO_TUNE_INITVAL2 0x124
+#define USB4_V5_5NM_QSERDES_PLL_VCO_TUNE_MINVAL1 0x128
+#define USB4_V5_5NM_QSERDES_PLL_VCO_TUNE_MINVAL2 0x12c
+#define USB4_V5_5NM_QSERDES_PLL_VCO_TUNE_MAXVAL1 0x130
+#define USB4_V5_5NM_QSERDES_PLL_VCO_TUNE_MAXVAL2 0x134
+#define USB4_V5_5NM_QSERDES_PLL_VCO_TUNE_TIMER1 0x138
+#define USB4_V5_5NM_QSERDES_PLL_VCO_TUNE_TIMER2 0x13c
+#define USB4_V5_5NM_QSERDES_PLL_CMN_STATUS 0x140
+#define USB4_V5_5NM_QSERDES_PLL_RESET_SM_STATUS 0x144
+#define USB4_V5_5NM_QSERDES_PLL_RESTRIM_CODE_STATUS 0x148
+#define USB4_V5_5NM_QSERDES_PLL_PLLCAL_CODE1_STATUS 0x14c
+#define USB4_V5_5NM_QSERDES_PLL_PLLCAL_CODE2_STATUS 0x150
+#define USB4_V5_5NM_QSERDES_PLL_CLK_SELECT 0x154
+#define USB4_V5_5NM_QSERDES_PLL_HSCLK_SEL 0x158
+#define USB4_V5_5NM_QSERDES_PLL_HSCLK_HS_SWITCH_SEL 0x15c
+#define USB4_V5_5NM_QSERDES_PLL_INTEGLOOP_BINCODE_STATUS 0x160
+#define USB4_V5_5NM_QSERDES_PLL_PLL_ANALOG 0x164
+#define USB4_V5_5NM_QSERDES_PLL_CORECLK_DIV_MODE0 0x168
+#define USB4_V5_5NM_QSERDES_PLL_CORECLK_DIV_MODE1 0x16c
+#define USB4_V5_5NM_QSERDES_PLL_SW_RESET 0x170
+#define USB4_V5_5NM_QSERDES_PLL_CORE_CLK_EN 0x174
+#define USB4_V5_5NM_QSERDES_PLL_C_READY_STATUS 0x178
+#define USB4_V5_5NM_QSERDES_PLL_CMN_CONFIG 0x17c
+#define USB4_V5_5NM_QSERDES_PLL_CMN_RATE_OVERRIDE 0x180
+#define USB4_V5_5NM_QSERDES_PLL_SVS_MODE_CLK_SEL 0x184
+#define USB4_V5_5NM_QSERDES_PLL_DEBUG_BUS0 0x188
+#define USB4_V5_5NM_QSERDES_PLL_DEBUG_BUS1 0x18c
+#define USB4_V5_5NM_QSERDES_PLL_DEBUG_BUS2 0x190
+#define USB4_V5_5NM_QSERDES_PLL_DEBUG_BUS3 0x194
+#define USB4_V5_5NM_QSERDES_PLL_DEBUG_BUS_SEL 0x198
+#define USB4_V5_5NM_QSERDES_PLL_CMN_MISC1 0x19c
+#define USB4_V5_5NM_QSERDES_PLL_CMN_MODE 0x1a0
+#define USB4_V5_5NM_QSERDES_PLL_CMN_MODE_CONTD 0x1a4
+#define USB4_V5_5NM_QSERDES_PLL_VCO_DC_LEVEL_CTRL 0x1a8
+#define USB4_V5_5NM_QSERDES_PLL_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac
+#define USB4_V5_5NM_QSERDES_PLL_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0
+#define USB4_V5_5NM_QSERDES_PLL_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4
+#define USB4_V5_5NM_QSERDES_PLL_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8
+#define USB4_V5_5NM_QSERDES_PLL_BIN_VCOCAL_HSCLK_SEL 0x1bc
+#define USB4_V5_5NM_QSERDES_PLL_ADDITIONAL_CTRL_1 0x1c0
+#define USB4_V5_5NM_QSERDES_PLL_MODE_OPERATION_STATUS 0x1c4
+#define USB4_V5_5NM_QSERDES_PLL_AUTO_GAIN_ADJ_CTRL_1 0x1c8
+#define USB4_V5_5NM_QSERDES_PLL_AUTO_GAIN_ADJ_CTRL_2 0x1cc
+#define USB4_V5_5NM_QSERDES_PLL_AUTO_GAIN_ADJ_CTRL_3 0x1d0
+#define USB4_V5_5NM_QSERDES_PLL_AUTO_GAIN_ADJ_CTRL_4 0x1d4
+#define USB4_V5_5NM_QSERDES_PLL_ADDITIONAL_MISC 0x1d8
+#define USB4_V5_5NM_QSERDES_PLL_ADDITIONAL_MISC_2 0x1dc
+#define USB4_V5_5NM_QSERDES_PLL_ADDITIONAL_MISC_3 0x1e0
+
+/* Module: USB4_PCS_L0_USB4_PCS_L0_USB4_PCS_LANE */
+#define USB4_V5_5NM_PCS_L0_PCS_STATUS1 0x00
+#define USB4_V5_5NM_PCS_L0_PCS_STATUS2 0x04
+#define USB4_V5_5NM_PCS_L0_PCS_STATUS3 0x08
+#define USB4_V5_5NM_PCS_L0_BIST_CHK_ERR_CNT_L_STATUS 0x0c
+#define USB4_V5_5NM_PCS_L0_BIST_CHK_ERR_CNT_H_STATUS 0x10
+#define USB4_V5_5NM_PCS_L0_BIST_CHK_STATUS 0x14
+#define USB4_V5_5NM_PCS_L0_INSIG_SW_CTRL1 0x18
+#define USB4_V5_5NM_PCS_L0_INSIG_SW_CTRL2 0x1c
+#define USB4_V5_5NM_PCS_L0_INSIG_MX_CTRL1 0x20
+#define USB4_V5_5NM_PCS_L0_INSIG_MX_CTRL2 0x24
+#define USB4_V5_5NM_PCS_L0_OUTSIG_SW_CTRL1 0x28
+#define USB4_V5_5NM_PCS_L0_OUTSIG_SW_CTRL2 0x2c
+#define USB4_V5_5NM_PCS_L0_OUTSIG_MX_CTRL1 0x30
+#define USB4_V5_5NM_PCS_L0_OUTSIG_MX_CTRL2 0x34
+#define USB4_V5_5NM_PCS_L0_PRESET_OVERRIDE_CONFIG 0x38
+#define USB4_V5_5NM_PCS_L0_TEST_CONTROL1 0x3c
+#define USB4_V5_5NM_PCS_L0_TEST_CONTROL2 0x40
+#define USB4_V5_5NM_PCS_L0_TEST_CONTROL3 0x44
+#define USB4_V5_5NM_PCS_L0_BIST_CTRL 0x48
+#define USB4_V5_5NM_PCS_L0_PRBS_SEED0 0x4c
+#define USB4_V5_5NM_PCS_L0_PRBS_SEED1 0x50
+#define USB4_V5_5NM_PCS_L0_LANE_OFF_CONFIG 0x54
+#define USB4_V5_5NM_PCS_L0_RXEQ_STATUS1 0x58
+#define USB4_V5_5NM_PCS_L0_RXEQ_STATUS2 0x5c
+#define USB4_V5_5NM_PCS_L0_RX_MARGINING_CTRL1 0x60
+#define USB4_V5_5NM_PCS_L0_RX_MARGINING_STATUS1 0x64
+#define USB4_V5_5NM_PCS_L0_RX_MARGINING_STATUS2 0x68
+
+/* Module: USB4_PCS_L1_USB4_PCS_L1_USB4_PCS_LANE */
+#define USB4_V5_5NM_PCS_L1_PCS_STATUS1 0x00
+#define USB4_V5_5NM_PCS_L1_PCS_STATUS2 0x04
+#define USB4_V5_5NM_PCS_L1_PCS_STATUS3 0x08
+#define USB4_V5_5NM_PCS_L1_BIST_CHK_ERR_CNT_L_STATUS 0x0c
+#define USB4_V5_5NM_PCS_L1_BIST_CHK_ERR_CNT_H_STATUS 0x10
+#define USB4_V5_5NM_PCS_L1_BIST_CHK_STATUS 0x14
+#define USB4_V5_5NM_PCS_L1_INSIG_SW_CTRL1 0x18
+#define USB4_V5_5NM_PCS_L1_INSIG_SW_CTRL2 0x1c
+#define USB4_V5_5NM_PCS_L1_INSIG_MX_CTRL1 0x20
+#define USB4_V5_5NM_PCS_L1_INSIG_MX_CTRL2 0x24
+#define USB4_V5_5NM_PCS_L1_OUTSIG_SW_CTRL1 0x28
+#define USB4_V5_5NM_PCS_L1_OUTSIG_SW_CTRL2 0x2c
+#define USB4_V5_5NM_PCS_L1_OUTSIG_MX_CTRL1 0x30
+#define USB4_V5_5NM_PCS_L1_OUTSIG_MX_CTRL2 0x34
+#define USB4_V5_5NM_PCS_L1_PRESET_OVERRIDE_CONFIG 0x38
+#define USB4_V5_5NM_PCS_L1_TEST_CONTROL1 0x3c
+#define USB4_V5_5NM_PCS_L1_TEST_CONTROL2 0x40
+#define USB4_V5_5NM_PCS_L1_TEST_CONTROL3 0x44
+#define USB4_V5_5NM_PCS_L1_BIST_CTRL 0x48
+#define USB4_V5_5NM_PCS_L1_PRBS_SEED0 0x4c
+#define USB4_V5_5NM_PCS_L1_PRBS_SEED1 0x50
+#define USB4_V5_5NM_PCS_L1_LANE_OFF_CONFIG 0x54
+#define USB4_V5_5NM_PCS_L1_RXEQ_STATUS1 0x58
+#define USB4_V5_5NM_PCS_L1_RXEQ_STATUS2 0x5c
+#define USB4_V5_5NM_PCS_L1_RX_MARGINING_CTRL1 0x60
+#define USB4_V5_5NM_PCS_L1_RX_MARGINING_STATUS1 0x64
+#define USB4_V5_5NM_PCS_L1_RX_MARGINING_STATUS2 0x68
+
+/* Module: USB4_PCS_USB4_PCS_USB4_PCS */
+#define USB4_V5_5NM_PCS_SW_RESET 0x000
+#define USB4_V5_5NM_PCS_REVISION_ID0 0x004
+#define USB4_V5_5NM_PCS_REVISION_ID1 0x008
+#define USB4_V5_5NM_PCS_REVISION_ID2 0x00c
+#define USB4_V5_5NM_PCS_REVISION_ID3 0x010
+#define USB4_V5_5NM_PCS_PCS_STATUS1 0x014
+#define USB4_V5_5NM_PCS_PCS_STATUS2 0x018
+#define USB4_V5_5NM_PCS_PCS_STATUS3 0x01c
+#define USB4_V5_5NM_PCS_PCS_STATUS4 0x020
+#define USB4_V5_5NM_PCS_PCS_STATUS5 0x024
+#define USB4_V5_5NM_PCS_PCS_STATUS6 0x028
+#define USB4_V5_5NM_PCS_PCS_STATUS7 0x02c
+#define USB4_V5_5NM_PCS_DEBUG_BUS_0_STATUS 0x030
+#define USB4_V5_5NM_PCS_DEBUG_BUS_1_STATUS 0x034
+#define USB4_V5_5NM_PCS_DEBUG_BUS_2_STATUS 0x038
+#define USB4_V5_5NM_PCS_DEBUG_BUS_3_STATUS 0x03c
+#define USB4_V5_5NM_PCS_POWER_DOWN_CONTROL 0x040
+#define USB4_V5_5NM_PCS_START_CONTROL 0x044
+#define USB4_V5_5NM_PCS_INSIG_SW_CTRL1 0x048
+#define USB4_V5_5NM_PCS_INSIG_SW_CTRL2 0x04c
+#define USB4_V5_5NM_PCS_INSIG_SW_CTRL3 0x050
+#define USB4_V5_5NM_PCS_INSIG_SW_CTRL4 0x054
+#define USB4_V5_5NM_PCS_INSIG_SW_CTRL5 0x058
+#define USB4_V5_5NM_PCS_INSIG_SW_CTRL6 0x05c
+#define USB4_V5_5NM_PCS_INSIG_SW_CTRL7 0x060
+#define USB4_V5_5NM_PCS_INSIG_SW_CTRL8 0x064
+#define USB4_V5_5NM_PCS_INSIG_MX_CTRL1 0x068
+#define USB4_V5_5NM_PCS_INSIG_MX_CTRL2 0x06c
+#define USB4_V5_5NM_PCS_INSIG_MX_CTRL3 0x070
+#define USB4_V5_5NM_PCS_INSIG_MX_CTRL4 0x074
+#define USB4_V5_5NM_PCS_INSIG_MX_CTRL5 0x078
+#define USB4_V5_5NM_PCS_INSIG_MX_CTRL8 0x07c
+#define USB4_V5_5NM_PCS_OUTSIG_SW_CTRL1 0x080
+#define USB4_V5_5NM_PCS_OUTSIG_MX_CTRL1 0x084
+#define USB4_V5_5NM_PCS_OUTSIG_SW_CTRL2 0x088
+#define USB4_V5_5NM_PCS_OUTSIG_MX_CTRL2 0x08c
+#define USB4_V5_5NM_PCS_POWER_STATE_CONFIG1 0x090
+#define USB4_V5_5NM_PCS_POWER_STATE_CONFIG2 0x094
+#define USB4_V5_5NM_PCS_POWER_STATE_CONFIG3 0x098
+#define USB4_V5_5NM_PCS_POWER_STATE_CONFIG4 0x09c
+#define USB4_V5_5NM_PCS_FLL_CNTRL1 0x0a0
+#define USB4_V5_5NM_PCS_FLL_CNTRL2 0x0a4
+#define USB4_V5_5NM_PCS_FLL_CNT_VAL_L 0x0a8
+#define USB4_V5_5NM_PCS_FLL_CNT_VAL_H_TOL 0x0ac
+#define USB4_V5_5NM_PCS_FLL_MAN_CODE 0x0b0
+#define USB4_V5_5NM_PCS_TEST_CONTROL1 0x0b4
+#define USB4_V5_5NM_PCS_TEST_CONTROL2 0x0b8
+#define USB4_V5_5NM_PCS_TEST_CONTROL3 0x0bc
+#define USB4_V5_5NM_PCS_TEST_CONTROL4 0x0c0
+#define USB4_V5_5NM_PCS_TEST_CONTROL5 0x0c4
+#define USB4_V5_5NM_PCS_TEST_CONTROL6 0x0c8
+#define USB4_V5_5NM_PCS_TEST_CONTROL7 0x0cc
+#define USB4_V5_5NM_PCS_LOCK_DETECT_CONFIG1 0x0d0
+#define USB4_V5_5NM_PCS_LOCK_DETECT_CONFIG2 0x0d4
+#define USB4_V5_5NM_PCS_REFGEN_REQ_CONFIG1 0x0d8
+#define USB4_V5_5NM_PCS_REFGEN_REQ_CONFIG2 0x0dc
+#define USB4_V5_5NM_PCS_REFGEN_REQ_CONFIG3 0x0e0
+#define USB4_V5_5NM_PCS_BIST_CTRL 0x0e4
+#define USB4_V5_5NM_PCS_BIST_CONFIG1 0x0e8
+#define USB4_V5_5NM_PCS_BIST_CONFIG2 0x0ec
+#define USB4_V5_5NM_PCS_BIST_CONFIG3 0x0f0
+#define USB4_V5_5NM_PCS_TXMGN_CONFIG 0x0f4
+#define USB4_V5_5NM_PCS_G3_TXMGN_MAIN 0x0f8
+#define USB4_V5_5NM_PCS_G3_TXMGN_MAIN_RS 0x0fc
+#define USB4_V5_5NM_PCS_G3_PRE_GAIN 0x100
+#define USB4_V5_5NM_PCS_G3_POST_GAIN 0x104
+#define USB4_V5_5NM_PCS_G3_PRE_POST_OFFSET 0x108
+#define USB4_V5_5NM_PCS_G3_PRE_GAIN_RS 0x10c
+#define USB4_V5_5NM_PCS_G3_POST_GAIN_RS 0x110
+#define USB4_V5_5NM_PCS_G3_PRE_POST_OFFSET_RS 0x114
+#define USB4_V5_5NM_PCS_G2_TXMGN_MAIN 0x118
+#define USB4_V5_5NM_PCS_G2_TXMGN_MAIN_RS 0x11c
+#define USB4_V5_5NM_PCS_G2_PRE_GAIN 0x120
+#define USB4_V5_5NM_PCS_G2_POST_GAIN 0x124
+#define USB4_V5_5NM_PCS_G2_PRE_POST_OFFSET 0x128
+#define USB4_V5_5NM_PCS_G2_PRE_GAIN_RS 0x12c
+#define USB4_V5_5NM_PCS_G2_POST_GAIN_RS 0x130
+#define USB4_V5_5NM_PCS_G2_PRE_POST_OFFSET_RS 0x134
+#define USB4_V5_5NM_PCS_TXCOEFF_CONFIG 0x138
+#define USB4_V5_5NM_PCS_PRESET_P0_P1_PRE 0x13c
+#define USB4_V5_5NM_PCS_PRESET_P2_P3_PRE 0x140
+#define USB4_V5_5NM_PCS_PRESET_P4_P5_PRE 0x144
+#define USB4_V5_5NM_PCS_PRESET_P6_P7_PRE 0x148
+#define USB4_V5_5NM_PCS_PRESET_P8_P9_PRE 0x14c
+#define USB4_V5_5NM_PCS_PRESET_P10_P11_PRE 0x150
+#define USB4_V5_5NM_PCS_PRESET_P12_P13_PRE 0x154
+#define USB4_V5_5NM_PCS_PRESET_P14_P15_PRE 0x158
+#define USB4_V5_5NM_PCS_PRESET_P0_P1_POST 0x15c
+#define USB4_V5_5NM_PCS_PRESET_P2_P3_POST 0x160
+#define USB4_V5_5NM_PCS_PRESET_P4_P5_POST 0x164
+#define USB4_V5_5NM_PCS_PRESET_P6_P7_POST 0x168
+#define USB4_V5_5NM_PCS_PRESET_P8_P9_POST 0x16c
+#define USB4_V5_5NM_PCS_PRESET_P10_P11_POST 0x170
+#define USB4_V5_5NM_PCS_PRESET_P12_P13_POST 0x174
+#define USB4_V5_5NM_PCS_PRESET_P14_P15_POST 0x178
+#define USB4_V5_5NM_PCS_RX_SIGDET_LVL 0x17c
+#define USB4_V5_5NM_PCS_RX_SIGDET_DTCT_CNTRL 0x180
+#define USB4_V5_5NM_PCS_RATE_SLEW_CNTRL 0x184
+#define USB4_V5_5NM_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x188
+#define USB4_V5_5NM_PCS_C3_WAKEUP_DLY_TIME_AUXCLK_L 0x18c
+#define USB4_V5_5NM_PCS_C3_WAKEUP_DLY_TIME_AUXCLK_H 0x190
+#define USB4_V5_5NM_PCS_TSYNC_RSYNC_TIME 0x194
+#define USB4_V5_5NM_PCS_CDR_RESET_TIME 0x198
+#define USB4_V5_5NM_PCS_TSYNC_DLY_TIME 0x19c
+#define USB4_V5_5NM_PCS_ELECIDLE_DLY_SEL 0x1a0
+#define USB4_V5_5NM_PCS_CMN_ACK_OUT_SEL 0x1a4
+#define USB4_V5_5NM_PCS_PCS_TX_RX_CONFIG1 0x1a8
+#define USB4_V5_5NM_PCS_PCS_TX_RX_CONFIG2 0x1ac
+#define USB4_V5_5NM_PCS_PCS_TX_RX_CONFIG3 0x1b0
+#define USB4_V5_5NM_PCS_RX_DCC_CAL_CONFIG 0x1b4
+#define USB4_V5_5NM_PCS_EQ_CONFIG1 0x1b8
+#define USB4_V5_5NM_PCS_EQ_CONFIG2 0x1bc
+#define USB4_V5_5NM_PCS_G2_EQ_CONFIG1 0x1c0
+#define USB4_V5_5NM_PCS_G2_EQ_CONFIG2 0x1c4
+#define USB4_V5_5NM_PCS_G2_EQ_CONFIG3 0x1c8
+#define USB4_V5_5NM_PCS_G2_EQ_CONFIG4 0x1cc
+#define USB4_V5_5NM_PCS_G2_EQ_CONFIG5 0x1d0
+#define USB4_V5_5NM_PCS_G2_EQ_CONFIG6 0x1d4
+#define USB4_V5_5NM_PCS_G3_EQ_CONFIG1 0x1d8
+#define USB4_V5_5NM_PCS_G3_EQ_CONFIG2 0x1dc
+#define USB4_V5_5NM_PCS_G3_EQ_CONFIG3 0x1e0
+#define USB4_V5_5NM_PCS_G3_EQ_CONFIG4 0x1e4
+#define USB4_V5_5NM_PCS_G3_EQ_CONFIG5 0x1e8
+#define USB4_V5_5NM_PCS_G3_EQ_CONFIG6 0x1ec
+#define USB4_V5_5NM_PCS_FOM_EQ_CONFIG1 0x1f0
+#define USB4_V5_5NM_PCS_FOM_EQ_CONFIG2 0x1f4
+#define USB4_V5_5NM_PCS_FOM_EQ_CONFIG3 0x1f8
+#define USB4_V5_5NM_PCS_FOM_EQ_CONFIG4 0x1fc
+#define USB4_V5_5NM_PCS_LFPS_DET_HIGH_COUNT_VAL 0x200
+#define USB4_V5_5NM_PCS_LFPS_TX_ECSTART 0x204
+#define USB4_V5_5NM_PCS_LFPS_TX_END_CNT_C3_START 0x208
+#define USB4_V5_5NM_PCS_MBUS_CONFIG1 0x20c
+#define USB4_V5_5NM_PCS_MBUS_CTRL1 0x210
+#define USB4_V5_5NM_PCS_MBUS_CTRL2 0x214
+#define USB4_V5_5NM_PCS_MBUS_CTRL3 0x218
+#define USB4_V5_5NM_PCS_MBUS_CTRL4 0x21c
+#define USB4_V5_5NM_PCS_MBUS_STATUS1 0x220
+#define USB4_V5_5NM_PCS_RX_MARGINING_CONFIG1 0x224
+#define USB4_V5_5NM_PCS_RX_MARGINING_CONFIG2 0x228
+#define USB4_V5_5NM_PCS_RX_MARGINING_CONFIG3 0x22c
+#define USB4_V5_5NM_PCS_WAKEUP_CLK_CONFIG1 0x230
+#define USB4_V5_5NM_PCS_WAKEUP_CLK_CONFIG2 0x234
+#define USB4_V5_5NM_PCS_WAKEUP_CLK_STATUS 0x238
+#define USB4_V5_5NM_PCS_TX_LATENCY_MEAS_CONFIG1 0x23c
+#define USB4_V5_5NM_PCS_TX_LATENCY_MEAS_CONFIG2 0x240
+#define USB4_V5_5NM_PCS_TX_LATENCY_STATUS 0x244
+#define USB4_V5_5NM_PCS_SIGDET_CNTRL 0x248
+
+#endif
+
--
2.35.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v2 3/5] phy: qcom-qmp: Add USB4 5NM QMP combo PHY registers
2022-06-07 21:35 ` [PATCH v2 3/5] phy: qcom-qmp: Add USB4 5NM QMP combo PHY registers Bjorn Andersson
@ 2022-06-07 22:24 ` Dmitry Baryshkov
2022-06-07 23:04 ` Bjorn Andersson
0 siblings, 1 reply; 16+ messages in thread
From: Dmitry Baryshkov @ 2022-06-07 22:24 UTC (permalink / raw)
To: Bjorn Andersson, Kishon Vijay Abraham I, Vinod Koul, Manu Gautam
Cc: Rob Herring, Krzysztof Kozlowski, linux-arm-msm, linux-phy,
devicetree, linux-kernel
On 08/06/2022 00:35, Bjorn Andersson wrote:
> Add all registers defines from qcom,usb4-5nm-qmp-combo.h of the msm-5.4
> kernel. Offsets are adjusted to be relative to each sub-block, as we
> describe the individual pieces in the upstream kernel and "v5_5NM" are
> injected in the defines to not collide with existing constants.
>
> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---
>
> Changes since v1:
> - New patch
>
> .../qualcomm/phy-qcom-usb4-5nm-qmp-combo.h | 1547 +++++++++++++++++
> 1 file changed, 1547 insertions(+)
> create mode 100644 drivers/phy/qualcomm/phy-qcom-usb4-5nm-qmp-combo.h
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-usb4-5nm-qmp-combo.h b/drivers/phy/qualcomm/phy-qcom-usb4-5nm-qmp-combo.h
> new file mode 100644
> index 000000000000..7be8a50269ec
> --- /dev/null
> +++ b/drivers/phy/qualcomm/phy-qcom-usb4-5nm-qmp-combo.h
> @@ -0,0 +1,1547 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2021, The Linux Foundation. All rights reserved.
> + */
> +
> +#ifndef PHY_QCOM_V5_5NM_QMP_COMBO_USB4_H
> +#define PHY_QCOM_V5_5NM_QMP_COMBO_USB4_H
> +
> +/* USB4-USB3-DP Combo PHY register offsets */
> +/* Module: USB43DP_COM_USB43DP_COM_USB4_USB3_DP_COM */
> +#define USB43DP_V5_5NM_COM_PHY_MODE_CTRL 0x00
> +#define USB43DP_V5_5NM_COM_SW_RESET 0x04
> +#define USB43DP_V5_5NM_COM_POWER_DOWN_CTRL 0x08
> +#define USB43DP_V5_5NM_COM_SWI_CTRL 0x0c
> +#define USB43DP_V5_5NM_COM_TYPEC_CTRL 0x10
> +#define USB43DP_V5_5NM_COM_TYPEC_PWRDN_CTRL 0x14
> +#define USB43DP_V5_5NM_COM_DP_BIST_CFG_0 0x18
> +#define USB43DP_V5_5NM_COM_RESET_OVRD_CTRL1 0x1c
> +#define USB43DP_V5_5NM_COM_RESET_OVRD_CTRL2 0x20
> +#define USB43DP_V5_5NM_COM_DBG_CLK_MUX_CTRL 0x24
> +#define USB43DP_V5_5NM_COM_TYPEC_STATUS 0x28
> +#define USB43DP_V5_5NM_COM_PLACEHOLDER_STATUS 0x2c
> +#define USB43DP_V5_5NM_COM_REVISION_ID0 0x30
> +#define USB43DP_V5_5NM_COM_REVISION_ID1 0x34
> +#define USB43DP_V5_5NM_COM_REVISION_ID2 0x38
> +#define USB43DP_V5_5NM_COM_REVISION_ID3 0x3c
QPHY_V5_DP_COM_foo ?
> +
> +/* Module: USB43DP_DBGINT_USB43DP_DBGINT_USB3_PCS_DEBUG_INT */
> +#define USB43DP_V5_5NM_DBGINT_INTGEN_STATUS1 0x00
> +#define USB43DP_V5_5NM_DBGINT_INTGEN_STATUS2 0x04
> +#define USB43DP_V5_5NM_DBGINT_CONFIG1 0x08
> +#define USB43DP_V5_5NM_DBGINT_SIGNALBLK1_CONFIG1 0x0c
> +#define USB43DP_V5_5NM_DBGINT_SIGNALBLK1_CONFIG2 0x10
> +#define USB43DP_V5_5NM_DBGINT_SIGNALBLK1_CONFIG3 0x14
> +#define USB43DP_V5_5NM_DBGINT_SIGNALBLK1_CONFIG4 0x18
> +#define USB43DP_V5_5NM_DBGINT_SIGNALBLK1_CONFIG5 0x1c
> +#define USB43DP_V5_5NM_DBGINT_SIGNALBLK2_CONFIG1 0x20
> +#define USB43DP_V5_5NM_DBGINT_SIGNALBLK2_CONFIG2 0x24
> +#define USB43DP_V5_5NM_DBGINT_SIGNALBLK2_CONFIG3 0x28
> +#define USB43DP_V5_5NM_DBGINT_SIGNALBLK2_CONFIG4 0x2c
> +#define USB43DP_V5_5NM_DBGINT_SIGNALBLK2_CONFIG5 0x30
> +#define USB43DP_V5_5NM_DBGINT_STRINGBLK1_CONFIG1 0x34
> +#define USB43DP_V5_5NM_DBGINT_STRINGBLK1_CONFIG2 0x38
> +#define USB43DP_V5_5NM_DBGINT_STRINGBLK1_CONFIG3 0x3c
> +#define USB43DP_V5_5NM_DBGINT_STRINGBLK1_CONFIG4 0x40
> +#define USB43DP_V5_5NM_DBGINT_STRINGBLK1_CONFIG5 0x44
> +#define USB43DP_V5_5NM_DBGINT_STRINGBLK2_CONFIG1 0x48
> +#define USB43DP_V5_5NM_DBGINT_STRINGBLK2_CONFIG2 0x4c
> +#define USB43DP_V5_5NM_DBGINT_STRINGBLK2_CONFIG3 0x50
> +#define USB43DP_V5_5NM_DBGINT_STRINGBLK2_CONFIG4 0x54
> +#define USB43DP_V5_5NM_DBGINT_STRINGBLK2_CONFIG5 0x58
> +
> +/* Module: USB43DP_QSERDES_TXA_USB43DP_QSERDES_TXA_USB4_USB3_DP_QMP_TX */
> +#define USB43DP_V5_5NM_QSERDES_TXA_BIST_MODE_LANENO 0x00
> +#define USB43DP_V5_5NM_QSERDES_TXA_BIST_INVERT 0x04
> +#define USB43DP_V5_5NM_QSERDES_TXA_CLKBUF_ENABLE 0x08
> +#define USB43DP_V5_5NM_QSERDES_TXA_TX_EMP_POST1_LVL 0x0c
> +#define USB43DP_V5_5NM_QSERDES_TXA_TX_IDLE_LVL_LARGE_AMP 0x10
> +#define USB43DP_V5_5NM_QSERDES_TXA_TX_DRV_LVL 0x14
> +#define USB43DP_V5_5NM_QSERDES_TXA_TX_DRV_LVL_OFFSET 0x18
> +#define USB43DP_V5_5NM_QSERDES_TXA_RESET_TSYNC_EN 0x1c
> +#define USB43DP_V5_5NM_QSERDES_TXA_PRE_STALL_LDO_BOOST_EN 0x20
> +#define USB43DP_V5_5NM_QSERDES_TXA_LPB_EN 0x24
> +#define USB43DP_V5_5NM_QSERDES_TXA_RES_CODE_LANE_TX 0x28
> +#define USB43DP_V5_5NM_QSERDES_TXA_RES_CODE_LANE_RX 0x2c
> +#define USB43DP_V5_5NM_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x30
> +#define USB43DP_V5_5NM_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x34
> +#define USB43DP_V5_5NM_QSERDES_TXA_PERL_LENGTH1 0x38
> +#define USB43DP_V5_5NM_QSERDES_TXA_PERL_LENGTH2 0x3c
> +#define USB43DP_V5_5NM_QSERDES_TXA_SERDES_BYP_EN_OUT 0x40
> +#define USB43DP_V5_5NM_QSERDES_TXA_DEBUG_BUS_SEL 0x44
> +#define USB43DP_V5_5NM_QSERDES_TXA_TRANSCEIVER_BIAS_EN 0x48
> +#define USB43DP_V5_5NM_QSERDES_TXA_HIGHZ_DRVR_EN 0x4c
> +#define USB43DP_V5_5NM_QSERDES_TXA_TX_POL_INV 0x50
> +#define USB43DP_V5_5NM_QSERDES_TXA_PARRATE_REC_DETECT_IDLE_EN 0x54
> +#define USB43DP_V5_5NM_QSERDES_TXA_BIST_PATTERN1 0x58
> +#define USB43DP_V5_5NM_QSERDES_TXA_BIST_PATTERN2 0x5c
> +#define USB43DP_V5_5NM_QSERDES_TXA_BIST_PATTERN3 0x60
> +#define USB43DP_V5_5NM_QSERDES_TXA_BIST_PATTERN4 0x64
> +#define USB43DP_V5_5NM_QSERDES_TXA_BIST_PATTERN5 0x68
> +#define USB43DP_V5_5NM_QSERDES_TXA_BIST_PATTERN6 0x6c
> +#define USB43DP_V5_5NM_QSERDES_TXA_BIST_PATTERN7 0x70
> +#define USB43DP_V5_5NM_QSERDES_TXA_BIST_PATTERN8 0x74
> +#define USB43DP_V5_5NM_QSERDES_TXA_LANE_MODE_1 0x78
> +#define USB43DP_V5_5NM_QSERDES_TXA_LANE_MODE_2 0x7c
> +#define USB43DP_V5_5NM_QSERDES_TXA_LANE_MODE_3 0x80
> +#define USB43DP_V5_5NM_QSERDES_TXA_ATB_SEL1 0x84
> +#define USB43DP_V5_5NM_QSERDES_TXA_ATB_SEL2 0x88
> +#define USB43DP_V5_5NM_QSERDES_TXA_RCV_DETECT_LVL 0x8c
> +#define USB43DP_V5_5NM_QSERDES_TXA_RCV_DETECT_LVL_2 0x90
> +#define USB43DP_V5_5NM_QSERDES_TXA_PRBS_SEED1 0x94
> +#define USB43DP_V5_5NM_QSERDES_TXA_PRBS_SEED2 0x98
> +#define USB43DP_V5_5NM_QSERDES_TXA_PRBS_SEED3 0x9c
> +#define USB43DP_V5_5NM_QSERDES_TXA_PRBS_SEED4 0xa0
> +#define USB43DP_V5_5NM_QSERDES_TXA_RESET_GEN 0xa4
> +#define USB43DP_V5_5NM_QSERDES_TXA_RESET_GEN_MUXES 0xa8
> +#define USB43DP_V5_5NM_QSERDES_TXA_TRAN_DRVR_EMP_EN 0xac
> +#define USB43DP_V5_5NM_QSERDES_TXA_VMODE_CTRL1 0xb0
> +#define USB43DP_V5_5NM_QSERDES_TXA_ALOG_OBSV_BUS_CTRL_1 0xb4
> +#define USB43DP_V5_5NM_QSERDES_TXA_BIST_STATUS 0xb8
> +#define USB43DP_V5_5NM_QSERDES_TXA_BIST_ERROR_COUNT1 0xbc
> +#define USB43DP_V5_5NM_QSERDES_TXA_BIST_ERROR_COUNT2 0xc0
> +#define USB43DP_V5_5NM_QSERDES_TXA_ALOG_OBSV_BUS_STATUS_1 0xc4
> +#define USB43DP_V5_5NM_QSERDES_TXA_LANE_DIG_CONFIG 0xc8
> +#define USB43DP_V5_5NM_QSERDES_TXA_PI_QEC_CTRL 0xcc
> +#define USB43DP_V5_5NM_QSERDES_TXA_PRE_EMPH 0xd0
> +#define USB43DP_V5_5NM_QSERDES_TXA_SW_RESET 0xd4
> +#define USB43DP_V5_5NM_QSERDES_TXA_TX_BAND 0xd8
> +#define USB43DP_V5_5NM_QSERDES_TXA_SLEW_CNTL0 0xdc
> +#define USB43DP_V5_5NM_QSERDES_TXA_SLEW_CNTL1 0xe0
> +#define USB43DP_V5_5NM_QSERDES_TXA_INTERFACE_SELECT 0xe4
> +#define USB43DP_V5_5NM_QSERDES_TXA_DIG_BKUP_CTRL 0xe8
> +#define USB43DP_V5_5NM_QSERDES_TXA_DEBUG_BUS0 0xec
> +#define USB43DP_V5_5NM_QSERDES_TXA_DEBUG_BUS1 0xf0
> +#define USB43DP_V5_5NM_QSERDES_TXA_DEBUG_BUS2 0xf4
> +#define USB43DP_V5_5NM_QSERDES_TXA_DEBUG_BUS3 0xf8
> +#define USB43DP_V5_5NM_QSERDES_TXA_TX_BKUP_RO_BUS 0xfc
QSERDES_V5_20_TX_foo ? This looks compatible with the 4 registers that
we have in the header, but I can not verify the rest of registers
> +
> +/* Module: USB43DP_QSERDES_RXA_USB43DP_QSERDES_RXA_USB4_USB3_DP_QMP_RX */
> +#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN_RATE0 0x000
> +#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN_RATE1 0x004
> +#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN_RATE2 0x008
> +#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN_RATE3 0x00c
> +#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FASTLOCK_SO_GAIN_RATE0 0x010
> +#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FASTLOCK_SO_GAIN_RATE1 0x014
> +#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FASTLOCK_SO_GAIN_RATE2 0x018
> +#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FASTLOCK_SO_GAIN_RATE3 0x01c
> +#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SO_SATURATION 0x020
> +#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FO_TO_SO_DELAY 0x024
> +#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW_RATE0 0x028
> +#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH_RATE0 0x02c
> +#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW_RATE1 0x030
> +#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH_RATE1 0x034
> +#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW_RATE2 0x038
> +#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH_RATE2 0x03c
> +#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW_RATE3 0x040
> +#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH_RATE3 0x044
> +#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_PI_CTRL1 0x048
> +#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_PI_CTRL2 0x04c
> +#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SB2_THRESH1_RATE0 0x050
> +#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SB2_THRESH1_RATE1 0x054
> +#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SB2_THRESH1_RATE2 0x058
> +#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SB2_THRESH1_RATE3 0x05c
> +#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SB2_THRESH2_RATE0 0x060
> +#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SB2_THRESH2_RATE1 0x064
> +#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SB2_THRESH2_RATE2 0x068
> +#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SB2_THRESH2_RATE3 0x06c
> +#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SB2_GAIN1_RATE0 0x070
> +#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SB2_GAIN1_RATE1 0x074
> +#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SB2_GAIN1_RATE2 0x078
> +#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SB2_GAIN1_RATE3 0x07c
> +#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SB2_GAIN2_RATE0 0x080
> +#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SB2_GAIN2_RATE1 0x084
> +#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SB2_GAIN2_RATE2 0x088
> +#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SB2_GAIN2_RATE3 0x08c
> +#define USB43DP_V5_5NM_QSERDES_RXA_RXCLK_DIV2_CTRL 0x090
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_BAND 0x094
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_TERM_BW 0x098
> +#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FO_GAIN_RATE0 0x09c
> +#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FO_GAIN_RATE1 0x0a0
> +#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FO_GAIN_RATE2 0x0a4
> +#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FO_GAIN_RATE3 0x0a8
> +#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SO_GAIN_RATE0 0x0ac
> +#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SO_GAIN_RATE1 0x0b0
> +#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SO_GAIN_RATE2 0x0b4
> +#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SO_GAIN_RATE3 0x0b8
> +#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_PI_CONTROLS 0x0bc
> +#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_PD_DATA_FILTER_ENABLES 0x0c0
> +#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SO_ACC_DEFAULT_VAL_RATE0 0x0c4
> +#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SO_ACC_DEFAULT_VAL_RATE1 0x0c8
> +#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SO_ACC_DEFAULT_VAL_RATE2 0x0cc
> +#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SO_ACC_DEFAULT_VAL_RATE3 0x0d0
> +#define USB43DP_V5_5NM_QSERDES_RXA_AUX_CONTROL 0x0d4
> +#define USB43DP_V5_5NM_QSERDES_RXA_AUXDATA_TB 0x0d8
> +#define USB43DP_V5_5NM_QSERDES_RXA_RCLK_AUXDATA_SEL 0x0dc
> +#define USB43DP_V5_5NM_QSERDES_RXA_EOM_CTRL 0x0e0
> +#define USB43DP_V5_5NM_QSERDES_RXA_AC_JTAG_ENABLE 0x0e4
> +#define USB43DP_V5_5NM_QSERDES_RXA_AC_JTAG_INITP 0x0e8
> +#define USB43DP_V5_5NM_QSERDES_RXA_AC_JTAG_INITN 0x0ec
> +#define USB43DP_V5_5NM_QSERDES_RXA_AC_JTAG_LVL 0x0f0
> +#define USB43DP_V5_5NM_QSERDES_RXA_AC_JTAG_MODE 0x0f4
> +#define USB43DP_V5_5NM_QSERDES_RXA_AC_JTAG_RESET 0x0f8
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_RCVR_IQ_EN 0x0fc
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_Q_EN_RATES 0x100
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_IDAC_I0_DC_OFFSETS 0x104
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_IDAC_I0BAR_DC_OFFSETS 0x108
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_IDAC_I1_DC_OFFSETS 0x10c
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_IDAC_I1BAR_DC_OFFSETS 0x110
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_IDAC_Q_DC_OFFSETS 0x114
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_IDAC_QBAR_DC_OFFSETS 0x118
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_IDAC_A_DC_OFFSETS 0x11c
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_IDAC_ABAR_DC_OFFSETS 0x120
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_IDAC_EN 0x124
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_IDAC_ENABLES 0x128
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_IDAC_SIGN 0x12c
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_IVCM_CAL_CODE_OVERRIDE 0x130
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_IVCM_CAL_CTRL1 0x134
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_IVCM_CAL_CTRL2 0x138
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_IVCM_POSTCAL_OFFSET 0x13c
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_SUMMER_CAL_SPD_MODE 0x140
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_HIGHZ_PARRATE 0x144
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x148
> +#define USB43DP_V5_5NM_QSERDES_RXA_DFE_1 0x14c
> +#define USB43DP_V5_5NM_QSERDES_RXA_DFE_2 0x150
> +#define USB43DP_V5_5NM_QSERDES_RXA_DFE_3 0x154
> +#define USB43DP_V5_5NM_QSERDES_RXA_DFE_4 0x158
> +#define USB43DP_V5_5NM_QSERDES_RXA_DFE_TAP3_CTRL 0x15c
> +#define USB43DP_V5_5NM_QSERDES_RXA_DFE_TAP3_MANVAL_KTAP 0x160
> +#define USB43DP_V5_5NM_QSERDES_RXA_DFE_TAP4_CTRL 0x164
> +#define USB43DP_V5_5NM_QSERDES_RXA_DFE_TAP4_MANVAL_KTAP 0x168
> +#define USB43DP_V5_5NM_QSERDES_RXA_DFE_TAP5_CTRL 0x16c
> +#define USB43DP_V5_5NM_QSERDES_RXA_DFE_TAP5_MANVAL_KTAP 0x170
> +#define USB43DP_V5_5NM_QSERDES_RXA_TX_ADPT_CTRL 0x174
> +#define USB43DP_V5_5NM_QSERDES_RXA_DFE_DAC_ENABLE1 0x178
> +#define USB43DP_V5_5NM_QSERDES_RXA_DFE_DAC_ENABLE2 0x17c
> +#define USB43DP_V5_5NM_QSERDES_RXA_TX_ADAPT_PRE_THRESH1 0x180
> +#define USB43DP_V5_5NM_QSERDES_RXA_TX_ADAPT_PRE_THRESH2 0x184
> +#define USB43DP_V5_5NM_QSERDES_RXA_TX_ADAPT_POST_THRESH1 0x188
> +#define USB43DP_V5_5NM_QSERDES_RXA_TX_ADAPT_POST_THRESH2 0x18c
> +#define USB43DP_V5_5NM_QSERDES_RXA_TX_ADAPT_MAIN_THRESH1 0x190
> +#define USB43DP_V5_5NM_QSERDES_RXA_TX_ADAPT_MAIN_THRESH2 0x194
> +#define USB43DP_V5_5NM_QSERDES_RXA_VGA_CAL_CNTRL1 0x198
> +#define USB43DP_V5_5NM_QSERDES_RXA_VGA_CAL_CNTRL2 0x19c
> +#define USB43DP_V5_5NM_QSERDES_RXA_VGA_CAL_MAN_VAL 0x1a0
> +#define USB43DP_V5_5NM_QSERDES_RXA_VTHRESH_CAL_CNTRL1 0x1a4
> +#define USB43DP_V5_5NM_QSERDES_RXA_VTHRESH_CAL_CNTRL2 0x1a8
> +#define USB43DP_V5_5NM_QSERDES_RXA_VTHRESH_CAL_MAN_VAL_RATE0 0x1ac
> +#define USB43DP_V5_5NM_QSERDES_RXA_VTHRESH_CAL_MAN_VAL_RATE1 0x1b0
> +#define USB43DP_V5_5NM_QSERDES_RXA_VTHRESH_CAL_MAN_VAL_RATE2 0x1b4
> +#define USB43DP_V5_5NM_QSERDES_RXA_VTHRESH_CAL_MAN_VAL_RATE3 0x1b8
> +#define USB43DP_V5_5NM_QSERDES_RXA_GM_CAL 0x1bc
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_VGA_GAIN2_BLK1 0x1c0
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_VGA_GAIN2_BLK2 0x1c4
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x1c8
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x1cc
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x1d0
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0x1d4
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_EQ_OFFSET_LSB 0x1d8
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_EQ_OFFSET_MSB 0x1dc
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1e0
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_OFFSET_ADAPTOR_CNTRL2 0x1e4
> +#define USB43DP_V5_5NM_QSERDES_RXA_SIGDET_ENABLES 0x1e8
> +#define USB43DP_V5_5NM_QSERDES_RXA_SIGDET_CNTRL 0x1ec
> +#define USB43DP_V5_5NM_QSERDES_RXA_SIGDET_LVL 0x1f0
> +#define USB43DP_V5_5NM_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x1f4
> +#define USB43DP_V5_5NM_QSERDES_RXA_CDR_FREEZE_UP_DN 0x1f8
> +#define USB43DP_V5_5NM_QSERDES_RXA_CDR_RESET_OVERRIDE 0x1fc
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_INTERFACE_MODE 0x200
> +#define USB43DP_V5_5NM_QSERDES_RXA_JITTER_GEN_MODE 0x204
> +#define USB43DP_V5_5NM_QSERDES_RXA_SJ_AMP1 0x208
> +#define USB43DP_V5_5NM_QSERDES_RXA_SJ_AMP2 0x20c
> +#define USB43DP_V5_5NM_QSERDES_RXA_SJ_PER1 0x210
> +#define USB43DP_V5_5NM_QSERDES_RXA_SJ_PER2 0x214
> +#define USB43DP_V5_5NM_QSERDES_RXA_PPM_OFFSET1 0x218
> +#define USB43DP_V5_5NM_QSERDES_RXA_PPM_OFFSET2 0x21c
> +#define USB43DP_V5_5NM_QSERDES_RXA_SIGN_PPM_PERIOD1 0x220
> +#define USB43DP_V5_5NM_QSERDES_RXA_SIGN_PPM_PERIOD2 0x224
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE_0_1_B0 0x228
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE_0_1_B1 0x22c
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE_0_1_B2 0x230
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE_0_1_B3 0x234
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE_0_1_B4 0x238
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE_0_1_B5 0x23c
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE_0_1_B6 0x240
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE_0_1_B7 0x244
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE2_B0 0x248
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE2_B1 0x24c
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE2_B2 0x250
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE2_B3 0x254
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE2_B4 0x258
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE2_B5 0x25c
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE2_B6 0x260
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE2_B7 0x264
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE3_B0 0x268
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE3_B1 0x26c
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE3_B2 0x270
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE3_B3 0x274
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE3_B4 0x278
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE3_B5 0x27c
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE3_B6 0x280
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE3_B7 0x284
> +#define USB43DP_V5_5NM_QSERDES_RXA_PHPRE_CTRL 0x288
> +#define USB43DP_V5_5NM_QSERDES_RXA_PHPRE_INITVAL 0x28c
> +#define USB43DP_V5_5NM_QSERDES_RXA_DFE_EN_TIMER 0x290
> +#define USB43DP_V5_5NM_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x294
> +#define USB43DP_V5_5NM_QSERDES_RXA_DCC_CTRL1 0x298
> +#define USB43DP_V5_5NM_QSERDES_RXA_DCC_CTRL2 0x29c
> +#define USB43DP_V5_5NM_QSERDES_RXA_DCC_OFFSET 0x2a0
> +#define USB43DP_V5_5NM_QSERDES_RXA_DCC_CMUX_POSTCAL_OFFSET 0x2a4
> +#define USB43DP_V5_5NM_QSERDES_RXA_DCC_CMUX_CAL_CTRL1 0x2a8
> +#define USB43DP_V5_5NM_QSERDES_RXA_DCC_CMUX_CAL_CTRL2 0x2ac
> +#define USB43DP_V5_5NM_QSERDES_RXA_ALOG_OBSV_BUS_CTRL_1 0x2b0
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_CTRL1 0x2b4
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_CTRL2 0x2b8
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_CTRL3 0x2bc
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_CTRL_4 0x2c0
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_CFG_RATE_0_1 0x2c4
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_CFG_RATE_2_3 0x2c8
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_CTRL1 0x2cc
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_CTRL2 0x2d0
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_THRESH1_RATE210 0x2d4
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_THRESH1_RATE3 0x2d8
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_THRESH2_RATE210 0x2dc
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_THRESH2_RATE3 0x2e0
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_THRESH3_RATE210 0x2e4
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_THRESH3_RATE3 0x2e8
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_THRESH4_RATE210 0x2ec
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_THRESH4_RATE3 0x2f0
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_THRESH5_RATE210 0x2f4
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_THRESH5_RATE3 0x2f8
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_THRESH6_RATE210 0x2fc
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_THRESH6_RATE3 0x300
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_THRESH7_RATE210 0x304
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_THRESH7_RATE3 0x308
> +#define USB43DP_V5_5NM_QSERDES_RXA_Q_PI_INTRINSIC_BIAS_RATE10 0x30c
> +#define USB43DP_V5_5NM_QSERDES_RXA_Q_PI_INTRINSIC_BIAS_RATE32 0x310
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_VERTICAL_CTRL 0x314
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_VERTICAL_CODE 0x318
> +#define USB43DP_V5_5NM_QSERDES_RXA_RES_CODE_THRESH_HIGH_AND_BYP 0x31c
> +#define USB43DP_V5_5NM_QSERDES_RXA_RES_CODE_THRESH_LOW 0x320
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_BKUP_CTRL1 0x324
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_BKUP_CTRL2 0x328
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_BKUP_CTRL3 0x32c
> +#define USB43DP_V5_5NM_QSERDES_RXA_PI_CTRL1 0x330
> +#define USB43DP_V5_5NM_QSERDES_RXA_PI_CTRL2 0x334
> +#define USB43DP_V5_5NM_QSERDES_RXA_PI_QUAD 0x338
> +#define USB43DP_V5_5NM_QSERDES_RXA_QPI_CTRL1 0x33c
> +#define USB43DP_V5_5NM_QSERDES_RXA_QPI_CTRL2 0x340
> +#define USB43DP_V5_5NM_QSERDES_RXA_QPI_QUAD 0x344
> +#define USB43DP_V5_5NM_QSERDES_RXA_IDATA1 0x348
> +#define USB43DP_V5_5NM_QSERDES_RXA_IDATA2 0x34c
> +#define USB43DP_V5_5NM_QSERDES_RXA_IDATA3 0x350
> +#define USB43DP_V5_5NM_QSERDES_RXA_AC_JTAG_OUTP 0x354
> +#define USB43DP_V5_5NM_QSERDES_RXA_AC_JTAG_OUTN 0x358
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_SIGDET 0x35c
> +#define USB43DP_V5_5NM_QSERDES_RXA_ALOG_OBSV_BUS_STATUS_1 0x360
> +#define USB43DP_V5_5NM_QSERDES_RXA_READ_EQCODE 0x364
> +#define USB43DP_V5_5NM_QSERDES_RXA_READ_OFFSETCODE 0x368
> +#define USB43DP_V5_5NM_QSERDES_RXA_IA_ERROR_COUNTER_LOW 0x36c
> +#define USB43DP_V5_5NM_QSERDES_RXA_IA_ERROR_COUNTER_HIGH 0x370
> +#define USB43DP_V5_5NM_QSERDES_RXA_VGA_READ_CODE 0x374
> +#define USB43DP_V5_5NM_QSERDES_RXA_VTHRESH_READ_CODE 0x378
> +#define USB43DP_V5_5NM_QSERDES_RXA_DFE_TAP1_READ_CODE 0x37c
> +#define USB43DP_V5_5NM_QSERDES_RXA_DFE_TAP2_READ_CODE 0x380
> +#define USB43DP_V5_5NM_QSERDES_RXA_DFE_TAP3_READ_CODE 0x384
> +#define USB43DP_V5_5NM_QSERDES_RXA_DFE_TAP4_READ_CODE 0x388
> +#define USB43DP_V5_5NM_QSERDES_RXA_DFE_TAP5_READ_CODE 0x38c
> +#define USB43DP_V5_5NM_QSERDES_RXA_IDAC_STATUS_I0 0x390
> +#define USB43DP_V5_5NM_QSERDES_RXA_IDAC_STATUS_I0BAR 0x394
> +#define USB43DP_V5_5NM_QSERDES_RXA_IDAC_STATUS_I1 0x398
> +#define USB43DP_V5_5NM_QSERDES_RXA_IDAC_STATUS_I1BAR 0x39c
> +#define USB43DP_V5_5NM_QSERDES_RXA_IDAC_STATUS_Q 0x3a0
> +#define USB43DP_V5_5NM_QSERDES_RXA_IDAC_STATUS_QBAR 0x3a4
> +#define USB43DP_V5_5NM_QSERDES_RXA_IDAC_STATUS_A 0x3a8
> +#define USB43DP_V5_5NM_QSERDES_RXA_IDAC_STATUS_ABAR 0x3ac
> +#define USB43DP_V5_5NM_QSERDES_RXA_IDAC_STATUS_SM_ON 0x3b0
> +#define USB43DP_V5_5NM_QSERDES_RXA_IDAC_STATUS_SIGNERROR 0x3b4
> +#define USB43DP_V5_5NM_QSERDES_RXA_IVCM_CAL_STATUS 0x3b8
> +#define USB43DP_V5_5NM_QSERDES_RXA_IVCM_CAL_DEBUG_STATUS 0x3bc
> +#define USB43DP_V5_5NM_QSERDES_RXA_DCC_CAL_STATUS 0x3c0
> +#define USB43DP_V5_5NM_QSERDES_RXA_DCC_READ_CODE_STATUS 0x3c4
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_DEBUG1_STATUS 0x3c8
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_DEBUG2_STATUS 0x3cc
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_READ_CODE_STATUS 0x3d0
> +#define USB43DP_V5_5NM_QSERDES_RXA_EOM_ERR_CNT_LSB_STATUS 0x3d4
> +#define USB43DP_V5_5NM_QSERDES_RXA_EOM_ERR_CNT_MSB_STATUS 0x3d8
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_TUNE_STATUS 0x3dc
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_BKUP_READ_BUS1_STATUS 0x3e0
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_BKUP_READ_BUS2_STATUS 0x3e4
> +#define USB43DP_V5_5NM_QSERDES_RXA_RX_BKUP_READ_BUS3_STATUS 0x3e8
> +
> +/* Module: USB43DP_QSERDES_TXB_USB43DP_QSERDES_TXB_USB4_USB3_DP_QMP_TX */
> +#define USB43DP_V5_5NM_QSERDES_TXB_BIST_MODE_LANENO 0x00
> +#define USB43DP_V5_5NM_QSERDES_TXB_BIST_INVERT 0x04
> +#define USB43DP_V5_5NM_QSERDES_TXB_CLKBUF_ENABLE 0x08
> +#define USB43DP_V5_5NM_QSERDES_TXB_TX_EMP_POST1_LVL 0x0c
> +#define USB43DP_V5_5NM_QSERDES_TXB_TX_IDLE_LVL_LARGE_AMP 0x10
> +#define USB43DP_V5_5NM_QSERDES_TXB_TX_DRV_LVL 0x14
> +#define USB43DP_V5_5NM_QSERDES_TXB_TX_DRV_LVL_OFFSET 0x18
> +#define USB43DP_V5_5NM_QSERDES_TXB_RESET_TSYNC_EN 0x1c
> +#define USB43DP_V5_5NM_QSERDES_TXB_PRE_STALL_LDO_BOOST_EN 0x20
> +#define USB43DP_V5_5NM_QSERDES_TXB_LPB_EN 0x24
> +#define USB43DP_V5_5NM_QSERDES_TXB_RES_CODE_LANE_TX 0x28
> +#define USB43DP_V5_5NM_QSERDES_TXB_RES_CODE_LANE_RX 0x2c
> +#define USB43DP_V5_5NM_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x30
> +#define USB43DP_V5_5NM_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x34
> +#define USB43DP_V5_5NM_QSERDES_TXB_PERL_LENGTH1 0x38
> +#define USB43DP_V5_5NM_QSERDES_TXB_PERL_LENGTH2 0x3c
> +#define USB43DP_V5_5NM_QSERDES_TXB_SERDES_BYP_EN_OUT 0x40
> +#define USB43DP_V5_5NM_QSERDES_TXB_DEBUG_BUS_SEL 0x44
> +#define USB43DP_V5_5NM_QSERDES_TXB_TRANSCEIVER_BIAS_EN 0x48
> +#define USB43DP_V5_5NM_QSERDES_TXB_HIGHZ_DRVR_EN 0x4c
> +#define USB43DP_V5_5NM_QSERDES_TXB_TX_POL_INV 0x50
> +#define USB43DP_V5_5NM_QSERDES_TXB_PARRATE_REC_DETECT_IDLE_EN 0x54
> +#define USB43DP_V5_5NM_QSERDES_TXB_BIST_PATTERN1 0x58
> +#define USB43DP_V5_5NM_QSERDES_TXB_BIST_PATTERN2 0x5c
> +#define USB43DP_V5_5NM_QSERDES_TXB_BIST_PATTERN3 0x60
> +#define USB43DP_V5_5NM_QSERDES_TXB_BIST_PATTERN4 0x64
> +#define USB43DP_V5_5NM_QSERDES_TXB_BIST_PATTERN5 0x68
> +#define USB43DP_V5_5NM_QSERDES_TXB_BIST_PATTERN6 0x6c
> +#define USB43DP_V5_5NM_QSERDES_TXB_BIST_PATTERN7 0x70
> +#define USB43DP_V5_5NM_QSERDES_TXB_BIST_PATTERN8 0x74
> +#define USB43DP_V5_5NM_QSERDES_TXB_LANE_MODE_1 0x78
> +#define USB43DP_V5_5NM_QSERDES_TXB_LANE_MODE_2 0x7c
> +#define USB43DP_V5_5NM_QSERDES_TXB_LANE_MODE_3 0x80
> +#define USB43DP_V5_5NM_QSERDES_TXB_ATB_SEL1 0x84
> +#define USB43DP_V5_5NM_QSERDES_TXB_ATB_SEL2 0x88
> +#define USB43DP_V5_5NM_QSERDES_TXB_RCV_DETECT_LVL 0x8c
> +#define USB43DP_V5_5NM_QSERDES_TXB_RCV_DETECT_LVL_2 0x90
> +#define USB43DP_V5_5NM_QSERDES_TXB_PRBS_SEED1 0x94
> +#define USB43DP_V5_5NM_QSERDES_TXB_PRBS_SEED2 0x98
> +#define USB43DP_V5_5NM_QSERDES_TXB_PRBS_SEED3 0x9c
> +#define USB43DP_V5_5NM_QSERDES_TXB_PRBS_SEED4 0xa0
> +#define USB43DP_V5_5NM_QSERDES_TXB_RESET_GEN 0xa4
> +#define USB43DP_V5_5NM_QSERDES_TXB_RESET_GEN_MUXES 0xa8
> +#define USB43DP_V5_5NM_QSERDES_TXB_TRAN_DRVR_EMP_EN 0xac
> +#define USB43DP_V5_5NM_QSERDES_TXB_VMODE_CTRL1 0xb0
> +#define USB43DP_V5_5NM_QSERDES_TXB_ALOG_OBSV_BUS_CTRL_1 0xb4
> +#define USB43DP_V5_5NM_QSERDES_TXB_BIST_STATUS 0xb8
> +#define USB43DP_V5_5NM_QSERDES_TXB_BIST_ERROR_COUNT1 0xbc
> +#define USB43DP_V5_5NM_QSERDES_TXB_BIST_ERROR_COUNT2 0xc0
> +#define USB43DP_V5_5NM_QSERDES_TXB_ALOG_OBSV_BUS_STATUS_1 0xc4
> +#define USB43DP_V5_5NM_QSERDES_TXB_LANE_DIG_CONFIG 0xc8
> +#define USB43DP_V5_5NM_QSERDES_TXB_PI_QEC_CTRL 0xcc
> +#define USB43DP_V5_5NM_QSERDES_TXB_PRE_EMPH 0xd0
> +#define USB43DP_V5_5NM_QSERDES_TXB_SW_RESET 0xd4
> +#define USB43DP_V5_5NM_QSERDES_TXB_TX_BAND 0xd8
> +#define USB43DP_V5_5NM_QSERDES_TXB_SLEW_CNTL0 0xdc
> +#define USB43DP_V5_5NM_QSERDES_TXB_SLEW_CNTL1 0xe0
> +#define USB43DP_V5_5NM_QSERDES_TXB_INTERFACE_SELECT 0xe4
> +#define USB43DP_V5_5NM_QSERDES_TXB_DIG_BKUP_CTRL 0xe8
> +#define USB43DP_V5_5NM_QSERDES_TXB_DEBUG_BUS0 0xec
> +#define USB43DP_V5_5NM_QSERDES_TXB_DEBUG_BUS1 0xf0
> +#define USB43DP_V5_5NM_QSERDES_TXB_DEBUG_BUS2 0xf4
> +#define USB43DP_V5_5NM_QSERDES_TXB_DEBUG_BUS3 0xf8
> +#define USB43DP_V5_5NM_QSERDES_TXB_TX_BKUP_RO_BUS 0xfc
What is the difference between _TXA_ and _TXB_ ?
> +
> +/* Module: USB43DP_QSERDES_RXB_USB43DP_QSERDES_RXB_USB4_USB3_DP_QMP_RX */
> +#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN_RATE0 0x000
> +#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN_RATE1 0x004
> +#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN_RATE2 0x008
> +#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN_RATE3 0x00c
> +#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FASTLOCK_SO_GAIN_RATE0 0x010
> +#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FASTLOCK_SO_GAIN_RATE1 0x014
> +#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FASTLOCK_SO_GAIN_RATE2 0x018
> +#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FASTLOCK_SO_GAIN_RATE3 0x01c
> +#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SO_SATURATION 0x020
> +#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FO_TO_SO_DELAY 0x024
> +#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW_RATE0 0x028
> +#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH_RATE0 0x02c
> +#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW_RATE1 0x030
> +#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH_RATE1 0x034
> +#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW_RATE2 0x038
> +#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH_RATE2 0x03c
> +#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW_RATE3 0x040
> +#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH_RATE3 0x044
> +#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_PI_CTRL1 0x048
> +#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_PI_CTRL2 0x04c
> +#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SB2_THRESH1_RATE0 0x050
> +#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SB2_THRESH1_RATE1 0x054
> +#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SB2_THRESH1_RATE2 0x058
> +#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SB2_THRESH1_RATE3 0x05c
> +#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SB2_THRESH2_RATE0 0x060
> +#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SB2_THRESH2_RATE1 0x064
> +#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SB2_THRESH2_RATE2 0x068
> +#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SB2_THRESH2_RATE3 0x06c
> +#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SB2_GAIN1_RATE0 0x070
> +#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SB2_GAIN1_RATE1 0x074
> +#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SB2_GAIN1_RATE2 0x078
> +#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SB2_GAIN1_RATE3 0x07c
> +#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SB2_GAIN2_RATE0 0x080
> +#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SB2_GAIN2_RATE1 0x084
> +#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SB2_GAIN2_RATE2 0x088
> +#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SB2_GAIN2_RATE3 0x08c
> +#define USB43DP_V5_5NM_QSERDES_RXB_RXCLK_DIV2_CTRL 0x090
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_BAND 0x094
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_TERM_BW 0x098
> +#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FO_GAIN_RATE0 0x09c
> +#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FO_GAIN_RATE1 0x0a0
> +#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FO_GAIN_RATE2 0x0a4
> +#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FO_GAIN_RATE3 0x0a8
> +#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SO_GAIN_RATE0 0x0ac
> +#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SO_GAIN_RATE1 0x0b0
> +#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SO_GAIN_RATE2 0x0b4
> +#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SO_GAIN_RATE3 0x0b8
> +#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_PI_CONTROLS 0x0bc
> +#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_PD_DATA_FILTER_ENABLES 0x0c0
> +#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SO_ACC_DEFAULT_VAL_RATE0 0x0c4
> +#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SO_ACC_DEFAULT_VAL_RATE1 0x0c8
> +#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SO_ACC_DEFAULT_VAL_RATE2 0x0cc
> +#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SO_ACC_DEFAULT_VAL_RATE3 0x0d0
> +#define USB43DP_V5_5NM_QSERDES_RXB_AUX_CONTROL 0x0d4
> +#define USB43DP_V5_5NM_QSERDES_RXB_AUXDATA_TB 0x0d8
> +#define USB43DP_V5_5NM_QSERDES_RXB_RCLK_AUXDATA_SEL 0x0dc
> +#define USB43DP_V5_5NM_QSERDES_RXB_EOM_CTRL 0x0e0
> +#define USB43DP_V5_5NM_QSERDES_RXB_AC_JTAG_ENABLE 0x0e4
> +#define USB43DP_V5_5NM_QSERDES_RXB_AC_JTAG_INITP 0x0e8
> +#define USB43DP_V5_5NM_QSERDES_RXB_AC_JTAG_INITN 0x0ec
> +#define USB43DP_V5_5NM_QSERDES_RXB_AC_JTAG_LVL 0x0f0
> +#define USB43DP_V5_5NM_QSERDES_RXB_AC_JTAG_MODE 0x0f4
> +#define USB43DP_V5_5NM_QSERDES_RXB_AC_JTAG_RESET 0x0f8
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_RCVR_IQ_EN 0x0fc
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_Q_EN_RATES 0x100
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_IDAC_I0_DC_OFFSETS 0x104
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_IDAC_I0BAR_DC_OFFSETS 0x108
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_IDAC_I1_DC_OFFSETS 0x10c
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_IDAC_I1BAR_DC_OFFSETS 0x110
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_IDAC_Q_DC_OFFSETS 0x114
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_IDAC_QBAR_DC_OFFSETS 0x118
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_IDAC_A_DC_OFFSETS 0x11c
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_IDAC_ABAR_DC_OFFSETS 0x120
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_IDAC_EN 0x124
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_IDAC_ENABLES 0x128
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_IDAC_SIGN 0x12c
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_IVCM_CAL_CODE_OVERRIDE 0x130
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_IVCM_CAL_CTRL1 0x134
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_IVCM_CAL_CTRL2 0x138
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_IVCM_POSTCAL_OFFSET 0x13c
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_SUMMER_CAL_SPD_MODE 0x140
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_HIGHZ_PARRATE 0x144
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x148
> +#define USB43DP_V5_5NM_QSERDES_RXB_DFE_1 0x14c
> +#define USB43DP_V5_5NM_QSERDES_RXB_DFE_2 0x150
> +#define USB43DP_V5_5NM_QSERDES_RXB_DFE_3 0x154
> +#define USB43DP_V5_5NM_QSERDES_RXB_DFE_4 0x158
> +#define USB43DP_V5_5NM_QSERDES_RXB_DFE_TAP3_CTRL 0x15c
> +#define USB43DP_V5_5NM_QSERDES_RXB_DFE_TAP3_MANVAL_KTAP 0x160
> +#define USB43DP_V5_5NM_QSERDES_RXB_DFE_TAP4_CTRL 0x164
> +#define USB43DP_V5_5NM_QSERDES_RXB_DFE_TAP4_MANVAL_KTAP 0x168
> +#define USB43DP_V5_5NM_QSERDES_RXB_DFE_TAP5_CTRL 0x16c
> +#define USB43DP_V5_5NM_QSERDES_RXB_DFE_TAP5_MANVAL_KTAP 0x170
> +#define USB43DP_V5_5NM_QSERDES_RXB_TX_ADPT_CTRL 0x174
> +#define USB43DP_V5_5NM_QSERDES_RXB_DFE_DAC_ENABLE1 0x178
> +#define USB43DP_V5_5NM_QSERDES_RXB_DFE_DAC_ENABLE2 0x17c
> +#define USB43DP_V5_5NM_QSERDES_RXB_TX_ADAPT_PRE_THRESH1 0x180
> +#define USB43DP_V5_5NM_QSERDES_RXB_TX_ADAPT_PRE_THRESH2 0x184
> +#define USB43DP_V5_5NM_QSERDES_RXB_TX_ADAPT_POST_THRESH1 0x188
> +#define USB43DP_V5_5NM_QSERDES_RXB_TX_ADAPT_POST_THRESH2 0x18c
> +#define USB43DP_V5_5NM_QSERDES_RXB_TX_ADAPT_MAIN_THRESH1 0x190
> +#define USB43DP_V5_5NM_QSERDES_RXB_TX_ADAPT_MAIN_THRESH2 0x194
> +#define USB43DP_V5_5NM_QSERDES_RXB_VGA_CAL_CNTRL1 0x198
> +#define USB43DP_V5_5NM_QSERDES_RXB_VGA_CAL_CNTRL2 0x19c
> +#define USB43DP_V5_5NM_QSERDES_RXB_VGA_CAL_MAN_VAL 0x1a0
> +#define USB43DP_V5_5NM_QSERDES_RXB_VTHRESH_CAL_CNTRL1 0x1a4
> +#define USB43DP_V5_5NM_QSERDES_RXB_VTHRESH_CAL_CNTRL2 0x1a8
> +#define USB43DP_V5_5NM_QSERDES_RXB_VTHRESH_CAL_MAN_VAL_RATE0 0x1ac
> +#define USB43DP_V5_5NM_QSERDES_RXB_VTHRESH_CAL_MAN_VAL_RATE1 0x1b0
> +#define USB43DP_V5_5NM_QSERDES_RXB_VTHRESH_CAL_MAN_VAL_RATE2 0x1b4
> +#define USB43DP_V5_5NM_QSERDES_RXB_VTHRESH_CAL_MAN_VAL_RATE3 0x1b8
> +#define USB43DP_V5_5NM_QSERDES_RXB_GM_CAL 0x1bc
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_VGA_GAIN2_BLK1 0x1c0
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_VGA_GAIN2_BLK2 0x1c4
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x1c8
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x1cc
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x1d0
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0x1d4
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_EQ_OFFSET_LSB 0x1d8
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_EQ_OFFSET_MSB 0x1dc
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1e0
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_OFFSET_ADAPTOR_CNTRL2 0x1e4
> +#define USB43DP_V5_5NM_QSERDES_RXB_SIGDET_ENABLES 0x1e8
> +#define USB43DP_V5_5NM_QSERDES_RXB_SIGDET_CNTRL 0x1ec
> +#define USB43DP_V5_5NM_QSERDES_RXB_SIGDET_LVL 0x1f0
> +#define USB43DP_V5_5NM_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x1f4
> +#define USB43DP_V5_5NM_QSERDES_RXB_CDR_FREEZE_UP_DN 0x1f8
> +#define USB43DP_V5_5NM_QSERDES_RXB_CDR_RESET_OVERRIDE 0x1fc
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_INTERFACE_MODE 0x200
> +#define USB43DP_V5_5NM_QSERDES_RXB_JITTER_GEN_MODE 0x204
> +#define USB43DP_V5_5NM_QSERDES_RXB_SJ_AMP1 0x208
> +#define USB43DP_V5_5NM_QSERDES_RXB_SJ_AMP2 0x20c
> +#define USB43DP_V5_5NM_QSERDES_RXB_SJ_PER1 0x210
> +#define USB43DP_V5_5NM_QSERDES_RXB_SJ_PER2 0x214
> +#define USB43DP_V5_5NM_QSERDES_RXB_PPM_OFFSET1 0x218
> +#define USB43DP_V5_5NM_QSERDES_RXB_PPM_OFFSET2 0x21c
> +#define USB43DP_V5_5NM_QSERDES_RXB_SIGN_PPM_PERIOD1 0x220
> +#define USB43DP_V5_5NM_QSERDES_RXB_SIGN_PPM_PERIOD2 0x224
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE_0_1_B0 0x228
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE_0_1_B1 0x22c
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE_0_1_B2 0x230
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE_0_1_B3 0x234
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE_0_1_B4 0x238
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE_0_1_B5 0x23c
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE_0_1_B6 0x240
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE_0_1_B7 0x244
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE2_B0 0x248
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE2_B1 0x24c
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE2_B2 0x250
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE2_B3 0x254
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE2_B4 0x258
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE2_B5 0x25c
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE2_B6 0x260
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE2_B7 0x264
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE3_B0 0x268
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE3_B1 0x26c
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE3_B2 0x270
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE3_B3 0x274
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE3_B4 0x278
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE3_B5 0x27c
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE3_B6 0x280
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE3_B7 0x284
> +#define USB43DP_V5_5NM_QSERDES_RXB_PHPRE_CTRL 0x288
> +#define USB43DP_V5_5NM_QSERDES_RXB_PHPRE_INITVAL 0x28c
> +#define USB43DP_V5_5NM_QSERDES_RXB_DFE_EN_TIMER 0x290
> +#define USB43DP_V5_5NM_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x294
> +#define USB43DP_V5_5NM_QSERDES_RXB_DCC_CTRL1 0x298
> +#define USB43DP_V5_5NM_QSERDES_RXB_DCC_CTRL2 0x29c
> +#define USB43DP_V5_5NM_QSERDES_RXB_DCC_OFFSET 0x2a0
> +#define USB43DP_V5_5NM_QSERDES_RXB_DCC_CMUX_POSTCAL_OFFSET 0x2a4
> +#define USB43DP_V5_5NM_QSERDES_RXB_DCC_CMUX_CAL_CTRL1 0x2a8
> +#define USB43DP_V5_5NM_QSERDES_RXB_DCC_CMUX_CAL_CTRL2 0x2ac
> +#define USB43DP_V5_5NM_QSERDES_RXB_ALOG_OBSV_BUS_CTRL_1 0x2b0
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_CTRL1 0x2b4
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_CTRL2 0x2b8
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_CTRL3 0x2bc
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_CTRL_4 0x2c0
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_CFG_RATE_0_1 0x2c4
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_CFG_RATE_2_3 0x2c8
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_CTRL1 0x2cc
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_CTRL2 0x2d0
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_THRESH1_RATE210 0x2d4
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_THRESH1_RATE3 0x2d8
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_THRESH2_RATE210 0x2dc
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_THRESH2_RATE3 0x2e0
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_THRESH3_RATE210 0x2e4
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_THRESH3_RATE3 0x2e8
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_THRESH4_RATE210 0x2ec
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_THRESH4_RATE3 0x2f0
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_THRESH5_RATE210 0x2f4
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_THRESH5_RATE3 0x2f8
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_THRESH6_RATE210 0x2fc
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_THRESH6_RATE3 0x300
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_THRESH7_RATE210 0x304
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_THRESH7_RATE3 0x308
> +#define USB43DP_V5_5NM_QSERDES_RXB_Q_PI_INTRINSIC_BIAS_RATE10 0x30c
> +#define USB43DP_V5_5NM_QSERDES_RXB_Q_PI_INTRINSIC_BIAS_RATE32 0x310
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_VERTICAL_CTRL 0x314
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_VERTICAL_CODE 0x318
> +#define USB43DP_V5_5NM_QSERDES_RXB_RES_CODE_THRESH_HIGH_AND_BYP 0x31c
> +#define USB43DP_V5_5NM_QSERDES_RXB_RES_CODE_THRESH_LOW 0x320
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_BKUP_CTRL1 0x324
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_BKUP_CTRL2 0x328
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_BKUP_CTRL3 0x32c
> +#define USB43DP_V5_5NM_QSERDES_RXB_PI_CTRL1 0x330
> +#define USB43DP_V5_5NM_QSERDES_RXB_PI_CTRL2 0x334
> +#define USB43DP_V5_5NM_QSERDES_RXB_PI_QUAD 0x338
> +#define USB43DP_V5_5NM_QSERDES_RXB_QPI_CTRL1 0x33c
> +#define USB43DP_V5_5NM_QSERDES_RXB_QPI_CTRL2 0x340
> +#define USB43DP_V5_5NM_QSERDES_RXB_QPI_QUAD 0x344
> +#define USB43DP_V5_5NM_QSERDES_RXB_IDATA1 0x348
> +#define USB43DP_V5_5NM_QSERDES_RXB_IDATA2 0x34c
> +#define USB43DP_V5_5NM_QSERDES_RXB_IDATA3 0x350
> +#define USB43DP_V5_5NM_QSERDES_RXB_AC_JTAG_OUTP 0x354
> +#define USB43DP_V5_5NM_QSERDES_RXB_AC_JTAG_OUTN 0x358
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_SIGDET 0x35c
> +#define USB43DP_V5_5NM_QSERDES_RXB_ALOG_OBSV_BUS_STATUS_1 0x360
> +#define USB43DP_V5_5NM_QSERDES_RXB_READ_EQCODE 0x364
> +#define USB43DP_V5_5NM_QSERDES_RXB_READ_OFFSETCODE 0x368
> +#define USB43DP_V5_5NM_QSERDES_RXB_IA_ERROR_COUNTER_LOW 0x36c
> +#define USB43DP_V5_5NM_QSERDES_RXB_IA_ERROR_COUNTER_HIGH 0x370
> +#define USB43DP_V5_5NM_QSERDES_RXB_VGA_READ_CODE 0x374
> +#define USB43DP_V5_5NM_QSERDES_RXB_VTHRESH_READ_CODE 0x378
> +#define USB43DP_V5_5NM_QSERDES_RXB_DFE_TAP1_READ_CODE 0x37c
> +#define USB43DP_V5_5NM_QSERDES_RXB_DFE_TAP2_READ_CODE 0x380
> +#define USB43DP_V5_5NM_QSERDES_RXB_DFE_TAP3_READ_CODE 0x384
> +#define USB43DP_V5_5NM_QSERDES_RXB_DFE_TAP4_READ_CODE 0x388
> +#define USB43DP_V5_5NM_QSERDES_RXB_DFE_TAP5_READ_CODE 0x38c
> +#define USB43DP_V5_5NM_QSERDES_RXB_IDAC_STATUS_I0 0x390
> +#define USB43DP_V5_5NM_QSERDES_RXB_IDAC_STATUS_I0BAR 0x394
> +#define USB43DP_V5_5NM_QSERDES_RXB_IDAC_STATUS_I1 0x398
> +#define USB43DP_V5_5NM_QSERDES_RXB_IDAC_STATUS_I1BAR 0x39c
> +#define USB43DP_V5_5NM_QSERDES_RXB_IDAC_STATUS_Q 0x3a0
> +#define USB43DP_V5_5NM_QSERDES_RXB_IDAC_STATUS_QBAR 0x3a4
> +#define USB43DP_V5_5NM_QSERDES_RXB_IDAC_STATUS_A 0x3a8
> +#define USB43DP_V5_5NM_QSERDES_RXB_IDAC_STATUS_ABAR 0x3ac
> +#define USB43DP_V5_5NM_QSERDES_RXB_IDAC_STATUS_SM_ON 0x3b0
> +#define USB43DP_V5_5NM_QSERDES_RXB_IDAC_STATUS_SIGNERROR 0x3b4
> +#define USB43DP_V5_5NM_QSERDES_RXB_IVCM_CAL_STATUS 0x3b8
> +#define USB43DP_V5_5NM_QSERDES_RXB_IVCM_CAL_DEBUG_STATUS 0x3bc
> +#define USB43DP_V5_5NM_QSERDES_RXB_DCC_CAL_STATUS 0x3c0
> +#define USB43DP_V5_5NM_QSERDES_RXB_DCC_READ_CODE_STATUS 0x3c4
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_DEBUG1_STATUS 0x3c8
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_DEBUG2_STATUS 0x3cc
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_READ_CODE_STATUS 0x3d0
> +#define USB43DP_V5_5NM_QSERDES_RXB_EOM_ERR_CNT_LSB_STATUS 0x3d4
> +#define USB43DP_V5_5NM_QSERDES_RXB_EOM_ERR_CNT_MSB_STATUS 0x3d8
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_TUNE_STATUS 0x3dc
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_BKUP_READ_BUS1_STATUS 0x3e0
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_BKUP_READ_BUS2_STATUS 0x3e4
> +#define USB43DP_V5_5NM_QSERDES_RXB_RX_BKUP_READ_BUS3_STATUS 0x3e8
We can also merge _RXA_ and _RXB_.
> +
> +/* Module: USB3_QSERDES_PLL_USB3_QSERDES_PLL_USB4_USB3_DP_QMP_PLL_20G */
> +#define USB3_V5_5NM_QSERDES_PLL_ATB_SEL1 0x000
> +#define USB3_V5_5NM_QSERDES_PLL_ATB_SEL2 0x004
> +#define USB3_V5_5NM_QSERDES_PLL_FREQ_UPDATE 0x008
> +#define USB3_V5_5NM_QSERDES_PLL_BG_TIMER 0x00c
> +#define USB3_V5_5NM_QSERDES_PLL_SSC_EN_CENTER 0x010
> +#define USB3_V5_5NM_QSERDES_PLL_SSC_ADJ_PER1 0x014
> +#define USB3_V5_5NM_QSERDES_PLL_SSC_ADJ_PER2 0x018
> +#define USB3_V5_5NM_QSERDES_PLL_SSC_PER1 0x01c
> +#define USB3_V5_5NM_QSERDES_PLL_SSC_PER2 0x020
> +#define USB3_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024
> +#define USB3_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x028
> +#define USB3_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE3_MODE0 0x02c
> +#define USB3_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x030
> +#define USB3_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x034
> +#define USB3_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE3_MODE1 0x038
> +#define USB3_V5_5NM_QSERDES_PLL_POST_DIV 0x03c
> +#define USB3_V5_5NM_QSERDES_PLL_POST_DIV_MUX 0x040
> +#define USB3_V5_5NM_QSERDES_PLL_BIAS_EN_CLKBUFLR_EN 0x044
> +#define USB3_V5_5NM_QSERDES_PLL_CLK_ENABLE1 0x048
> +#define USB3_V5_5NM_QSERDES_PLL_SYS_CLK_CTRL 0x04c
> +#define USB3_V5_5NM_QSERDES_PLL_SYSCLK_BUF_ENABLE 0x050
> +#define USB3_V5_5NM_QSERDES_PLL_PLL_EN 0x054
> +#define USB3_V5_5NM_QSERDES_PLL_PLL_IVCO 0x058
> +#define USB3_V5_5NM_QSERDES_PLL_CMN_IETRIM 0x05c
> +#define USB3_V5_5NM_QSERDES_PLL_CMN_IPTRIM 0x060
> +#define USB3_V5_5NM_QSERDES_PLL_EP_CLOCK_DETECT_CTRL 0x064
> +#define USB3_V5_5NM_QSERDES_PLL_SYSCLK_DET_COMP_STATUS 0x068
> +#define USB3_V5_5NM_QSERDES_PLL_CLK_EP_DIV_MODE0 0x06c
> +#define USB3_V5_5NM_QSERDES_PLL_CLK_EP_DIV_MODE1 0x070
> +#define USB3_V5_5NM_QSERDES_PLL_CP_CTRL_MODE0 0x074
> +#define USB3_V5_5NM_QSERDES_PLL_CP_CTRL_MODE1 0x078
> +#define USB3_V5_5NM_QSERDES_PLL_PLL_RCTRL_MODE0 0x07c
> +#define USB3_V5_5NM_QSERDES_PLL_PLL_RCTRL_MODE1 0x080
> +#define USB3_V5_5NM_QSERDES_PLL_PLL_CCTRL_MODE0 0x084
> +#define USB3_V5_5NM_QSERDES_PLL_PLL_CCTRL_MODE1 0x088
> +#define USB3_V5_5NM_QSERDES_PLL_PLL_CNTRL 0x08c
> +#define USB3_V5_5NM_QSERDES_PLL_BIAS_EN_CTRL_BY_PSM 0x090
> +#define USB3_V5_5NM_QSERDES_PLL_SYSCLK_EN_SEL 0x094
> +#define USB3_V5_5NM_QSERDES_PLL_CML_SYSCLK_SEL 0x098
> +#define USB3_V5_5NM_QSERDES_PLL_RESETSM_CNTRL 0x09c
> +#define USB3_V5_5NM_QSERDES_PLL_RESETSM_CNTRL2 0x0a0
> +#define USB3_V5_5NM_QSERDES_PLL_LOCK_CMP_EN 0x0a4
> +#define USB3_V5_5NM_QSERDES_PLL_LOCK_CMP_CFG 0x0a8
> +#define USB3_V5_5NM_QSERDES_PLL_LOCK_CMP1_MODE0 0x0ac
> +#define USB3_V5_5NM_QSERDES_PLL_LOCK_CMP2_MODE0 0x0b0
> +#define USB3_V5_5NM_QSERDES_PLL_LOCK_CMP1_MODE1 0x0b4
> +#define USB3_V5_5NM_QSERDES_PLL_LOCK_CMP2_MODE1 0x0b8
> +#define USB3_V5_5NM_QSERDES_PLL_DEC_START_MODE0 0x0bc
> +#define USB3_V5_5NM_QSERDES_PLL_DEC_START_MSB_MODE0 0x0c0
> +#define USB3_V5_5NM_QSERDES_PLL_DEC_START_MODE1 0x0c4
> +#define USB3_V5_5NM_QSERDES_PLL_DEC_START_MSB_MODE1 0x0c8
> +#define USB3_V5_5NM_QSERDES_PLL_DIV_FRAC_START1_MODE0 0x0cc
> +#define USB3_V5_5NM_QSERDES_PLL_DIV_FRAC_START2_MODE0 0x0d0
> +#define USB3_V5_5NM_QSERDES_PLL_DIV_FRAC_START3_MODE0 0x0d4
> +#define USB3_V5_5NM_QSERDES_PLL_DIV_FRAC_START1_MODE1 0x0d8
> +#define USB3_V5_5NM_QSERDES_PLL_DIV_FRAC_START2_MODE1 0x0dc
> +#define USB3_V5_5NM_QSERDES_PLL_DIV_FRAC_START3_MODE1 0x0e0
> +#define USB3_V5_5NM_QSERDES_PLL_INTEGLOOP_INITVAL 0x0e4
> +#define USB3_V5_5NM_QSERDES_PLL_INTEGLOOP_EN 0x0e8
> +#define USB3_V5_5NM_QSERDES_PLL_INTEGLOOP_GAIN0_MODE0 0x0ec
> +#define USB3_V5_5NM_QSERDES_PLL_INTEGLOOP_GAIN1_MODE0 0x0f0
> +#define USB3_V5_5NM_QSERDES_PLL_INTEGLOOP_GAIN0_MODE1 0x0f4
> +#define USB3_V5_5NM_QSERDES_PLL_INTEGLOOP_GAIN1_MODE1 0x0f8
> +#define USB3_V5_5NM_QSERDES_PLL_INTEGLOOP_P_PATH_GAIN0 0x0fc
> +#define USB3_V5_5NM_QSERDES_PLL_INTEGLOOP_P_PATH_GAIN1 0x100
> +#define USB3_V5_5NM_QSERDES_PLL_VCOCAL_DEADMAN_CTRL 0x104
> +#define USB3_V5_5NM_QSERDES_PLL_VCO_TUNE_CTRL 0x108
> +#define USB3_V5_5NM_QSERDES_PLL_VCO_TUNE_MAP 0x10c
> +#define USB3_V5_5NM_QSERDES_PLL_VCO_TUNE1_MODE0 0x110
> +#define USB3_V5_5NM_QSERDES_PLL_VCO_TUNE2_MODE0 0x114
> +#define USB3_V5_5NM_QSERDES_PLL_VCO_TUNE1_MODE1 0x118
> +#define USB3_V5_5NM_QSERDES_PLL_VCO_TUNE2_MODE1 0x11c
> +#define USB3_V5_5NM_QSERDES_PLL_VCO_TUNE_INITVAL1 0x120
> +#define USB3_V5_5NM_QSERDES_PLL_VCO_TUNE_INITVAL2 0x124
> +#define USB3_V5_5NM_QSERDES_PLL_VCO_TUNE_MINVAL1 0x128
> +#define USB3_V5_5NM_QSERDES_PLL_VCO_TUNE_MINVAL2 0x12c
> +#define USB3_V5_5NM_QSERDES_PLL_VCO_TUNE_MAXVAL1 0x130
> +#define USB3_V5_5NM_QSERDES_PLL_VCO_TUNE_MAXVAL2 0x134
> +#define USB3_V5_5NM_QSERDES_PLL_VCO_TUNE_TIMER1 0x138
> +#define USB3_V5_5NM_QSERDES_PLL_VCO_TUNE_TIMER2 0x13c
> +#define USB3_V5_5NM_QSERDES_PLL_CMN_STATUS 0x140
> +#define USB3_V5_5NM_QSERDES_PLL_RESET_SM_STATUS 0x144
> +#define USB3_V5_5NM_QSERDES_PLL_RESTRIM_CODE_STATUS 0x148
> +#define USB3_V5_5NM_QSERDES_PLL_PLLCAL_CODE1_STATUS 0x14c
> +#define USB3_V5_5NM_QSERDES_PLL_PLLCAL_CODE2_STATUS 0x150
> +#define USB3_V5_5NM_QSERDES_PLL_CLK_SELECT 0x154
> +#define USB3_V5_5NM_QSERDES_PLL_HSCLK_SEL 0x158
> +#define USB3_V5_5NM_QSERDES_PLL_HSCLK_HS_SWITCH_SEL 0x15c
> +#define USB3_V5_5NM_QSERDES_PLL_INTEGLOOP_BINCODE_STATUS 0x160
> +#define USB3_V5_5NM_QSERDES_PLL_PLL_ANALOG 0x164
> +#define USB3_V5_5NM_QSERDES_PLL_CORECLK_DIV_MODE0 0x168
> +#define USB3_V5_5NM_QSERDES_PLL_CORECLK_DIV_MODE1 0x16c
> +#define USB3_V5_5NM_QSERDES_PLL_SW_RESET 0x170
> +#define USB3_V5_5NM_QSERDES_PLL_CORE_CLK_EN 0x174
> +#define USB3_V5_5NM_QSERDES_PLL_C_READY_STATUS 0x178
> +#define USB3_V5_5NM_QSERDES_PLL_CMN_CONFIG 0x17c
> +#define USB3_V5_5NM_QSERDES_PLL_CMN_RATE_OVERRIDE 0x180
> +#define USB3_V5_5NM_QSERDES_PLL_SVS_MODE_CLK_SEL 0x184
> +#define USB3_V5_5NM_QSERDES_PLL_DEBUG_BUS0 0x188
> +#define USB3_V5_5NM_QSERDES_PLL_DEBUG_BUS1 0x18c
> +#define USB3_V5_5NM_QSERDES_PLL_DEBUG_BUS2 0x190
> +#define USB3_V5_5NM_QSERDES_PLL_DEBUG_BUS3 0x194
> +#define USB3_V5_5NM_QSERDES_PLL_DEBUG_BUS_SEL 0x198
> +#define USB3_V5_5NM_QSERDES_PLL_CMN_MISC1 0x19c
> +#define USB3_V5_5NM_QSERDES_PLL_CMN_MODE 0x1a0
> +#define USB3_V5_5NM_QSERDES_PLL_CMN_MODE_CONTD 0x1a4
> +#define USB3_V5_5NM_QSERDES_PLL_VCO_DC_LEVEL_CTRL 0x1a8
> +#define USB3_V5_5NM_QSERDES_PLL_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac
> +#define USB3_V5_5NM_QSERDES_PLL_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0
> +#define USB3_V5_5NM_QSERDES_PLL_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4
> +#define USB3_V5_5NM_QSERDES_PLL_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8
> +#define USB3_V5_5NM_QSERDES_PLL_BIN_VCOCAL_HSCLK_SEL 0x1bc
> +#define USB3_V5_5NM_QSERDES_PLL_ADDITIONAL_CTRL_1 0x1c0
> +#define USB3_V5_5NM_QSERDES_PLL_MODE_OPERATION_STATUS 0x1c4
> +#define USB3_V5_5NM_QSERDES_PLL_AUTO_GAIN_ADJ_CTRL_1 0x1c8
> +#define USB3_V5_5NM_QSERDES_PLL_AUTO_GAIN_ADJ_CTRL_2 0x1cc
> +#define USB3_V5_5NM_QSERDES_PLL_AUTO_GAIN_ADJ_CTRL_3 0x1d0
> +#define USB3_V5_5NM_QSERDES_PLL_AUTO_GAIN_ADJ_CTRL_4 0x1d4
> +#define USB3_V5_5NM_QSERDES_PLL_ADDITIONAL_MISC 0x1d8
> +#define USB3_V5_5NM_QSERDES_PLL_ADDITIONAL_MISC_2 0x1dc
> +#define USB3_V5_5NM_QSERDES_PLL_ADDITIONAL_MISC_3 0x1e0
QSERDES_V5_COM_foo
> +
> +/* Module: USB3_PCS_MISC_USB3_PCS_MISC_USB3_PCS_MISC */
> +#define USB3_V5_5NM_PCS_MISC_TYPEC_CTRL 0x00
> +#define USB3_V5_5NM_PCS_MISC_TYPEC_PWRDN_CTRL 0x04
> +#define USB3_V5_5NM_PCS_MISC_PCS_MISC_CONFIG1 0x08
> +#define USB3_V5_5NM_PCS_MISC_CLAMP_ENABLE 0x0c
> +#define USB3_V5_5NM_PCS_MISC_TYPEC_STATUS 0x10
> +#define USB3_V5_5NM_PCS_MISC_PLACEHOLDER_STATUS 0x14
QPHY_V4_PCS_MISC (or v5)
> +
> +/* Module: USB3_PCS_LN_USB3_PCS_LN_USB3_PCS_LANE */
> +#define USB3_V5_5NM_PCS_LN_PCS_STATUS1 0x00
> +#define USB3_V5_5NM_PCS_LN_PCS_STATUS2 0x04
> +#define USB3_V5_5NM_PCS_LN_PCS_STATUS2_CLEAR 0x08
> +#define USB3_V5_5NM_PCS_LN_PCS_STATUS3 0x0c
> +#define USB3_V5_5NM_PCS_LN_BIST_CHK_ERR_CNT_L_STATUS 0x10
> +#define USB3_V5_5NM_PCS_LN_BIST_CHK_ERR_CNT_H_STATUS 0x14
> +#define USB3_V5_5NM_PCS_LN_BIST_CHK_STATUS 0x18
> +#define USB3_V5_5NM_PCS_LN_INSIG_SW_CTRL1 0x1c
> +#define USB3_V5_5NM_PCS_LN_INSIG_MX_CTRL1 0x20
> +#define USB3_V5_5NM_PCS_LN_OUTSIG_SW_CTRL1 0x24
> +#define USB3_V5_5NM_PCS_LN_OUTSIG_MX_CTRL1 0x28
> +#define USB3_V5_5NM_PCS_LN_TEST_CONTROL1 0x2c
> +#define USB3_V5_5NM_PCS_LN_BIST_CTRL 0x30
> +#define USB3_V5_5NM_PCS_LN_PRBS_SEED0 0x34
> +#define USB3_V5_5NM_PCS_LN_PRBS_SEED1 0x38
> +#define USB3_V5_5NM_PCS_LN_FIXED_PAT_CTRL 0x3c
> +#define USB3_V5_5NM_PCS_LN_EQ_CONFIG 0x40
> +#define USB3_V5_5NM_PCS_LN_TEST_CONTROL2 0x44
> +#define USB3_V5_5NM_PCS_LN_TEST_CONTROL3 0x48
> +
> +/* Module: USB3_PCS_USB3_PCS_USB3_PCS */
> +#define USB3_V5_5NM_PCS_SW_RESET 0x000
> +#define USB3_V5_5NM_PCS_REVISION_ID0 0x004
> +#define USB3_V5_5NM_PCS_REVISION_ID1 0x008
> +#define USB3_V5_5NM_PCS_REVISION_ID2 0x00c
> +#define USB3_V5_5NM_PCS_REVISION_ID3 0x010
> +#define USB3_V5_5NM_PCS_PCS_STATUS1 0x014
> +#define USB3_V5_5NM_PCS_PCS_STATUS2 0x018
> +#define USB3_V5_5NM_PCS_PCS_STATUS3 0x01c
> +#define USB3_V5_5NM_PCS_PCS_STATUS4 0x020
> +#define USB3_V5_5NM_PCS_PCS_STATUS5 0x024
> +#define USB3_V5_5NM_PCS_PCS_STATUS6 0x028
> +#define USB3_V5_5NM_PCS_PCS_STATUS7 0x02c
> +#define USB3_V5_5NM_PCS_DEBUG_BUS_0_STATUS 0x030
> +#define USB3_V5_5NM_PCS_DEBUG_BUS_1_STATUS 0x034
> +#define USB3_V5_5NM_PCS_DEBUG_BUS_2_STATUS 0x038
> +#define USB3_V5_5NM_PCS_DEBUG_BUS_3_STATUS 0x03c
> +#define USB3_V5_5NM_PCS_POWER_DOWN_CONTROL 0x040
> +#define USB3_V5_5NM_PCS_START_CONTROL 0x044
> +#define USB3_V5_5NM_PCS_INSIG_SW_CTRL1 0x048
> +#define USB3_V5_5NM_PCS_INSIG_SW_CTRL2 0x04c
> +#define USB3_V5_5NM_PCS_INSIG_SW_CTRL3 0x050
> +#define USB3_V5_5NM_PCS_INSIG_SW_CTRL4 0x054
> +#define USB3_V5_5NM_PCS_INSIG_SW_CTRL5 0x058
> +#define USB3_V5_5NM_PCS_INSIG_SW_CTRL6 0x05c
> +#define USB3_V5_5NM_PCS_INSIG_SW_CTRL7 0x060
> +#define USB3_V5_5NM_PCS_INSIG_SW_CTRL8 0x064
> +#define USB3_V5_5NM_PCS_INSIG_MX_CTRL1 0x068
> +#define USB3_V5_5NM_PCS_INSIG_MX_CTRL2 0x06c
> +#define USB3_V5_5NM_PCS_INSIG_MX_CTRL3 0x070
> +#define USB3_V5_5NM_PCS_INSIG_MX_CTRL4 0x074
> +#define USB3_V5_5NM_PCS_INSIG_MX_CTRL5 0x078
> +#define USB3_V5_5NM_PCS_INSIG_MX_CTRL7 0x07c
> +#define USB3_V5_5NM_PCS_INSIG_MX_CTRL8 0x080
> +#define USB3_V5_5NM_PCS_OUTSIG_SW_CTRL1 0x084
> +#define USB3_V5_5NM_PCS_OUTSIG_MX_CTRL1 0x088
> +#define USB3_V5_5NM_PCS_CLAMP_ENABLE 0x08c
> +#define USB3_V5_5NM_PCS_POWER_STATE_CONFIG1 0x090
> +#define USB3_V5_5NM_PCS_POWER_STATE_CONFIG2 0x094
> +#define USB3_V5_5NM_PCS_FLL_CNTRL1 0x098
> +#define USB3_V5_5NM_PCS_FLL_CNTRL2 0x09c
> +#define USB3_V5_5NM_PCS_FLL_CNT_VAL_L 0x0a0
> +#define USB3_V5_5NM_PCS_FLL_CNT_VAL_H_TOL 0x0a4
> +#define USB3_V5_5NM_PCS_FLL_MAN_CODE 0x0a8
> +#define USB3_V5_5NM_PCS_TEST_CONTROL1 0x0ac
> +#define USB3_V5_5NM_PCS_TEST_CONTROL2 0x0b0
> +#define USB3_V5_5NM_PCS_TEST_CONTROL3 0x0b4
> +#define USB3_V5_5NM_PCS_TEST_CONTROL4 0x0b8
> +#define USB3_V5_5NM_PCS_TEST_CONTROL5 0x0bc
> +#define USB3_V5_5NM_PCS_TEST_CONTROL6 0x0c0
> +#define USB3_V5_5NM_PCS_LOCK_DETECT_CONFIG1 0x0c4
> +#define USB3_V5_5NM_PCS_LOCK_DETECT_CONFIG2 0x0c8
> +#define USB3_V5_5NM_PCS_LOCK_DETECT_CONFIG3 0x0cc
> +#define USB3_V5_5NM_PCS_LOCK_DETECT_CONFIG4 0x0d0
> +#define USB3_V5_5NM_PCS_LOCK_DETECT_CONFIG5 0x0d4
> +#define USB3_V5_5NM_PCS_LOCK_DETECT_CONFIG6 0x0d8
> +#define USB3_V5_5NM_PCS_REFGEN_REQ_CONFIG1 0x0dc
> +#define USB3_V5_5NM_PCS_REFGEN_REQ_CONFIG2 0x0e0
> +#define USB3_V5_5NM_PCS_REFGEN_REQ_CONFIG3 0x0e4
> +#define USB3_V5_5NM_PCS_BIST_CTRL 0x0e8
> +#define USB3_V5_5NM_PCS_PRBS_POLY0 0x0ec
> +#define USB3_V5_5NM_PCS_PRBS_POLY1 0x0f0
> +#define USB3_V5_5NM_PCS_FIXED_PAT0 0x0f4
> +#define USB3_V5_5NM_PCS_FIXED_PAT1 0x0f8
> +#define USB3_V5_5NM_PCS_FIXED_PAT2 0x0fc
> +#define USB3_V5_5NM_PCS_FIXED_PAT3 0x100
> +#define USB3_V5_5NM_PCS_FIXED_PAT4 0x104
> +#define USB3_V5_5NM_PCS_FIXED_PAT5 0x108
> +#define USB3_V5_5NM_PCS_FIXED_PAT6 0x10c
> +#define USB3_V5_5NM_PCS_FIXED_PAT7 0x110
> +#define USB3_V5_5NM_PCS_FIXED_PAT8 0x114
> +#define USB3_V5_5NM_PCS_FIXED_PAT9 0x118
> +#define USB3_V5_5NM_PCS_FIXED_PAT10 0x11c
> +#define USB3_V5_5NM_PCS_FIXED_PAT11 0x120
> +#define USB3_V5_5NM_PCS_FIXED_PAT12 0x124
> +#define USB3_V5_5NM_PCS_FIXED_PAT13 0x128
> +#define USB3_V5_5NM_PCS_FIXED_PAT14 0x12c
> +#define USB3_V5_5NM_PCS_FIXED_PAT15 0x130
> +#define USB3_V5_5NM_PCS_TXMGN_CONFIG 0x134
> +#define USB3_V5_5NM_PCS_G12S1_TXMGN_V0 0x138
> +#define USB3_V5_5NM_PCS_G12S1_TXMGN_V1 0x13c
> +#define USB3_V5_5NM_PCS_G12S1_TXMGN_V2 0x140
> +#define USB3_V5_5NM_PCS_G12S1_TXMGN_V3 0x144
> +#define USB3_V5_5NM_PCS_G12S1_TXMGN_V4 0x148
> +#define USB3_V5_5NM_PCS_G12S1_TXMGN_V0_RS 0x14c
> +#define USB3_V5_5NM_PCS_G12S1_TXMGN_V1_RS 0x150
> +#define USB3_V5_5NM_PCS_G12S1_TXMGN_V2_RS 0x154
> +#define USB3_V5_5NM_PCS_G12S1_TXMGN_V3_RS 0x158
> +#define USB3_V5_5NM_PCS_G12S1_TXMGN_V4_RS 0x15c
> +#define USB3_V5_5NM_PCS_G3S2_TXMGN_MAIN 0x160
> +#define USB3_V5_5NM_PCS_G3S2_TXMGN_MAIN_RS 0x164
> +#define USB3_V5_5NM_PCS_G12S1_TXDEEMPH_M6DB 0x168
> +#define USB3_V5_5NM_PCS_G12S1_TXDEEMPH_M3P5DB 0x16c
> +#define USB3_V5_5NM_PCS_G3S2_PRE_GAIN 0x170
> +#define USB3_V5_5NM_PCS_G3S2_POST_GAIN 0x174
> +#define USB3_V5_5NM_PCS_G3S2_PRE_POST_OFFSET 0x178
> +#define USB3_V5_5NM_PCS_G3S2_PRE_GAIN_RS 0x17c
> +#define USB3_V5_5NM_PCS_G3S2_POST_GAIN_RS 0x180
> +#define USB3_V5_5NM_PCS_G3S2_PRE_POST_OFFSET_RS 0x184
> +#define USB3_V5_5NM_PCS_RX_SIGDET_LVL 0x188
> +#define USB3_V5_5NM_PCS_RX_SIGDET_DTCT_CNTRL 0x18c
> +#define USB3_V5_5NM_PCS_RCVR_DTCT_DLY_P1U2_L 0x190
> +#define USB3_V5_5NM_PCS_RCVR_DTCT_DLY_P1U2_H 0x194
> +#define USB3_V5_5NM_PCS_RATE_SLEW_CNTRL1 0x198
> +#define USB3_V5_5NM_PCS_RATE_SLEW_CNTRL2 0x19c
> +#define USB3_V5_5NM_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x1a0
> +#define USB3_V5_5NM_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4
> +#define USB3_V5_5NM_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8
> +#define USB3_V5_5NM_PCS_TSYNC_RSYNC_TIME 0x1ac
> +#define USB3_V5_5NM_PCS_RX_CONFIG 0x1b0
> +#define USB3_V5_5NM_PCS_TSYNC_DLY_TIME 0x1b4
> +#define USB3_V5_5NM_PCS_ELECIDLE_DLY_SEL 0x1b8
> +#define USB3_V5_5NM_PCS_CMN_ACK_OUT_SEL 0x1bc
> +#define USB3_V5_5NM_PCS_ALIGN_DETECT_CONFIG1 0x1c0
> +#define USB3_V5_5NM_PCS_ALIGN_DETECT_CONFIG2 0x1c4
> +#define USB3_V5_5NM_PCS_ALIGN_DETECT_CONFIG3 0x1c8
> +#define USB3_V5_5NM_PCS_ALIGN_DETECT_CONFIG4 0x1cc
> +#define USB3_V5_5NM_PCS_PCS_TX_RX_CONFIG 0x1d0
> +#define USB3_V5_5NM_PCS_RX_IDLE_DTCT_CNTRL 0x1d4
> +#define USB3_V5_5NM_PCS_RX_DCC_CAL_CONFIG 0x1d8
> +#define USB3_V5_5NM_PCS_EQ_CONFIG1 0x1dc
> +#define USB3_V5_5NM_PCS_EQ_CONFIG2 0x1e0
> +#define USB3_V5_5NM_PCS_EQ_CONFIG3 0x1e4
> +#define USB3_V5_5NM_PCS_EQ_CONFIG4 0x1E8
> +#define USB3_V5_5NM_PCS_EQ_CONFIG5 0x1EC
This looks like both QPHY_V4_PCS and QPHY_V5_PCS. Most probably we
should merge them together and add these defines.
> +
> +/* Module: USB3_PCS_USB3_USB3_PCS_USB3_USB3_PCS_USB3 */
> +#define USB3_V5_5NM_PCS_USB3_POWER_STATE_CONFIG1 0x00
> +#define USB3_V5_5NM_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x04
> +#define USB3_V5_5NM_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x08
> +#define USB3_V5_5NM_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x0c
> +#define USB3_V5_5NM_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x10
> +#define USB3_V5_5NM_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x14
> +#define USB3_V5_5NM_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x18
> +#define USB3_V5_5NM_PCS_USB3_LFPS_TX_ECSTART 0x1c
> +#define USB3_V5_5NM_PCS_USB3_LFPS_PER_TIMER_VAL 0x20
> +#define USB3_V5_5NM_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x24
> +#define USB3_V5_5NM_PCS_USB3_LFPS_CONFIG1 0x28
> +#define USB3_V5_5NM_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x2c
> +#define USB3_V5_5NM_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x30
> +#define USB3_V5_5NM_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x34
> +#define USB3_V5_5NM_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x38
> +#define USB3_V5_5NM_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x3c
> +#define USB3_V5_5NM_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x40
> +#define USB3_V5_5NM_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x44
> +#define USB3_V5_5NM_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x48
> +#define USB3_V5_5NM_PCS_USB3_ARCVR_DTCT_CM_DLY 0x4c
> +#define USB3_V5_5NM_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x50
> +#define USB3_V5_5NM_PCS_USB3_ALFPS_DEGLITCH_VAL 0x54
> +#define USB3_V5_5NM_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x58
> +#define USB3_V5_5NM_PCS_USB3_TEST_CONTROL 0x5c
> +#define USB3_V5_5NM_PCS_USB3_RXTERMINATION_DLY_SEL 0x60
Again, QPHY_V5_PCS_USB w/o the 0x300 offset
> +
> +/* Module: DP_QSERDES_PLL_DP_QSERDES_PLL_USB4_USB3_DP_QMP_PLL */
> +#define DP_V5_5NM_QSERDES_PLL_ATB_SEL1 0x000
> +#define DP_V5_5NM_QSERDES_PLL_ATB_SEL2 0x004
> +#define DP_V5_5NM_QSERDES_PLL_FREQ_UPDATE 0x008
> +#define DP_V5_5NM_QSERDES_PLL_BG_TIMER 0x00c
> +#define DP_V5_5NM_QSERDES_PLL_SSC_EN_CENTER 0x010
> +#define DP_V5_5NM_QSERDES_PLL_SSC_ADJ_PER1 0x014
> +#define DP_V5_5NM_QSERDES_PLL_SSC_ADJ_PER2 0x018
> +#define DP_V5_5NM_QSERDES_PLL_SSC_PER1 0x01c
> +#define DP_V5_5NM_QSERDES_PLL_SSC_PER2 0x020
> +#define DP_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024
> +#define DP_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x028
> +#define DP_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE3_MODE0 0x02c
> +#define DP_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x030
> +#define DP_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x034
> +#define DP_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE3_MODE1 0x038
> +#define DP_V5_5NM_QSERDES_PLL_POST_DIV 0x03c
> +#define DP_V5_5NM_QSERDES_PLL_POST_DIV_MUX 0x040
> +#define DP_V5_5NM_QSERDES_PLL_BIAS_EN_CLKBUFLR_EN 0x044
> +#define DP_V5_5NM_QSERDES_PLL_CLK_ENABLE1 0x048
> +#define DP_V5_5NM_QSERDES_PLL_SYS_CLK_CTRL 0x04c
> +#define DP_V5_5NM_QSERDES_PLL_SYSCLK_BUF_ENABLE 0x050
> +#define DP_V5_5NM_QSERDES_PLL_PLL_EN 0x054
> +#define DP_V5_5NM_QSERDES_PLL_PLL_IVCO 0x058
> +#define DP_V5_5NM_QSERDES_PLL_CMN_IETRIM 0x05c
> +#define DP_V5_5NM_QSERDES_PLL_CMN_IPTRIM 0x060
> +#define DP_V5_5NM_QSERDES_PLL_EP_CLOCK_DETECT_CTRL 0x064
> +#define DP_V5_5NM_QSERDES_PLL_SYSCLK_DET_COMP_STATUS 0x068
> +#define DP_V5_5NM_QSERDES_PLL_CLK_EP_DIV_MODE0 0x06c
> +#define DP_V5_5NM_QSERDES_PLL_CLK_EP_DIV_MODE1 0x070
> +#define DP_V5_5NM_QSERDES_PLL_CP_CTRL_MODE0 0x074
> +#define DP_V5_5NM_QSERDES_PLL_CP_CTRL_MODE1 0x078
> +#define DP_V5_5NM_QSERDES_PLL_PLL_RCTRL_MODE0 0x07c
> +#define DP_V5_5NM_QSERDES_PLL_PLL_RCTRL_MODE1 0x080
> +#define DP_V5_5NM_QSERDES_PLL_PLL_CCTRL_MODE0 0x084
> +#define DP_V5_5NM_QSERDES_PLL_PLL_CCTRL_MODE1 0x088
> +#define DP_V5_5NM_QSERDES_PLL_PLL_CNTRL 0x08c
> +#define DP_V5_5NM_QSERDES_PLL_BIAS_EN_CTRL_BY_PSM 0x090
> +#define DP_V5_5NM_QSERDES_PLL_SYSCLK_EN_SEL 0x094
> +#define DP_V5_5NM_QSERDES_PLL_CML_SYSCLK_SEL 0x098
> +#define DP_V5_5NM_QSERDES_PLL_RESETSM_CNTRL 0x09c
> +#define DP_V5_5NM_QSERDES_PLL_RESETSM_CNTRL2 0x0a0
> +#define DP_V5_5NM_QSERDES_PLL_LOCK_CMP_EN 0x0a4
> +#define DP_V5_5NM_QSERDES_PLL_LOCK_CMP_CFG 0x0a8
> +#define DP_V5_5NM_QSERDES_PLL_LOCK_CMP1_MODE0 0x0ac
> +#define DP_V5_5NM_QSERDES_PLL_LOCK_CMP2_MODE0 0x0b0
> +#define DP_V5_5NM_QSERDES_PLL_LOCK_CMP1_MODE1 0x0b4
> +#define DP_V5_5NM_QSERDES_PLL_LOCK_CMP2_MODE1 0x0b8
> +#define DP_V5_5NM_QSERDES_PLL_DEC_START_MODE0 0x0bc
> +#define DP_V5_5NM_QSERDES_PLL_DEC_START_MSB_MODE0 0x0c0
> +#define DP_V5_5NM_QSERDES_PLL_DEC_START_MODE1 0x0c4
> +#define DP_V5_5NM_QSERDES_PLL_DEC_START_MSB_MODE1 0x0c8
> +#define DP_V5_5NM_QSERDES_PLL_DIV_FRAC_START1_MODE0 0x0cc
> +#define DP_V5_5NM_QSERDES_PLL_DIV_FRAC_START2_MODE0 0x0d0
> +#define DP_V5_5NM_QSERDES_PLL_DIV_FRAC_START3_MODE0 0x0d4
> +#define DP_V5_5NM_QSERDES_PLL_DIV_FRAC_START1_MODE1 0x0d8
> +#define DP_V5_5NM_QSERDES_PLL_DIV_FRAC_START2_MODE1 0x0dc
> +#define DP_V5_5NM_QSERDES_PLL_DIV_FRAC_START3_MODE1 0x0e0
> +#define DP_V5_5NM_QSERDES_PLL_INTEGLOOP_INITVAL 0x0e4
> +#define DP_V5_5NM_QSERDES_PLL_INTEGLOOP_EN 0x0e8
> +#define DP_V5_5NM_QSERDES_PLL_INTEGLOOP_GAIN0_MODE0 0x0ec
> +#define DP_V5_5NM_QSERDES_PLL_INTEGLOOP_GAIN1_MODE0 0x0f0
> +#define DP_V5_5NM_QSERDES_PLL_INTEGLOOP_GAIN0_MODE1 0x0f4
> +#define DP_V5_5NM_QSERDES_PLL_INTEGLOOP_GAIN1_MODE1 0x0f8
> +#define DP_V5_5NM_QSERDES_PLL_INTEGLOOP_P_PATH_GAIN0 0x0fc
> +#define DP_V5_5NM_QSERDES_PLL_INTEGLOOP_P_PATH_GAIN1 0x100
> +#define DP_V5_5NM_QSERDES_PLL_VCOCAL_DEADMAN_CTRL 0x104
> +#define DP_V5_5NM_QSERDES_PLL_VCO_TUNE_CTRL 0x108
> +#define DP_V5_5NM_QSERDES_PLL_VCO_TUNE_MAP 0x10c
> +#define DP_V5_5NM_QSERDES_PLL_VCO_TUNE1_MODE0 0x110
> +#define DP_V5_5NM_QSERDES_PLL_VCO_TUNE2_MODE0 0x114
> +#define DP_V5_5NM_QSERDES_PLL_VCO_TUNE1_MODE1 0x118
> +#define DP_V5_5NM_QSERDES_PLL_VCO_TUNE2_MODE1 0x11c
> +#define DP_V5_5NM_QSERDES_PLL_VCO_TUNE_INITVAL1 0x120
> +#define DP_V5_5NM_QSERDES_PLL_VCO_TUNE_INITVAL2 0x124
> +#define DP_V5_5NM_QSERDES_PLL_VCO_TUNE_MINVAL1 0x128
> +#define DP_V5_5NM_QSERDES_PLL_VCO_TUNE_MINVAL2 0x12c
> +#define DP_V5_5NM_QSERDES_PLL_VCO_TUNE_MAXVAL1 0x130
> +#define DP_V5_5NM_QSERDES_PLL_VCO_TUNE_MAXVAL2 0x134
> +#define DP_V5_5NM_QSERDES_PLL_VCO_TUNE_TIMER1 0x138
> +#define DP_V5_5NM_QSERDES_PLL_VCO_TUNE_TIMER2 0x13c
> +#define DP_V5_5NM_QSERDES_PLL_CMN_STATUS 0x140
> +#define DP_V5_5NM_QSERDES_PLL_RESET_SM_STATUS 0x144
> +#define DP_V5_5NM_QSERDES_PLL_RESTRIM_CODE_STATUS 0x148
> +#define DP_V5_5NM_QSERDES_PLL_PLLCAL_CODE1_STATUS 0x14c
> +#define DP_V5_5NM_QSERDES_PLL_PLLCAL_CODE2_STATUS 0x150
> +#define DP_V5_5NM_QSERDES_PLL_CLK_SELECT 0x154
> +#define DP_V5_5NM_QSERDES_PLL_HSCLK_SEL 0x158
> +#define DP_V5_5NM_QSERDES_PLL_HSCLK_HS_SWITCH_SEL 0x15c
> +#define DP_V5_5NM_QSERDES_PLL_INTEGLOOP_BINCODE_STATUS 0x160
> +#define DP_V5_5NM_QSERDES_PLL_PLL_ANALOG 0x164
> +#define DP_V5_5NM_QSERDES_PLL_CORECLK_DIV_MODE0 0x168
> +#define DP_V5_5NM_QSERDES_PLL_CORECLK_DIV_MODE1 0x16c
> +#define DP_V5_5NM_QSERDES_PLL_SW_RESET 0x170
> +#define DP_V5_5NM_QSERDES_PLL_CORE_CLK_EN 0x174
> +#define DP_V5_5NM_QSERDES_PLL_C_READY_STATUS 0x178
> +#define DP_V5_5NM_QSERDES_PLL_CMN_CONFIG 0x17c
> +#define DP_V5_5NM_QSERDES_PLL_CMN_RATE_OVERRIDE 0x180
> +#define DP_V5_5NM_QSERDES_PLL_SVS_MODE_CLK_SEL 0x184
> +#define DP_V5_5NM_QSERDES_PLL_DEBUG_BUS0 0x188
> +#define DP_V5_5NM_QSERDES_PLL_DEBUG_BUS1 0x18c
> +#define DP_V5_5NM_QSERDES_PLL_DEBUG_BUS2 0x190
> +#define DP_V5_5NM_QSERDES_PLL_DEBUG_BUS3 0x194
> +#define DP_V5_5NM_QSERDES_PLL_DEBUG_BUS_SEL 0x198
> +#define DP_V5_5NM_QSERDES_PLL_CMN_MISC1 0x19c
> +#define DP_V5_5NM_QSERDES_PLL_CMN_MODE 0x1a0
> +#define DP_V5_5NM_QSERDES_PLL_CMN_MODE_CONTD 0x1a4
> +#define DP_V5_5NM_QSERDES_PLL_VCO_DC_LEVEL_CTRL 0x1a8
> +#define DP_V5_5NM_QSERDES_PLL_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac
> +#define DP_V5_5NM_QSERDES_PLL_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0
> +#define DP_V5_5NM_QSERDES_PLL_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4
> +#define DP_V5_5NM_QSERDES_PLL_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8
> +#define DP_V5_5NM_QSERDES_PLL_BIN_VCOCAL_HSCLK_SEL 0x1bc
> +#define DP_V5_5NM_QSERDES_PLL_RESERVED_1 0x1c0
> +#define DP_V5_5NM_QSERDES_PLL_MODE_OPERATION_STATUS 0x1c4
QSERDES_V5_COM
> +
> +/* Module: DP_DP_DP_PHY */
> +#define DP_V5_5NM_DP_PHY_REVISION_ID0 0x000
> +#define DP_V5_5NM_DP_PHY_REVISION_ID1 0x004
> +#define DP_V5_5NM_DP_PHY_REVISION_ID2 0x008
> +#define DP_V5_5NM_DP_PHY_REVISION_ID3 0x00c
> +#define DP_V5_5NM_DP_PHY_CFG 0x010
> +#define DP_V5_5NM_DP_PHY_CFG_1 0x014
> +#define DP_V5_5NM_DP_PHY_PD_CTL 0x018
> +#define DP_V5_5NM_DP_PHY_MODE 0x01c
> +#define DP_V5_5NM_DP_PHY_AUX_CFG0 0x020
> +#define DP_V5_5NM_DP_PHY_AUX_CFG1 0x024
> +#define DP_V5_5NM_DP_PHY_AUX_CFG2 0x028
> +#define DP_V5_5NM_DP_PHY_AUX_CFG3 0x02c
> +#define DP_V5_5NM_DP_PHY_AUX_CFG4 0x030
> +#define DP_V5_5NM_DP_PHY_AUX_CFG5 0x034
> +#define DP_V5_5NM_DP_PHY_AUX_CFG6 0x038
> +#define DP_V5_5NM_DP_PHY_AUX_CFG7 0x03c
> +#define DP_V5_5NM_DP_PHY_AUX_CFG8 0x040
> +#define DP_V5_5NM_DP_PHY_AUX_CFG9 0x044
> +#define DP_V5_5NM_DP_PHY_AUX_CFG10 0x048
> +#define DP_V5_5NM_DP_PHY_AUX_CFG11 0x04c
> +#define DP_V5_5NM_DP_PHY_AUX_CFG12 0x050
> +#define DP_V5_5NM_DP_PHY_AUX_INTERRUPT_MASK 0x054
> +#define DP_V5_5NM_DP_PHY_AUX_INTERRUPT_CLEAR 0x058
> +#define DP_V5_5NM_DP_PHY_AUX_BIST_CFG 0x05c
> +#define DP_V5_5NM_DP_PHY_AUX_BIST_PRBS_SEED 0x060
> +#define DP_V5_5NM_DP_PHY_AUX_BIST_PRBS_POLY 0x064
> +#define DP_V5_5NM_DP_PHY_AUX_TX_PROG_PAT_16B_LSB 0x068
> +#define DP_V5_5NM_DP_PHY_AUX_TX_PROG_PAT_16B_MSB 0x06c
> +#define DP_V5_5NM_DP_PHY_VCO_DIV 0x070
> +#define DP_V5_5NM_DP_PHY_TSYNC_OVRD 0x074
> +#define DP_V5_5NM_DP_PHY_TX0_TX1_LANE_CTL 0x078
> +#define DP_V5_5NM_DP_PHY_TX0_TX1_BIST_CFG0 0x07c
> +#define DP_V5_5NM_DP_PHY_TX0_TX1_BIST_CFG1 0x080
> +#define DP_V5_5NM_DP_PHY_TX0_TX1_BIST_CFG2 0x084
> +#define DP_V5_5NM_DP_PHY_TX0_TX1_BIST_CFG3 0x088
> +#define DP_V5_5NM_DP_PHY_TX0_TX1_PRBS_SEED_BYTE0 0x08c
> +#define DP_V5_5NM_DP_PHY_TX0_TX1_PRBS_SEED_BYTE1 0x090
> +#define DP_V5_5NM_DP_PHY_TX0_TX1_BIST_PATTERN0 0x094
> +#define DP_V5_5NM_DP_PHY_TX0_TX1_BIST_PATTERN1 0x098
> +#define DP_V5_5NM_DP_PHY_TX2_TX3_LANE_CTL 0x09c
> +#define DP_V5_5NM_DP_PHY_TX2_TX3_BIST_CFG0 0x0a0
> +#define DP_V5_5NM_DP_PHY_TX2_TX3_BIST_CFG1 0x0a4
> +#define DP_V5_5NM_DP_PHY_TX2_TX3_BIST_CFG2 0x0a8
> +#define DP_V5_5NM_DP_PHY_TX2_TX3_BIST_CFG3 0x0ac
> +#define DP_V5_5NM_DP_PHY_TX2_TX3_PRBS_SEED_BYTE0 0x0b0
> +#define DP_V5_5NM_DP_PHY_TX2_TX3_PRBS_SEED_BYTE1 0x0b4
> +#define DP_V5_5NM_DP_PHY_TX2_TX3_BIST_PATTERN0 0x0b8
> +#define DP_V5_5NM_DP_PHY_TX2_TX3_BIST_PATTERN1 0x0bc
> +#define DP_V5_5NM_DP_PHY_MISR_CTRL 0x0c0
> +#define DP_V5_5NM_DP_PHY_DEBUG_BUS_SEL 0x0c4
> +#define DP_V5_5NM_DP_PHY_SPARE0 0x0c8
> +#define DP_V5_5NM_DP_PHY_SPARE1 0x0cc
> +#define DP_V5_5NM_DP_PHY_SPARE2 0x0d0
> +#define DP_V5_5NM_DP_PHY_SPARE3 0x0d4
> +#define DP_V5_5NM_DP_PHY_AUX_INTERRUPT_STATUS 0x0d8
> +#define DP_V5_5NM_DP_PHY_STATUS 0x0dc
> +#define DP_V5_5NM_DP_PHY_AUX_BIST_STATUS0 0x0e0
> +#define DP_V5_5NM_DP_PHY_AUX_BIST_STATUS1 0x0e4
> +#define DP_V5_5NM_DP_PHY_AUX_BIST_STATUS2 0x0e8
> +#define DP_V5_5NM_DP_PHY_TX0_TX1_BIST_STATUS0 0x0ec
> +#define DP_V5_5NM_DP_PHY_TX0_TX1_BIST_STATUS1 0x0f0
> +#define DP_V5_5NM_DP_PHY_TX0_TX1_BIST_STATUS2 0x0f4
> +#define DP_V5_5NM_DP_PHY_TX2_TX3_BIST_STATUS0 0x0f8
> +#define DP_V5_5NM_DP_PHY_TX2_TX3_BIST_STATUS1 0x0fc
> +#define DP_V5_5NM_DP_PHY_TX2_TX3_BIST_STATUS2 0x100
> +#define DP_V5_5NM_DP_PHY_MISR_STATUS 0x104
> +#define DP_V5_5NM_DP_PHY_TX0_MISR_STATUS000 0x108
> +#define DP_V5_5NM_DP_PHY_TX0_MISR_STATUS001 0x10c
> +#define DP_V5_5NM_DP_PHY_TX0_MISR_STATUS010 0x110
> +#define DP_V5_5NM_DP_PHY_TX0_MISR_STATUS011 0x114
> +#define DP_V5_5NM_DP_PHY_TX0_MISR_STATUS100 0x118
> +#define DP_V5_5NM_DP_PHY_TX0_MISR_STATUS101 0x11c
> +#define DP_V5_5NM_DP_PHY_TX0_MISR_STATUS110 0x120
> +#define DP_V5_5NM_DP_PHY_TX0_MISR_STATUS111 0x124
> +#define DP_V5_5NM_DP_PHY_TX1_MISR_STATUS000 0x128
> +#define DP_V5_5NM_DP_PHY_TX1_MISR_STATUS001 0x12c
> +#define DP_V5_5NM_DP_PHY_TX1_MISR_STATUS010 0x130
> +#define DP_V5_5NM_DP_PHY_TX1_MISR_STATUS011 0x134
> +#define DP_V5_5NM_DP_PHY_TX1_MISR_STATUS100 0x138
> +#define DP_V5_5NM_DP_PHY_TX1_MISR_STATUS101 0x13c
> +#define DP_V5_5NM_DP_PHY_TX1_MISR_STATUS110 0x140
> +#define DP_V5_5NM_DP_PHY_TX1_MISR_STATUS111 0x144
> +#define DP_V5_5NM_DP_PHY_TX2_MISR_STATUS000 0x148
> +#define DP_V5_5NM_DP_PHY_TX2_MISR_STATUS001 0x14c
> +#define DP_V5_5NM_DP_PHY_TX2_MISR_STATUS010 0x150
> +#define DP_V5_5NM_DP_PHY_TX2_MISR_STATUS011 0x154
> +#define DP_V5_5NM_DP_PHY_TX2_MISR_STATUS100 0x158
> +#define DP_V5_5NM_DP_PHY_TX2_MISR_STATUS101 0x15c
> +#define DP_V5_5NM_DP_PHY_TX2_MISR_STATUS110 0x160
> +#define DP_V5_5NM_DP_PHY_TX2_MISR_STATUS111 0x164
> +#define DP_V5_5NM_DP_PHY_TX3_MISR_STATUS000 0x168
> +#define DP_V5_5NM_DP_PHY_TX3_MISR_STATUS001 0x16c
> +#define DP_V5_5NM_DP_PHY_TX3_MISR_STATUS010 0x170
> +#define DP_V5_5NM_DP_PHY_TX3_MISR_STATUS011 0x174
> +#define DP_V5_5NM_DP_PHY_TX3_MISR_STATUS100 0x178
> +#define DP_V5_5NM_DP_PHY_TX3_MISR_STATUS101 0x17c
> +#define DP_V5_5NM_DP_PHY_TX3_MISR_STATUS110 0x180
> +#define DP_V5_5NM_DP_PHY_TX3_MISR_STATUS111 0x184
> +#define DP_V5_5NM_DP_PHY_DEBUG_BUS0 0x188
> +#define DP_V5_5NM_DP_PHY_DEBUG_BUS1 0x18c
> +#define DP_V5_5NM_DP_PHY_DEBUG_BUS2 0x190
> +#define DP_V5_5NM_DP_PHY_DEBUG_BUS3 0x194
QSERDES_V4_DP_PHY_ ?
> +
> +/* Module: USB4_QSERDES_PLL_USB4_QSERDES_PLL_USB4_USB3_DP_QMP_PLL_20G */
> +#define USB4_V5_5NM_QSERDES_PLL_ATB_SEL1 0x000
> +#define USB4_V5_5NM_QSERDES_PLL_ATB_SEL2 0x004
> +#define USB4_V5_5NM_QSERDES_PLL_FREQ_UPDATE 0x008
> +#define USB4_V5_5NM_QSERDES_PLL_BG_TIMER 0x00c
> +#define USB4_V5_5NM_QSERDES_PLL_SSC_EN_CENTER 0x010
> +#define USB4_V5_5NM_QSERDES_PLL_SSC_ADJ_PER1 0x014
> +#define USB4_V5_5NM_QSERDES_PLL_SSC_ADJ_PER2 0x018
> +#define USB4_V5_5NM_QSERDES_PLL_SSC_PER1 0x01c
> +#define USB4_V5_5NM_QSERDES_PLL_SSC_PER2 0x020
> +#define USB4_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024
> +#define USB4_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x028
> +#define USB4_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE3_MODE0 0x02c
> +#define USB4_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x030
> +#define USB4_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x034
> +#define USB4_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE3_MODE1 0x038
> +#define USB4_V5_5NM_QSERDES_PLL_POST_DIV 0x03c
> +#define USB4_V5_5NM_QSERDES_PLL_POST_DIV_MUX 0x040
> +#define USB4_V5_5NM_QSERDES_PLL_BIAS_EN_CLKBUFLR_EN 0x044
> +#define USB4_V5_5NM_QSERDES_PLL_CLK_ENABLE1 0x048
> +#define USB4_V5_5NM_QSERDES_PLL_SYS_CLK_CTRL 0x04c
> +#define USB4_V5_5NM_QSERDES_PLL_SYSCLK_BUF_ENABLE 0x050
> +#define USB4_V5_5NM_QSERDES_PLL_PLL_EN 0x054
> +#define USB4_V5_5NM_QSERDES_PLL_PLL_IVCO 0x058
> +#define USB4_V5_5NM_QSERDES_PLL_CMN_IETRIM 0x05c
> +#define USB4_V5_5NM_QSERDES_PLL_CMN_IPTRIM 0x060
> +#define USB4_V5_5NM_QSERDES_PLL_EP_CLOCK_DETECT_CTRL 0x064
> +#define USB4_V5_5NM_QSERDES_PLL_SYSCLK_DET_COMP_STATUS 0x068
> +#define USB4_V5_5NM_QSERDES_PLL_CLK_EP_DIV_MODE0 0x06c
> +#define USB4_V5_5NM_QSERDES_PLL_CLK_EP_DIV_MODE1 0x070
> +#define USB4_V5_5NM_QSERDES_PLL_CP_CTRL_MODE0 0x074
> +#define USB4_V5_5NM_QSERDES_PLL_CP_CTRL_MODE1 0x078
> +#define USB4_V5_5NM_QSERDES_PLL_PLL_RCTRL_MODE0 0x07c
> +#define USB4_V5_5NM_QSERDES_PLL_PLL_RCTRL_MODE1 0x080
> +#define USB4_V5_5NM_QSERDES_PLL_PLL_CCTRL_MODE0 0x084
> +#define USB4_V5_5NM_QSERDES_PLL_PLL_CCTRL_MODE1 0x088
> +#define USB4_V5_5NM_QSERDES_PLL_PLL_CNTRL 0x08c
> +#define USB4_V5_5NM_QSERDES_PLL_BIAS_EN_CTRL_BY_PSM 0x090
> +#define USB4_V5_5NM_QSERDES_PLL_SYSCLK_EN_SEL 0x094
> +#define USB4_V5_5NM_QSERDES_PLL_CML_SYSCLK_SEL 0x098
> +#define USB4_V5_5NM_QSERDES_PLL_RESETSM_CNTRL 0x09c
> +#define USB4_V5_5NM_QSERDES_PLL_RESETSM_CNTRL2 0x0a0
> +#define USB4_V5_5NM_QSERDES_PLL_LOCK_CMP_EN 0x0a4
> +#define USB4_V5_5NM_QSERDES_PLL_LOCK_CMP_CFG 0x0a8
> +#define USB4_V5_5NM_QSERDES_PLL_LOCK_CMP1_MODE0 0x0ac
> +#define USB4_V5_5NM_QSERDES_PLL_LOCK_CMP2_MODE0 0x0b0
> +#define USB4_V5_5NM_QSERDES_PLL_LOCK_CMP1_MODE1 0x0b4
> +#define USB4_V5_5NM_QSERDES_PLL_LOCK_CMP2_MODE1 0x0b8
> +#define USB4_V5_5NM_QSERDES_PLL_DEC_START_MODE0 0x0bc
> +#define USB4_V5_5NM_QSERDES_PLL_DEC_START_MSB_MODE0 0x0c0
> +#define USB4_V5_5NM_QSERDES_PLL_DEC_START_MODE1 0x0c4
> +#define USB4_V5_5NM_QSERDES_PLL_DEC_START_MSB_MODE1 0x0c8
> +#define USB4_V5_5NM_QSERDES_PLL_DIV_FRAC_START1_MODE0 0x0cc
> +#define USB4_V5_5NM_QSERDES_PLL_DIV_FRAC_START2_MODE0 0x0d0
> +#define USB4_V5_5NM_QSERDES_PLL_DIV_FRAC_START3_MODE0 0x0d4
> +#define USB4_V5_5NM_QSERDES_PLL_DIV_FRAC_START1_MODE1 0x0d8
> +#define USB4_V5_5NM_QSERDES_PLL_DIV_FRAC_START2_MODE1 0x0dc
> +#define USB4_V5_5NM_QSERDES_PLL_DIV_FRAC_START3_MODE1 0x0e0
> +#define USB4_V5_5NM_QSERDES_PLL_INTEGLOOP_INITVAL 0x0e4
> +#define USB4_V5_5NM_QSERDES_PLL_INTEGLOOP_EN 0x0e8
> +#define USB4_V5_5NM_QSERDES_PLL_INTEGLOOP_GAIN0_MODE0 0x0ec
> +#define USB4_V5_5NM_QSERDES_PLL_INTEGLOOP_GAIN1_MODE0 0x0f0
> +#define USB4_V5_5NM_QSERDES_PLL_INTEGLOOP_GAIN0_MODE1 0x0f4
> +#define USB4_V5_5NM_QSERDES_PLL_INTEGLOOP_GAIN1_MODE1 0x0f8
> +#define USB4_V5_5NM_QSERDES_PLL_INTEGLOOP_P_PATH_GAIN0 0x0fc
> +#define USB4_V5_5NM_QSERDES_PLL_INTEGLOOP_P_PATH_GAIN1 0x100
> +#define USB4_V5_5NM_QSERDES_PLL_VCOCAL_DEADMAN_CTRL 0x104
> +#define USB4_V5_5NM_QSERDES_PLL_VCO_TUNE_CTRL 0x108
> +#define USB4_V5_5NM_QSERDES_PLL_VCO_TUNE_MAP 0x10c
> +#define USB4_V5_5NM_QSERDES_PLL_VCO_TUNE1_MODE0 0x110
> +#define USB4_V5_5NM_QSERDES_PLL_VCO_TUNE2_MODE0 0x114
> +#define USB4_V5_5NM_QSERDES_PLL_VCO_TUNE1_MODE1 0x118
> +#define USB4_V5_5NM_QSERDES_PLL_VCO_TUNE2_MODE1 0x11c
> +#define USB4_V5_5NM_QSERDES_PLL_VCO_TUNE_INITVAL1 0x120
> +#define USB4_V5_5NM_QSERDES_PLL_VCO_TUNE_INITVAL2 0x124
> +#define USB4_V5_5NM_QSERDES_PLL_VCO_TUNE_MINVAL1 0x128
> +#define USB4_V5_5NM_QSERDES_PLL_VCO_TUNE_MINVAL2 0x12c
> +#define USB4_V5_5NM_QSERDES_PLL_VCO_TUNE_MAXVAL1 0x130
> +#define USB4_V5_5NM_QSERDES_PLL_VCO_TUNE_MAXVAL2 0x134
> +#define USB4_V5_5NM_QSERDES_PLL_VCO_TUNE_TIMER1 0x138
> +#define USB4_V5_5NM_QSERDES_PLL_VCO_TUNE_TIMER2 0x13c
> +#define USB4_V5_5NM_QSERDES_PLL_CMN_STATUS 0x140
> +#define USB4_V5_5NM_QSERDES_PLL_RESET_SM_STATUS 0x144
> +#define USB4_V5_5NM_QSERDES_PLL_RESTRIM_CODE_STATUS 0x148
> +#define USB4_V5_5NM_QSERDES_PLL_PLLCAL_CODE1_STATUS 0x14c
> +#define USB4_V5_5NM_QSERDES_PLL_PLLCAL_CODE2_STATUS 0x150
> +#define USB4_V5_5NM_QSERDES_PLL_CLK_SELECT 0x154
> +#define USB4_V5_5NM_QSERDES_PLL_HSCLK_SEL 0x158
> +#define USB4_V5_5NM_QSERDES_PLL_HSCLK_HS_SWITCH_SEL 0x15c
> +#define USB4_V5_5NM_QSERDES_PLL_INTEGLOOP_BINCODE_STATUS 0x160
> +#define USB4_V5_5NM_QSERDES_PLL_PLL_ANALOG 0x164
> +#define USB4_V5_5NM_QSERDES_PLL_CORECLK_DIV_MODE0 0x168
> +#define USB4_V5_5NM_QSERDES_PLL_CORECLK_DIV_MODE1 0x16c
> +#define USB4_V5_5NM_QSERDES_PLL_SW_RESET 0x170
> +#define USB4_V5_5NM_QSERDES_PLL_CORE_CLK_EN 0x174
> +#define USB4_V5_5NM_QSERDES_PLL_C_READY_STATUS 0x178
> +#define USB4_V5_5NM_QSERDES_PLL_CMN_CONFIG 0x17c
> +#define USB4_V5_5NM_QSERDES_PLL_CMN_RATE_OVERRIDE 0x180
> +#define USB4_V5_5NM_QSERDES_PLL_SVS_MODE_CLK_SEL 0x184
> +#define USB4_V5_5NM_QSERDES_PLL_DEBUG_BUS0 0x188
> +#define USB4_V5_5NM_QSERDES_PLL_DEBUG_BUS1 0x18c
> +#define USB4_V5_5NM_QSERDES_PLL_DEBUG_BUS2 0x190
> +#define USB4_V5_5NM_QSERDES_PLL_DEBUG_BUS3 0x194
> +#define USB4_V5_5NM_QSERDES_PLL_DEBUG_BUS_SEL 0x198
> +#define USB4_V5_5NM_QSERDES_PLL_CMN_MISC1 0x19c
> +#define USB4_V5_5NM_QSERDES_PLL_CMN_MODE 0x1a0
> +#define USB4_V5_5NM_QSERDES_PLL_CMN_MODE_CONTD 0x1a4
> +#define USB4_V5_5NM_QSERDES_PLL_VCO_DC_LEVEL_CTRL 0x1a8
> +#define USB4_V5_5NM_QSERDES_PLL_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac
> +#define USB4_V5_5NM_QSERDES_PLL_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0
> +#define USB4_V5_5NM_QSERDES_PLL_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4
> +#define USB4_V5_5NM_QSERDES_PLL_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8
> +#define USB4_V5_5NM_QSERDES_PLL_BIN_VCOCAL_HSCLK_SEL 0x1bc
> +#define USB4_V5_5NM_QSERDES_PLL_ADDITIONAL_CTRL_1 0x1c0
> +#define USB4_V5_5NM_QSERDES_PLL_MODE_OPERATION_STATUS 0x1c4
> +#define USB4_V5_5NM_QSERDES_PLL_AUTO_GAIN_ADJ_CTRL_1 0x1c8
> +#define USB4_V5_5NM_QSERDES_PLL_AUTO_GAIN_ADJ_CTRL_2 0x1cc
> +#define USB4_V5_5NM_QSERDES_PLL_AUTO_GAIN_ADJ_CTRL_3 0x1d0
> +#define USB4_V5_5NM_QSERDES_PLL_AUTO_GAIN_ADJ_CTRL_4 0x1d4
> +#define USB4_V5_5NM_QSERDES_PLL_ADDITIONAL_MISC 0x1d8
> +#define USB4_V5_5NM_QSERDES_PLL_ADDITIONAL_MISC_2 0x1dc
> +#define USB4_V5_5NM_QSERDES_PLL_ADDITIONAL_MISC_3 0x1e0
And mode QSERDES_V5_COM_
> +
> +/* Module: USB4_PCS_L0_USB4_PCS_L0_USB4_PCS_LANE */
> +#define USB4_V5_5NM_PCS_L0_PCS_STATUS1 0x00
> +#define USB4_V5_5NM_PCS_L0_PCS_STATUS2 0x04
> +#define USB4_V5_5NM_PCS_L0_PCS_STATUS3 0x08
> +#define USB4_V5_5NM_PCS_L0_BIST_CHK_ERR_CNT_L_STATUS 0x0c
> +#define USB4_V5_5NM_PCS_L0_BIST_CHK_ERR_CNT_H_STATUS 0x10
> +#define USB4_V5_5NM_PCS_L0_BIST_CHK_STATUS 0x14
> +#define USB4_V5_5NM_PCS_L0_INSIG_SW_CTRL1 0x18
> +#define USB4_V5_5NM_PCS_L0_INSIG_SW_CTRL2 0x1c
> +#define USB4_V5_5NM_PCS_L0_INSIG_MX_CTRL1 0x20
> +#define USB4_V5_5NM_PCS_L0_INSIG_MX_CTRL2 0x24
> +#define USB4_V5_5NM_PCS_L0_OUTSIG_SW_CTRL1 0x28
> +#define USB4_V5_5NM_PCS_L0_OUTSIG_SW_CTRL2 0x2c
> +#define USB4_V5_5NM_PCS_L0_OUTSIG_MX_CTRL1 0x30
> +#define USB4_V5_5NM_PCS_L0_OUTSIG_MX_CTRL2 0x34
> +#define USB4_V5_5NM_PCS_L0_PRESET_OVERRIDE_CONFIG 0x38
> +#define USB4_V5_5NM_PCS_L0_TEST_CONTROL1 0x3c
> +#define USB4_V5_5NM_PCS_L0_TEST_CONTROL2 0x40
> +#define USB4_V5_5NM_PCS_L0_TEST_CONTROL3 0x44
> +#define USB4_V5_5NM_PCS_L0_BIST_CTRL 0x48
> +#define USB4_V5_5NM_PCS_L0_PRBS_SEED0 0x4c
> +#define USB4_V5_5NM_PCS_L0_PRBS_SEED1 0x50
> +#define USB4_V5_5NM_PCS_L0_LANE_OFF_CONFIG 0x54
> +#define USB4_V5_5NM_PCS_L0_RXEQ_STATUS1 0x58
> +#define USB4_V5_5NM_PCS_L0_RXEQ_STATUS2 0x5c
> +#define USB4_V5_5NM_PCS_L0_RX_MARGINING_CTRL1 0x60
> +#define USB4_V5_5NM_PCS_L0_RX_MARGINING_STATUS1 0x64
> +#define USB4_V5_5NM_PCS_L0_RX_MARGINING_STATUS2 0x68
> +
> +/* Module: USB4_PCS_L1_USB4_PCS_L1_USB4_PCS_LANE */
> +#define USB4_V5_5NM_PCS_L1_PCS_STATUS1 0x00
> +#define USB4_V5_5NM_PCS_L1_PCS_STATUS2 0x04
> +#define USB4_V5_5NM_PCS_L1_PCS_STATUS3 0x08
> +#define USB4_V5_5NM_PCS_L1_BIST_CHK_ERR_CNT_L_STATUS 0x0c
> +#define USB4_V5_5NM_PCS_L1_BIST_CHK_ERR_CNT_H_STATUS 0x10
> +#define USB4_V5_5NM_PCS_L1_BIST_CHK_STATUS 0x14
> +#define USB4_V5_5NM_PCS_L1_INSIG_SW_CTRL1 0x18
> +#define USB4_V5_5NM_PCS_L1_INSIG_SW_CTRL2 0x1c
> +#define USB4_V5_5NM_PCS_L1_INSIG_MX_CTRL1 0x20
> +#define USB4_V5_5NM_PCS_L1_INSIG_MX_CTRL2 0x24
> +#define USB4_V5_5NM_PCS_L1_OUTSIG_SW_CTRL1 0x28
> +#define USB4_V5_5NM_PCS_L1_OUTSIG_SW_CTRL2 0x2c
> +#define USB4_V5_5NM_PCS_L1_OUTSIG_MX_CTRL1 0x30
> +#define USB4_V5_5NM_PCS_L1_OUTSIG_MX_CTRL2 0x34
> +#define USB4_V5_5NM_PCS_L1_PRESET_OVERRIDE_CONFIG 0x38
> +#define USB4_V5_5NM_PCS_L1_TEST_CONTROL1 0x3c
> +#define USB4_V5_5NM_PCS_L1_TEST_CONTROL2 0x40
> +#define USB4_V5_5NM_PCS_L1_TEST_CONTROL3 0x44
> +#define USB4_V5_5NM_PCS_L1_BIST_CTRL 0x48
> +#define USB4_V5_5NM_PCS_L1_PRBS_SEED0 0x4c
> +#define USB4_V5_5NM_PCS_L1_PRBS_SEED1 0x50
> +#define USB4_V5_5NM_PCS_L1_LANE_OFF_CONFIG 0x54
> +#define USB4_V5_5NM_PCS_L1_RXEQ_STATUS1 0x58
> +#define USB4_V5_5NM_PCS_L1_RXEQ_STATUS2 0x5c
> +#define USB4_V5_5NM_PCS_L1_RX_MARGINING_CTRL1 0x60
> +#define USB4_V5_5NM_PCS_L1_RX_MARGINING_STATUS1 0x64
> +#define USB4_V5_5NM_PCS_L1_RX_MARGINING_STATUS2 0x68
> +
> +/* Module: USB4_PCS_USB4_PCS_USB4_PCS */
> +#define USB4_V5_5NM_PCS_SW_RESET 0x000
> +#define USB4_V5_5NM_PCS_REVISION_ID0 0x004
> +#define USB4_V5_5NM_PCS_REVISION_ID1 0x008
> +#define USB4_V5_5NM_PCS_REVISION_ID2 0x00c
> +#define USB4_V5_5NM_PCS_REVISION_ID3 0x010
> +#define USB4_V5_5NM_PCS_PCS_STATUS1 0x014
> +#define USB4_V5_5NM_PCS_PCS_STATUS2 0x018
> +#define USB4_V5_5NM_PCS_PCS_STATUS3 0x01c
> +#define USB4_V5_5NM_PCS_PCS_STATUS4 0x020
> +#define USB4_V5_5NM_PCS_PCS_STATUS5 0x024
> +#define USB4_V5_5NM_PCS_PCS_STATUS6 0x028
> +#define USB4_V5_5NM_PCS_PCS_STATUS7 0x02c
> +#define USB4_V5_5NM_PCS_DEBUG_BUS_0_STATUS 0x030
> +#define USB4_V5_5NM_PCS_DEBUG_BUS_1_STATUS 0x034
> +#define USB4_V5_5NM_PCS_DEBUG_BUS_2_STATUS 0x038
> +#define USB4_V5_5NM_PCS_DEBUG_BUS_3_STATUS 0x03c
> +#define USB4_V5_5NM_PCS_POWER_DOWN_CONTROL 0x040
> +#define USB4_V5_5NM_PCS_START_CONTROL 0x044
> +#define USB4_V5_5NM_PCS_INSIG_SW_CTRL1 0x048
> +#define USB4_V5_5NM_PCS_INSIG_SW_CTRL2 0x04c
> +#define USB4_V5_5NM_PCS_INSIG_SW_CTRL3 0x050
> +#define USB4_V5_5NM_PCS_INSIG_SW_CTRL4 0x054
> +#define USB4_V5_5NM_PCS_INSIG_SW_CTRL5 0x058
> +#define USB4_V5_5NM_PCS_INSIG_SW_CTRL6 0x05c
> +#define USB4_V5_5NM_PCS_INSIG_SW_CTRL7 0x060
> +#define USB4_V5_5NM_PCS_INSIG_SW_CTRL8 0x064
> +#define USB4_V5_5NM_PCS_INSIG_MX_CTRL1 0x068
> +#define USB4_V5_5NM_PCS_INSIG_MX_CTRL2 0x06c
> +#define USB4_V5_5NM_PCS_INSIG_MX_CTRL3 0x070
> +#define USB4_V5_5NM_PCS_INSIG_MX_CTRL4 0x074
> +#define USB4_V5_5NM_PCS_INSIG_MX_CTRL5 0x078
> +#define USB4_V5_5NM_PCS_INSIG_MX_CTRL8 0x07c
> +#define USB4_V5_5NM_PCS_OUTSIG_SW_CTRL1 0x080
> +#define USB4_V5_5NM_PCS_OUTSIG_MX_CTRL1 0x084
> +#define USB4_V5_5NM_PCS_OUTSIG_SW_CTRL2 0x088
> +#define USB4_V5_5NM_PCS_OUTSIG_MX_CTRL2 0x08c
> +#define USB4_V5_5NM_PCS_POWER_STATE_CONFIG1 0x090
> +#define USB4_V5_5NM_PCS_POWER_STATE_CONFIG2 0x094
> +#define USB4_V5_5NM_PCS_POWER_STATE_CONFIG3 0x098
> +#define USB4_V5_5NM_PCS_POWER_STATE_CONFIG4 0x09c
> +#define USB4_V5_5NM_PCS_FLL_CNTRL1 0x0a0
> +#define USB4_V5_5NM_PCS_FLL_CNTRL2 0x0a4
> +#define USB4_V5_5NM_PCS_FLL_CNT_VAL_L 0x0a8
> +#define USB4_V5_5NM_PCS_FLL_CNT_VAL_H_TOL 0x0ac
> +#define USB4_V5_5NM_PCS_FLL_MAN_CODE 0x0b0
> +#define USB4_V5_5NM_PCS_TEST_CONTROL1 0x0b4
> +#define USB4_V5_5NM_PCS_TEST_CONTROL2 0x0b8
> +#define USB4_V5_5NM_PCS_TEST_CONTROL3 0x0bc
> +#define USB4_V5_5NM_PCS_TEST_CONTROL4 0x0c0
> +#define USB4_V5_5NM_PCS_TEST_CONTROL5 0x0c4
> +#define USB4_V5_5NM_PCS_TEST_CONTROL6 0x0c8
> +#define USB4_V5_5NM_PCS_TEST_CONTROL7 0x0cc
> +#define USB4_V5_5NM_PCS_LOCK_DETECT_CONFIG1 0x0d0
> +#define USB4_V5_5NM_PCS_LOCK_DETECT_CONFIG2 0x0d4
> +#define USB4_V5_5NM_PCS_REFGEN_REQ_CONFIG1 0x0d8
> +#define USB4_V5_5NM_PCS_REFGEN_REQ_CONFIG2 0x0dc
> +#define USB4_V5_5NM_PCS_REFGEN_REQ_CONFIG3 0x0e0
> +#define USB4_V5_5NM_PCS_BIST_CTRL 0x0e4
> +#define USB4_V5_5NM_PCS_BIST_CONFIG1 0x0e8
> +#define USB4_V5_5NM_PCS_BIST_CONFIG2 0x0ec
> +#define USB4_V5_5NM_PCS_BIST_CONFIG3 0x0f0
> +#define USB4_V5_5NM_PCS_TXMGN_CONFIG 0x0f4
> +#define USB4_V5_5NM_PCS_G3_TXMGN_MAIN 0x0f8
> +#define USB4_V5_5NM_PCS_G3_TXMGN_MAIN_RS 0x0fc
> +#define USB4_V5_5NM_PCS_G3_PRE_GAIN 0x100
> +#define USB4_V5_5NM_PCS_G3_POST_GAIN 0x104
> +#define USB4_V5_5NM_PCS_G3_PRE_POST_OFFSET 0x108
> +#define USB4_V5_5NM_PCS_G3_PRE_GAIN_RS 0x10c
> +#define USB4_V5_5NM_PCS_G3_POST_GAIN_RS 0x110
> +#define USB4_V5_5NM_PCS_G3_PRE_POST_OFFSET_RS 0x114
> +#define USB4_V5_5NM_PCS_G2_TXMGN_MAIN 0x118
> +#define USB4_V5_5NM_PCS_G2_TXMGN_MAIN_RS 0x11c
> +#define USB4_V5_5NM_PCS_G2_PRE_GAIN 0x120
> +#define USB4_V5_5NM_PCS_G2_POST_GAIN 0x124
> +#define USB4_V5_5NM_PCS_G2_PRE_POST_OFFSET 0x128
> +#define USB4_V5_5NM_PCS_G2_PRE_GAIN_RS 0x12c
> +#define USB4_V5_5NM_PCS_G2_POST_GAIN_RS 0x130
> +#define USB4_V5_5NM_PCS_G2_PRE_POST_OFFSET_RS 0x134
> +#define USB4_V5_5NM_PCS_TXCOEFF_CONFIG 0x138
> +#define USB4_V5_5NM_PCS_PRESET_P0_P1_PRE 0x13c
> +#define USB4_V5_5NM_PCS_PRESET_P2_P3_PRE 0x140
> +#define USB4_V5_5NM_PCS_PRESET_P4_P5_PRE 0x144
> +#define USB4_V5_5NM_PCS_PRESET_P6_P7_PRE 0x148
> +#define USB4_V5_5NM_PCS_PRESET_P8_P9_PRE 0x14c
> +#define USB4_V5_5NM_PCS_PRESET_P10_P11_PRE 0x150
> +#define USB4_V5_5NM_PCS_PRESET_P12_P13_PRE 0x154
> +#define USB4_V5_5NM_PCS_PRESET_P14_P15_PRE 0x158
> +#define USB4_V5_5NM_PCS_PRESET_P0_P1_POST 0x15c
> +#define USB4_V5_5NM_PCS_PRESET_P2_P3_POST 0x160
> +#define USB4_V5_5NM_PCS_PRESET_P4_P5_POST 0x164
> +#define USB4_V5_5NM_PCS_PRESET_P6_P7_POST 0x168
> +#define USB4_V5_5NM_PCS_PRESET_P8_P9_POST 0x16c
> +#define USB4_V5_5NM_PCS_PRESET_P10_P11_POST 0x170
> +#define USB4_V5_5NM_PCS_PRESET_P12_P13_POST 0x174
> +#define USB4_V5_5NM_PCS_PRESET_P14_P15_POST 0x178
> +#define USB4_V5_5NM_PCS_RX_SIGDET_LVL 0x17c
> +#define USB4_V5_5NM_PCS_RX_SIGDET_DTCT_CNTRL 0x180
> +#define USB4_V5_5NM_PCS_RATE_SLEW_CNTRL 0x184
> +#define USB4_V5_5NM_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x188
> +#define USB4_V5_5NM_PCS_C3_WAKEUP_DLY_TIME_AUXCLK_L 0x18c
> +#define USB4_V5_5NM_PCS_C3_WAKEUP_DLY_TIME_AUXCLK_H 0x190
> +#define USB4_V5_5NM_PCS_TSYNC_RSYNC_TIME 0x194
> +#define USB4_V5_5NM_PCS_CDR_RESET_TIME 0x198
> +#define USB4_V5_5NM_PCS_TSYNC_DLY_TIME 0x19c
> +#define USB4_V5_5NM_PCS_ELECIDLE_DLY_SEL 0x1a0
> +#define USB4_V5_5NM_PCS_CMN_ACK_OUT_SEL 0x1a4
> +#define USB4_V5_5NM_PCS_PCS_TX_RX_CONFIG1 0x1a8
> +#define USB4_V5_5NM_PCS_PCS_TX_RX_CONFIG2 0x1ac
> +#define USB4_V5_5NM_PCS_PCS_TX_RX_CONFIG3 0x1b0
> +#define USB4_V5_5NM_PCS_RX_DCC_CAL_CONFIG 0x1b4
> +#define USB4_V5_5NM_PCS_EQ_CONFIG1 0x1b8
> +#define USB4_V5_5NM_PCS_EQ_CONFIG2 0x1bc
> +#define USB4_V5_5NM_PCS_G2_EQ_CONFIG1 0x1c0
> +#define USB4_V5_5NM_PCS_G2_EQ_CONFIG2 0x1c4
> +#define USB4_V5_5NM_PCS_G2_EQ_CONFIG3 0x1c8
> +#define USB4_V5_5NM_PCS_G2_EQ_CONFIG4 0x1cc
> +#define USB4_V5_5NM_PCS_G2_EQ_CONFIG5 0x1d0
> +#define USB4_V5_5NM_PCS_G2_EQ_CONFIG6 0x1d4
> +#define USB4_V5_5NM_PCS_G3_EQ_CONFIG1 0x1d8
> +#define USB4_V5_5NM_PCS_G3_EQ_CONFIG2 0x1dc
> +#define USB4_V5_5NM_PCS_G3_EQ_CONFIG3 0x1e0
> +#define USB4_V5_5NM_PCS_G3_EQ_CONFIG4 0x1e4
> +#define USB4_V5_5NM_PCS_G3_EQ_CONFIG5 0x1e8
> +#define USB4_V5_5NM_PCS_G3_EQ_CONFIG6 0x1ec
> +#define USB4_V5_5NM_PCS_FOM_EQ_CONFIG1 0x1f0
> +#define USB4_V5_5NM_PCS_FOM_EQ_CONFIG2 0x1f4
> +#define USB4_V5_5NM_PCS_FOM_EQ_CONFIG3 0x1f8
> +#define USB4_V5_5NM_PCS_FOM_EQ_CONFIG4 0x1fc
> +#define USB4_V5_5NM_PCS_LFPS_DET_HIGH_COUNT_VAL 0x200
> +#define USB4_V5_5NM_PCS_LFPS_TX_ECSTART 0x204
> +#define USB4_V5_5NM_PCS_LFPS_TX_END_CNT_C3_START 0x208
> +#define USB4_V5_5NM_PCS_MBUS_CONFIG1 0x20c
> +#define USB4_V5_5NM_PCS_MBUS_CTRL1 0x210
> +#define USB4_V5_5NM_PCS_MBUS_CTRL2 0x214
> +#define USB4_V5_5NM_PCS_MBUS_CTRL3 0x218
> +#define USB4_V5_5NM_PCS_MBUS_CTRL4 0x21c
> +#define USB4_V5_5NM_PCS_MBUS_STATUS1 0x220
> +#define USB4_V5_5NM_PCS_RX_MARGINING_CONFIG1 0x224
> +#define USB4_V5_5NM_PCS_RX_MARGINING_CONFIG2 0x228
> +#define USB4_V5_5NM_PCS_RX_MARGINING_CONFIG3 0x22c
> +#define USB4_V5_5NM_PCS_WAKEUP_CLK_CONFIG1 0x230
> +#define USB4_V5_5NM_PCS_WAKEUP_CLK_CONFIG2 0x234
> +#define USB4_V5_5NM_PCS_WAKEUP_CLK_STATUS 0x238
> +#define USB4_V5_5NM_PCS_TX_LATENCY_MEAS_CONFIG1 0x23c
> +#define USB4_V5_5NM_PCS_TX_LATENCY_MEAS_CONFIG2 0x240
> +#define USB4_V5_5NM_PCS_TX_LATENCY_STATUS 0x244
> +#define USB4_V5_5NM_PCS_SIGDET_CNTRL 0x248
> +
> +#endif
> +
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 3/5] phy: qcom-qmp: Add USB4 5NM QMP combo PHY registers
2022-06-07 22:24 ` Dmitry Baryshkov
@ 2022-06-07 23:04 ` Bjorn Andersson
2022-06-07 23:28 ` Dmitry Baryshkov
2022-06-07 23:52 ` Dmitry Baryshkov
0 siblings, 2 replies; 16+ messages in thread
From: Bjorn Andersson @ 2022-06-07 23:04 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Kishon Vijay Abraham I, Vinod Koul, Manu Gautam, Rob Herring,
Krzysztof Kozlowski, linux-arm-msm, linux-phy, devicetree,
linux-kernel
On Tue 07 Jun 15:24 PDT 2022, Dmitry Baryshkov wrote:
> On 08/06/2022 00:35, Bjorn Andersson wrote:
> > Add all registers defines from qcom,usb4-5nm-qmp-combo.h of the msm-5.4
> > kernel. Offsets are adjusted to be relative to each sub-block, as we
> > describe the individual pieces in the upstream kernel and "v5_5NM" are
> > injected in the defines to not collide with existing constants.
> >
> > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> > ---
> >
> > Changes since v1:
> > - New patch
> >
> > .../qualcomm/phy-qcom-usb4-5nm-qmp-combo.h | 1547 +++++++++++++++++
> > 1 file changed, 1547 insertions(+)
> > create mode 100644 drivers/phy/qualcomm/phy-qcom-usb4-5nm-qmp-combo.h
> >
> > diff --git a/drivers/phy/qualcomm/phy-qcom-usb4-5nm-qmp-combo.h b/drivers/phy/qualcomm/phy-qcom-usb4-5nm-qmp-combo.h
> > new file mode 100644
> > index 000000000000..7be8a50269ec
> > --- /dev/null
> > +++ b/drivers/phy/qualcomm/phy-qcom-usb4-5nm-qmp-combo.h
> > @@ -0,0 +1,1547 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Copyright (c) 2021, The Linux Foundation. All rights reserved.
> > + */
> > +
> > +#ifndef PHY_QCOM_V5_5NM_QMP_COMBO_USB4_H
> > +#define PHY_QCOM_V5_5NM_QMP_COMBO_USB4_H
> > +
> > +/* USB4-USB3-DP Combo PHY register offsets */
> > +/* Module: USB43DP_COM_USB43DP_COM_USB4_USB3_DP_COM */
> > +#define USB43DP_V5_5NM_COM_PHY_MODE_CTRL 0x00
> > +#define USB43DP_V5_5NM_COM_SW_RESET 0x04
> > +#define USB43DP_V5_5NM_COM_POWER_DOWN_CTRL 0x08
> > +#define USB43DP_V5_5NM_COM_SWI_CTRL 0x0c
> > +#define USB43DP_V5_5NM_COM_TYPEC_CTRL 0x10
> > +#define USB43DP_V5_5NM_COM_TYPEC_PWRDN_CTRL 0x14
> > +#define USB43DP_V5_5NM_COM_DP_BIST_CFG_0 0x18
> > +#define USB43DP_V5_5NM_COM_RESET_OVRD_CTRL1 0x1c
> > +#define USB43DP_V5_5NM_COM_RESET_OVRD_CTRL2 0x20
> > +#define USB43DP_V5_5NM_COM_DBG_CLK_MUX_CTRL 0x24
> > +#define USB43DP_V5_5NM_COM_TYPEC_STATUS 0x28
> > +#define USB43DP_V5_5NM_COM_PLACEHOLDER_STATUS 0x2c
> > +#define USB43DP_V5_5NM_COM_REVISION_ID0 0x30
> > +#define USB43DP_V5_5NM_COM_REVISION_ID1 0x34
> > +#define USB43DP_V5_5NM_COM_REVISION_ID2 0x38
> > +#define USB43DP_V5_5NM_COM_REVISION_ID3 0x3c
>
> QPHY_V5_DP_COM_foo ?
>
My first version of the QMP patch used V5 defines and USB worked
sometimes. So I hacked up a thing to dump the phy sequences of the
downstream and upstream kernels, compared the magic numbers and then
tried to fit suitable constants.
But it obviously was a waste of time and I would have to make up a
different naming scheme for the ones that doesn't match the existing
constants - when we could just use the autogenerated files that exist in
the downstream kernels.
[..]
> > +#define USB43DP_V5_5NM_QSERDES_TXA_DEBUG_BUS1 0xf0
> > +#define USB43DP_V5_5NM_QSERDES_TXA_DEBUG_BUS2 0xf4
> > +#define USB43DP_V5_5NM_QSERDES_TXA_DEBUG_BUS3 0xf8
> > +#define USB43DP_V5_5NM_QSERDES_TXA_TX_BKUP_RO_BUS 0xfc
>
> QSERDES_V5_20_TX_foo ? This looks compatible with the 4 registers that we
> have in the header, but I can not verify the rest of registers
>
Exactly the point I was making in my reply to the other patch.
Per the documentation this is version 5.0.0, but these register offsets
happens to match the 5.20 defines that we have...
> > +
> > +/* Module: USB43DP_QSERDES_RXA_USB43DP_QSERDES_RXA_USB4_USB3_DP_QMP_RX */
[..]
> > +#define USB43DP_V5_5NM_QSERDES_RXA_RX_BKUP_READ_BUS3_STATUS 0x3e8
And these, doesn't match either V5 or V5_20.
[..]
> > +#define USB43DP_V5_5NM_QSERDES_TXB_TX_BKUP_RO_BUS 0xfc
>
> What is the difference between _TXA_ and _TXB_ ?
>
Nothing, I just don't want us to mess around with these files if we can
get them dumped from the register documentation.
> > +
[..]
> > +
> > +/* Module: USB3_PCS_MISC_USB3_PCS_MISC_USB3_PCS_MISC */
> > +#define USB3_V5_5NM_PCS_MISC_TYPEC_CTRL 0x00
> > +#define USB3_V5_5NM_PCS_MISC_TYPEC_PWRDN_CTRL 0x04
> > +#define USB3_V5_5NM_PCS_MISC_PCS_MISC_CONFIG1 0x08
> > +#define USB3_V5_5NM_PCS_MISC_CLAMP_ENABLE 0x0c
> > +#define USB3_V5_5NM_PCS_MISC_TYPEC_STATUS 0x10
> > +#define USB3_V5_5NM_PCS_MISC_PLACEHOLDER_STATUS 0x14
>
> QPHY_V4_PCS_MISC (or v5)
>
Perhaps, but then we're just making up those prefixes and hoping for the
best.
[..]
> > +#define USB3_V5_5NM_PCS_EQ_CONFIG2 0x1e0
> > +#define USB3_V5_5NM_PCS_EQ_CONFIG3 0x1e4
> > +#define USB3_V5_5NM_PCS_EQ_CONFIG4 0x1E8
> > +#define USB3_V5_5NM_PCS_EQ_CONFIG5 0x1EC
>
> This looks like both QPHY_V4_PCS and QPHY_V5_PCS. Most probably we should
> merge them together and add these defines.
>
Exactly, all these defines looks like defines we already have and if you
pick the wrong one you end up with things not working - or in my case
something that worked sometimes.
> > +
> > +/* Module: USB3_PCS_USB3_USB3_PCS_USB3_USB3_PCS_USB3 */
[..]
> > +#define USB3_V5_5NM_PCS_USB3_RXTERMINATION_DLY_SEL 0x60
>
> Again, QPHY_V5_PCS_USB w/o the 0x300 offset
>
Yeah, that extra region needs to be added to the binding and driver.
Regards,
Bjorn
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 3/5] phy: qcom-qmp: Add USB4 5NM QMP combo PHY registers
2022-06-07 23:04 ` Bjorn Andersson
@ 2022-06-07 23:28 ` Dmitry Baryshkov
2022-06-07 23:52 ` Dmitry Baryshkov
1 sibling, 0 replies; 16+ messages in thread
From: Dmitry Baryshkov @ 2022-06-07 23:28 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Kishon Vijay Abraham I, Vinod Koul, Manu Gautam, Rob Herring,
Krzysztof Kozlowski, linux-arm-msm, linux-phy, devicetree,
linux-kernel
On Wed, 8 Jun 2022 at 02:02, Bjorn Andersson <bjorn.andersson@linaro.org> wrote:
>
> On Tue 07 Jun 15:24 PDT 2022, Dmitry Baryshkov wrote:
>
> > On 08/06/2022 00:35, Bjorn Andersson wrote:
> > > Add all registers defines from qcom,usb4-5nm-qmp-combo.h of the msm-5.4
> > > kernel. Offsets are adjusted to be relative to each sub-block, as we
> > > describe the individual pieces in the upstream kernel and "v5_5NM" are
> > > injected in the defines to not collide with existing constants.
> > >
> > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> > > ---
> > >
> > > Changes since v1:
> > > - New patch
> > >
> > > .../qualcomm/phy-qcom-usb4-5nm-qmp-combo.h | 1547 +++++++++++++++++
> > > 1 file changed, 1547 insertions(+)
> > > create mode 100644 drivers/phy/qualcomm/phy-qcom-usb4-5nm-qmp-combo.h
> > >
> > > diff --git a/drivers/phy/qualcomm/phy-qcom-usb4-5nm-qmp-combo.h b/drivers/phy/qualcomm/phy-qcom-usb4-5nm-qmp-combo.h
> > > new file mode 100644
> > > index 000000000000..7be8a50269ec
> > > --- /dev/null
> > > +++ b/drivers/phy/qualcomm/phy-qcom-usb4-5nm-qmp-combo.h
> > > @@ -0,0 +1,1547 @@
> > > +/* SPDX-License-Identifier: GPL-2.0-only */
> > > +/*
> > > + * Copyright (c) 2021, The Linux Foundation. All rights reserved.
> > > + */
> > > +
> > > +#ifndef PHY_QCOM_V5_5NM_QMP_COMBO_USB4_H
> > > +#define PHY_QCOM_V5_5NM_QMP_COMBO_USB4_H
> > > +
> > > +/* USB4-USB3-DP Combo PHY register offsets */
> > > +/* Module: USB43DP_COM_USB43DP_COM_USB4_USB3_DP_COM */
> > > +#define USB43DP_V5_5NM_COM_PHY_MODE_CTRL 0x00
> > > +#define USB43DP_V5_5NM_COM_SW_RESET 0x04
> > > +#define USB43DP_V5_5NM_COM_POWER_DOWN_CTRL 0x08
> > > +#define USB43DP_V5_5NM_COM_SWI_CTRL 0x0c
> > > +#define USB43DP_V5_5NM_COM_TYPEC_CTRL 0x10
> > > +#define USB43DP_V5_5NM_COM_TYPEC_PWRDN_CTRL 0x14
> > > +#define USB43DP_V5_5NM_COM_DP_BIST_CFG_0 0x18
> > > +#define USB43DP_V5_5NM_COM_RESET_OVRD_CTRL1 0x1c
> > > +#define USB43DP_V5_5NM_COM_RESET_OVRD_CTRL2 0x20
> > > +#define USB43DP_V5_5NM_COM_DBG_CLK_MUX_CTRL 0x24
> > > +#define USB43DP_V5_5NM_COM_TYPEC_STATUS 0x28
> > > +#define USB43DP_V5_5NM_COM_PLACEHOLDER_STATUS 0x2c
> > > +#define USB43DP_V5_5NM_COM_REVISION_ID0 0x30
> > > +#define USB43DP_V5_5NM_COM_REVISION_ID1 0x34
> > > +#define USB43DP_V5_5NM_COM_REVISION_ID2 0x38
> > > +#define USB43DP_V5_5NM_COM_REVISION_ID3 0x3c
> >
> > QPHY_V5_DP_COM_foo ?
> >
>
> My first version of the QMP patch used V5 defines and USB worked
> sometimes. So I hacked up a thing to dump the phy sequences of the
> downstream and upstream kernels, compared the magic numbers and then
> tried to fit suitable constants.
>
> But it obviously was a waste of time and I would have to make up a
> different naming scheme for the ones that doesn't match the existing
> constants - when we could just use the autogenerated files that exist in
> the downstream kernels.
>
> [..]
> > > +#define USB43DP_V5_5NM_QSERDES_TXA_DEBUG_BUS1 0xf0
> > > +#define USB43DP_V5_5NM_QSERDES_TXA_DEBUG_BUS2 0xf4
> > > +#define USB43DP_V5_5NM_QSERDES_TXA_DEBUG_BUS3 0xf8
> > > +#define USB43DP_V5_5NM_QSERDES_TXA_TX_BKUP_RO_BUS 0xfc
> >
> > QSERDES_V5_20_TX_foo ? This looks compatible with the 4 registers that we
> > have in the header, but I can not verify the rest of registers
> >
>
> Exactly the point I was making in my reply to the other patch.
>
> Per the documentation this is version 5.0.0, but these register offsets
> happens to match the 5.20 defines that we have...
>
> > > +
> > > +/* Module: USB43DP_QSERDES_RXA_USB43DP_QSERDES_RXA_USB4_USB3_DP_QMP_RX */
> [..]
> > > +#define USB43DP_V5_5NM_QSERDES_RXA_RX_BKUP_READ_BUS3_STATUS 0x3e8
>
> And these, doesn't match either V5 or V5_20.
Yes, I guessed so.
>
> [..]
> > > +#define USB43DP_V5_5NM_QSERDES_TXB_TX_BKUP_RO_BUS 0xfc
> >
> > What is the difference between _TXA_ and _TXB_ ?
> >
>
> Nothing, I just don't want us to mess around with these files if we can
> get them dumped from the register documentation.
Well, you still had the register offsets adjusted, hadn't you? I think
we can also apply sed to convert the names and then check if they
match the existing headers or not. If they do not, create a new
prefix, repeat, etc.
>
> > > +
> [..]
> > > +
> > > +/* Module: USB3_PCS_MISC_USB3_PCS_MISC_USB3_PCS_MISC */
> > > +#define USB3_V5_5NM_PCS_MISC_TYPEC_CTRL 0x00
> > > +#define USB3_V5_5NM_PCS_MISC_TYPEC_PWRDN_CTRL 0x04
> > > +#define USB3_V5_5NM_PCS_MISC_PCS_MISC_CONFIG1 0x08
> > > +#define USB3_V5_5NM_PCS_MISC_CLAMP_ENABLE 0x0c
> > > +#define USB3_V5_5NM_PCS_MISC_TYPEC_STATUS 0x10
> > > +#define USB3_V5_5NM_PCS_MISC_PLACEHOLDER_STATUS 0x14
> >
> > QPHY_V4_PCS_MISC (or v5)
> >
>
> Perhaps, but then we're just making up those prefixes and hoping for the
> best.
>
> [..]
> > > +#define USB3_V5_5NM_PCS_EQ_CONFIG2 0x1e0
> > > +#define USB3_V5_5NM_PCS_EQ_CONFIG3 0x1e4
> > > +#define USB3_V5_5NM_PCS_EQ_CONFIG4 0x1E8
> > > +#define USB3_V5_5NM_PCS_EQ_CONFIG5 0x1EC
> >
> > This looks like both QPHY_V4_PCS and QPHY_V5_PCS. Most probably we should
> > merge them together and add these defines.
> >
>
> Exactly, all these defines looks like defines we already have and if you
> pick the wrong one you end up with things not working - or in my case
> something that worked sometimes.
>
> > > +
> > > +/* Module: USB3_PCS_USB3_USB3_PCS_USB3_USB3_PCS_USB3 */
> [..]
> > > +#define USB3_V5_5NM_PCS_USB3_RXTERMINATION_DLY_SEL 0x60
> >
> > Again, QPHY_V5_PCS_USB w/o the 0x300 offset
> >
>
> Yeah, that extra region needs to be added to the binding and driver.
We can add it to the driver first (and just make it as an offset from pcs).
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 3/5] phy: qcom-qmp: Add USB4 5NM QMP combo PHY registers
2022-06-07 23:04 ` Bjorn Andersson
2022-06-07 23:28 ` Dmitry Baryshkov
@ 2022-06-07 23:52 ` Dmitry Baryshkov
2022-06-08 15:38 ` Vinod Koul
1 sibling, 1 reply; 16+ messages in thread
From: Dmitry Baryshkov @ 2022-06-07 23:52 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Kishon Vijay Abraham I, Vinod Koul, Manu Gautam, Rob Herring,
Krzysztof Kozlowski, linux-arm-msm, linux-phy, devicetree,
linux-kernel
On Wed, 8 Jun 2022 at 02:02, Bjorn Andersson <bjorn.andersson@linaro.org> wrote:
>
> On Tue 07 Jun 15:24 PDT 2022, Dmitry Baryshkov wrote:
>
> > On 08/06/2022 00:35, Bjorn Andersson wrote:
> > > Add all registers defines from qcom,usb4-5nm-qmp-combo.h of the msm-5.4
> > > kernel. Offsets are adjusted to be relative to each sub-block, as we
> > > describe the individual pieces in the upstream kernel and "v5_5NM" are
> > > injected in the defines to not collide with existing constants.
> > >
> > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> > > ---
> > >
> > > Changes since v1:
> > > - New patch
> > >
> > > .../qualcomm/phy-qcom-usb4-5nm-qmp-combo.h | 1547 +++++++++++++++++
> > > 1 file changed, 1547 insertions(+)
> > > create mode 100644 drivers/phy/qualcomm/phy-qcom-usb4-5nm-qmp-combo.h
> > >
> > > diff --git a/drivers/phy/qualcomm/phy-qcom-usb4-5nm-qmp-combo.h b/drivers/phy/qualcomm/phy-qcom-usb4-5nm-qmp-combo.h
> > > new file mode 100644
> > > index 000000000000..7be8a50269ec
> > > --- /dev/null
> > > +++ b/drivers/phy/qualcomm/phy-qcom-usb4-5nm-qmp-combo.h
> > > @@ -0,0 +1,1547 @@
> > > +/* SPDX-License-Identifier: GPL-2.0-only */
> > > +/*
> > > + * Copyright (c) 2021, The Linux Foundation. All rights reserved.
> > > + */
> > > +
> > > +#ifndef PHY_QCOM_V5_5NM_QMP_COMBO_USB4_H
> > > +#define PHY_QCOM_V5_5NM_QMP_COMBO_USB4_H
> > > +
> > > +/* USB4-USB3-DP Combo PHY register offsets */
> > > +/* Module: USB43DP_COM_USB43DP_COM_USB4_USB3_DP_COM */
> > > +#define USB43DP_V5_5NM_COM_PHY_MODE_CTRL 0x00
> > > +#define USB43DP_V5_5NM_COM_SW_RESET 0x04
> > > +#define USB43DP_V5_5NM_COM_POWER_DOWN_CTRL 0x08
> > > +#define USB43DP_V5_5NM_COM_SWI_CTRL 0x0c
> > > +#define USB43DP_V5_5NM_COM_TYPEC_CTRL 0x10
> > > +#define USB43DP_V5_5NM_COM_TYPEC_PWRDN_CTRL 0x14
> > > +#define USB43DP_V5_5NM_COM_DP_BIST_CFG_0 0x18
> > > +#define USB43DP_V5_5NM_COM_RESET_OVRD_CTRL1 0x1c
> > > +#define USB43DP_V5_5NM_COM_RESET_OVRD_CTRL2 0x20
> > > +#define USB43DP_V5_5NM_COM_DBG_CLK_MUX_CTRL 0x24
> > > +#define USB43DP_V5_5NM_COM_TYPEC_STATUS 0x28
> > > +#define USB43DP_V5_5NM_COM_PLACEHOLDER_STATUS 0x2c
> > > +#define USB43DP_V5_5NM_COM_REVISION_ID0 0x30
> > > +#define USB43DP_V5_5NM_COM_REVISION_ID1 0x34
> > > +#define USB43DP_V5_5NM_COM_REVISION_ID2 0x38
> > > +#define USB43DP_V5_5NM_COM_REVISION_ID3 0x3c
> >
> > QPHY_V5_DP_COM_foo ?
> >
>
> My first version of the QMP patch used V5 defines and USB worked
> sometimes. So I hacked up a thing to dump the phy sequences of the
> downstream and upstream kernels, compared the magic numbers and then
> tried to fit suitable constants.
>
> But it obviously was a waste of time and I would have to make up a
> different naming scheme for the ones that doesn't match the existing
> constants - when we could just use the autogenerated files that exist in
> the downstream kernels.
I decided that I should write more about it. My main issue with using
downstream tables is that we end up with tons of repetitive defines.
Each chip generation would bring 2-4 sets of tables, wouldn't it? This
can easily become an unsupported beast.
I'd propose to follow the opposite path. Let's split the existing
tables on a per-generation, per-region basis. Yes, we'd end up with
tens of the header files. However then when new generation arrives, we
can split corresponding header files on a region-by-region basis, and
compare each region with existing tables. If the region matches, use
it. If it does not, create a new header. Yes, I can do this for the
existing header as a continuation of the QMP split saga, if everybody
agrees that this is a good path.
You can ask, why do I suggest such a scheme? Because it looks like the
lowest common scheme. If we check downstream, we have USB/USB+DP with
huge autogenerated tables. Then comes UFS, which mostly follows naming
of the phy-qcom-qmp.h.
And the last one is a PCIe. I do not know about the sc8280xp, but for
the rest of the platforms we do not have register names at all. When I
was porting the SM8450 PCIe PHY support, I had to guess the correct
generation beforehand. With just 5 QSERDES_COM_ namespaces, guessing
is easy. If we had separate namespaces for the UFS and for several
USB PHY instances, guessing would be next to impossible. And then
creating a correct table would also be impossible. Well, as long as we
do not accept tables without register names.
Thus I think we should resort to using a single naming scheme rather
than following downstream here. If you dislike existing
QSERDES_Vn/QPHY_Vn, let's come up with something more sensible.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 3/5] phy: qcom-qmp: Add USB4 5NM QMP combo PHY registers
2022-06-07 23:52 ` Dmitry Baryshkov
@ 2022-06-08 15:38 ` Vinod Koul
0 siblings, 0 replies; 16+ messages in thread
From: Vinod Koul @ 2022-06-08 15:38 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Bjorn Andersson, Kishon Vijay Abraham I, Manu Gautam, Rob Herring,
Krzysztof Kozlowski, linux-arm-msm, linux-phy, devicetree,
linux-kernel
On 08-06-22, 02:52, Dmitry Baryshkov wrote:
> On Wed, 8 Jun 2022 at 02:02, Bjorn Andersson <bjorn.andersson@linaro.org> wrote:
> >
> > On Tue 07 Jun 15:24 PDT 2022, Dmitry Baryshkov wrote:
> >
> > > On 08/06/2022 00:35, Bjorn Andersson wrote:
> > > > Add all registers defines from qcom,usb4-5nm-qmp-combo.h of the msm-5.4
> > > > kernel. Offsets are adjusted to be relative to each sub-block, as we
> > > > describe the individual pieces in the upstream kernel and "v5_5NM" are
> > > > injected in the defines to not collide with existing constants.
> > > >
> > > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> > > > ---
> > > >
> > > > Changes since v1:
> > > > - New patch
> > > >
> > > > .../qualcomm/phy-qcom-usb4-5nm-qmp-combo.h | 1547 +++++++++++++++++
> > > > 1 file changed, 1547 insertions(+)
> > > > create mode 100644 drivers/phy/qualcomm/phy-qcom-usb4-5nm-qmp-combo.h
> > > >
> > > > diff --git a/drivers/phy/qualcomm/phy-qcom-usb4-5nm-qmp-combo.h b/drivers/phy/qualcomm/phy-qcom-usb4-5nm-qmp-combo.h
> > > > new file mode 100644
> > > > index 000000000000..7be8a50269ec
> > > > --- /dev/null
> > > > +++ b/drivers/phy/qualcomm/phy-qcom-usb4-5nm-qmp-combo.h
> > > > @@ -0,0 +1,1547 @@
> > > > +/* SPDX-License-Identifier: GPL-2.0-only */
> > > > +/*
> > > > + * Copyright (c) 2021, The Linux Foundation. All rights reserved.
> > > > + */
> > > > +
> > > > +#ifndef PHY_QCOM_V5_5NM_QMP_COMBO_USB4_H
> > > > +#define PHY_QCOM_V5_5NM_QMP_COMBO_USB4_H
> > > > +
> > > > +/* USB4-USB3-DP Combo PHY register offsets */
> > > > +/* Module: USB43DP_COM_USB43DP_COM_USB4_USB3_DP_COM */
> > > > +#define USB43DP_V5_5NM_COM_PHY_MODE_CTRL 0x00
> > > > +#define USB43DP_V5_5NM_COM_SW_RESET 0x04
> > > > +#define USB43DP_V5_5NM_COM_POWER_DOWN_CTRL 0x08
> > > > +#define USB43DP_V5_5NM_COM_SWI_CTRL 0x0c
> > > > +#define USB43DP_V5_5NM_COM_TYPEC_CTRL 0x10
> > > > +#define USB43DP_V5_5NM_COM_TYPEC_PWRDN_CTRL 0x14
> > > > +#define USB43DP_V5_5NM_COM_DP_BIST_CFG_0 0x18
> > > > +#define USB43DP_V5_5NM_COM_RESET_OVRD_CTRL1 0x1c
> > > > +#define USB43DP_V5_5NM_COM_RESET_OVRD_CTRL2 0x20
> > > > +#define USB43DP_V5_5NM_COM_DBG_CLK_MUX_CTRL 0x24
> > > > +#define USB43DP_V5_5NM_COM_TYPEC_STATUS 0x28
> > > > +#define USB43DP_V5_5NM_COM_PLACEHOLDER_STATUS 0x2c
> > > > +#define USB43DP_V5_5NM_COM_REVISION_ID0 0x30
> > > > +#define USB43DP_V5_5NM_COM_REVISION_ID1 0x34
> > > > +#define USB43DP_V5_5NM_COM_REVISION_ID2 0x38
> > > > +#define USB43DP_V5_5NM_COM_REVISION_ID3 0x3c
> > >
> > > QPHY_V5_DP_COM_foo ?
> > >
> >
> > My first version of the QMP patch used V5 defines and USB worked
> > sometimes. So I hacked up a thing to dump the phy sequences of the
> > downstream and upstream kernels, compared the magic numbers and then
> > tried to fit suitable constants.
> >
> > But it obviously was a waste of time and I would have to make up a
> > different naming scheme for the ones that doesn't match the existing
> > constants - when we could just use the autogenerated files that exist in
> > the downstream kernels.
>
> I decided that I should write more about it. My main issue with using
> downstream tables is that we end up with tons of repetitive defines.
> Each chip generation would bring 2-4 sets of tables, wouldn't it? This
> can easily become an unsupported beast.
> I'd propose to follow the opposite path. Let's split the existing
> tables on a per-generation, per-region basis. Yes, we'd end up with
> tens of the header files. However then when new generation arrives, we
> can split corresponding header files on a region-by-region basis, and
> compare each region with existing tables. If the region matches, use
> it. If it does not, create a new header. Yes, I can do this for the
> existing header as a continuation of the QMP split saga, if everybody
> agrees that this is a good path.
>
> You can ask, why do I suggest such a scheme? Because it looks like the
> lowest common scheme. If we check downstream, we have USB/USB+DP with
> huge autogenerated tables. Then comes UFS, which mostly follows naming
> of the phy-qcom-qmp.h.
>
> And the last one is a PCIe. I do not know about the sc8280xp, but for
> the rest of the platforms we do not have register names at all. When I
> was porting the SM8450 PCIe PHY support, I had to guess the correct
> generation beforehand. With just 5 QSERDES_COM_ namespaces, guessing
> is easy. If we had separate namespaces for the UFS and for several
> USB PHY instances, guessing would be next to impossible. And then
> creating a correct table would also be impossible. Well, as long as we
> do not accept tables without register names.
>
> Thus I think we should resort to using a single naming scheme rather
> than following downstream here. If you dislike existing
> QSERDES_Vn/QPHY_Vn, let's come up with something more sensible.
Bjorn has a valid point that we should not tinker with downstream
auto-generated headers and use as is. But Dmitry also has a good
argument of this becoming unmanageable mess.
So which of the lesser devils should we deal with... Former is easy to
do, latter involves a bit of work for kernel developers...
TBH My personal taste would be latter as that keeps the code clean... We
have seen the versions are getting managed terribly downstream.. Maybe
splitting the headers up is a good idea in that direction...
Thought...?
--
~Vinod
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v2 4/5] phy: qcom-qmp: Add SC8280XP USB3 UNI phy
2022-06-07 21:35 [PATCH v2 0/5] phy: qcom: Add SC8280XP UNI and COMBO USB phys Bjorn Andersson
` (2 preceding siblings ...)
2022-06-07 21:35 ` [PATCH v2 3/5] phy: qcom-qmp: Add USB4 5NM QMP combo PHY registers Bjorn Andersson
@ 2022-06-07 21:35 ` Bjorn Andersson
2022-06-07 21:35 ` [PATCH v2 5/5] phy: qcom-qmp: Add sc8280xp USB/DP combo phys Bjorn Andersson
2022-06-07 22:34 ` [PATCH v2 0/5] phy: qcom: Add SC8280XP UNI and COMBO USB phys Dmitry Baryshkov
5 siblings, 0 replies; 16+ messages in thread
From: Bjorn Andersson @ 2022-06-07 21:35 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Manu Gautam
Cc: Rob Herring, Krzysztof Kozlowski, linux-arm-msm, linux-phy,
devicetree, linux-kernel
The SC8280XP platform has two instances of the 5nm USB3 UNI phy attached
to the multi-port USB controller, add definition for these.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
Changes since v1:
- Moved to uni-phy driver
drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 138 ++++++++++++++++++++++++
1 file changed, 138 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
index aebe5ed4e4e3..75b8c4bf1548 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
@@ -23,6 +23,7 @@
#include <dt-bindings/phy/phy.h>
#include "phy-qcom-qmp.h"
+#include "phy-qcom-usb3-5nm-qmp-uni.h"
/* QPHY_SW_RESET bit */
#define SW_RESET BIT(0)
@@ -1347,6 +1348,111 @@ static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
};
+static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_serdes_tbl[] = {
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_COM_HSCLK_SEL, 0x01),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_COM_DEC_START_MODE0, 0x82),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_COM_DIV_FRAC_START1_MODE0, 0xab),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_COM_DIV_FRAC_START2_MODE0, 0xea),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_COM_DIV_FRAC_START3_MODE0, 0x02),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_COM_CP_CTRL_MODE0, 0x06),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_COM_PLL_CCTRL_MODE0, 0x36),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_COM_VCO_TUNE1_MODE0, 0x24),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_COM_LOCK_CMP1_MODE0, 0x14),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_COM_LOCK_CMP_EN, 0x04),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_COM_SYSCLK_BUF_ENABLE, 0x0a),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_COM_VCO_TUNE2_MODE1, 0x02),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_COM_VCO_TUNE1_MODE1, 0x24),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_COM_CORECLK_DIV_MODE1, 0x08),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_COM_DEC_START_MODE1, 0x82),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_COM_DIV_FRAC_START1_MODE1, 0xab),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_COM_DIV_FRAC_START2_MODE1, 0xea),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_COM_DIV_FRAC_START3_MODE1, 0x02),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_COM_LOCK_CMP2_MODE1, 0x82),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_COM_LOCK_CMP1_MODE1, 0x34),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_COM_CP_CTRL_MODE1, 0x06),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_COM_PLL_CCTRL_MODE1, 0x36),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_COM_SSC_EN_CENTER, 0x01),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_COM_SSC_PER1, 0x31),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_COM_SSC_PER2, 0x01),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE1, 0xde),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE1, 0x07),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0, 0xde),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0, 0x07),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_COM_VCO_TUNE_MAP, 0x02),
+};
+
+static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_tx_tbl[] = {
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_TX_LANE_MODE_1, 0xa5),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_TX_LANE_MODE_2, 0x82),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_TX_LANE_MODE_3, 0x3f),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_TX_LANE_MODE_4, 0x3f),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_TX_PI_QEC_CTRL, 0x21),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
+};
+
+static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_rx_tbl[] = {
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_RX_RX_MODE_00_HIGH4, 0xdc),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_RX_RX_MODE_00_HIGH3, 0xbd),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_RX_RX_MODE_00_HIGH2, 0xff),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_RX_RX_MODE_00_HIGH, 0x7f),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_RX_RX_MODE_00_LOW, 0xff),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_RX_RX_MODE_01_HIGH4, 0xa9),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_RX_RX_MODE_01_HIGH3, 0x7b),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_RX_RX_MODE_01_HIGH2, 0xe4),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_RX_RX_MODE_01_HIGH, 0x24),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_RX_RX_MODE_01_LOW, 0x64),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_RX_UCDR_PI_CONTROLS, 0x99),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_RX_UCDR_SB2_THRESH1, 0x08),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_RX_UCDR_SB2_THRESH2, 0x08),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_RX_UCDR_SB2_GAIN1, 0x00),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_RX_UCDR_SB2_GAIN2, 0x04),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_RX_UCDR_FO_GAIN, 0x0a),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_RX_VGA_CAL_CNTRL1, 0x54),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_RX_VGA_CAL_CNTRL2, 0x0f),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_RX_SIGDET_CNTRL, 0x04),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_RX_UCDR_SO_GAIN, 0x05),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_RX_GM_CAL, 0x00),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_QSERDES_RX_SIGDET_ENABLES, 0x00),
+};
+
+static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_pcs_tbl[] = {
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_PCS_LOCK_DETECT_CONFIG1, 0xd0),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_PCS_LOCK_DETECT_CONFIG2, 0x07),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_PCS_LOCK_DETECT_CONFIG3, 0x20),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_PCS_LOCK_DETECT_CONFIG6, 0x13),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_PCS_RX_SIGDET_LVL, 0xaa),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_PCS_PCS_TX_RX_CONFIG, 0x0c),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_PCS_CDR_RESET_TIME, 0x0a),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_PCS_ALIGN_DETECT_CONFIG1, 0x88),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_PCS_ALIGN_DETECT_CONFIG2, 0x13),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_PCS_EQ_CONFIG1, 0x4b),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_PCS_EQ_CONFIG5, 0x10),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_UNI_PCS_REFGEN_REQ_CONFIG1, 0x21),
+};
+
struct qmp_phy;
/* struct qmp_phy_cfg - per-PHY initialization config */
@@ -1635,6 +1741,35 @@ static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
.is_dual_lane_phy = true,
};
+static const struct qmp_phy_cfg sc8280xp_usb3_uniphy_cfg = {
+ .type = PHY_TYPE_USB3,
+ .nlanes = 1,
+
+ .serdes_tbl = sc8280xp_usb3_uniphy_serdes_tbl,
+ .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_serdes_tbl),
+ .tx_tbl = sc8280xp_usb3_uniphy_tx_tbl,
+ .tx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_tx_tbl),
+ .rx_tbl = sc8280xp_usb3_uniphy_rx_tbl,
+ .rx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_rx_tbl),
+ .pcs_tbl = sc8280xp_usb3_uniphy_pcs_tbl,
+ .pcs_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_pcs_tbl),
+ .clk_list = qmp_v4_phy_clk_l,
+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
+ .reset_list = msm8996_usb3phy_reset_l,
+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
+ .vreg_list = qmp_phy_vreg_l,
+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+ .regs = qmp_v4_usb3_uniphy_regs_layout,
+
+ .start_ctrl = SERDES_START | PCS_START,
+ .pwrdn_ctrl = SW_PWRDN,
+ .phy_status = PHYSTATUS,
+
+ .has_pwrdn_delay = true,
+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
+};
+
static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
.type = PHY_TYPE_USB3,
.nlanes = 1,
@@ -2580,6 +2715,9 @@ static const struct of_device_id qcom_qmp_phy_usb_of_match_table[] = {
}, {
.compatible = "qcom,sc8180x-qmp-usb3-phy",
.data = &sm8150_usb3phy_cfg,
+ }, {
+ .compatible = "qcom,sc8280xp-qmp-usb3-uni-phy",
+ .data = &sc8280xp_usb3_uniphy_cfg,
}, {
.compatible = "qcom,sdm845-qmp-usb3-phy",
.data = &qmp_v3_usb3phy_cfg,
--
2.35.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 5/5] phy: qcom-qmp: Add sc8280xp USB/DP combo phys
2022-06-07 21:35 [PATCH v2 0/5] phy: qcom: Add SC8280XP UNI and COMBO USB phys Bjorn Andersson
` (3 preceding siblings ...)
2022-06-07 21:35 ` [PATCH v2 4/5] phy: qcom-qmp: Add SC8280XP USB3 UNI phy Bjorn Andersson
@ 2022-06-07 21:35 ` Bjorn Andersson
2022-06-07 22:34 ` [PATCH v2 0/5] phy: qcom: Add SC8280XP UNI and COMBO USB phys Dmitry Baryshkov
5 siblings, 0 replies; 16+ messages in thread
From: Bjorn Andersson @ 2022-06-07 21:35 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Manu Gautam
Cc: Rob Herring, Krzysztof Kozlowski, linux-arm-msm, linux-phy,
devicetree, linux-kernel
The SC8280P has two copies of an USB/DP compbo PHY, add support for this
to the Qualcomm QMP PHY driver.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
Changes since v1:
- New patch
drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 205 ++++++++++++++++++++++
drivers/phy/qualcomm/phy-qcom-qmp.h | 13 ++
2 files changed, 218 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
index 893b5a4bb554..c18cd3b93c30 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
@@ -23,6 +23,7 @@
#include <dt-bindings/phy/phy.h>
#include "phy-qcom-qmp.h"
+#include "phy-qcom-usb4-5nm-qmp-combo.h"
/* QPHY_SW_RESET bit */
#define SW_RESET BIT(0)
@@ -604,6 +605,134 @@ static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),
};
+static const struct qmp_phy_init_tbl qmp_v420_5nm_dp_tx_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V4_20_5NM_DP_VMODE_CTRL1, 0x40),
+ QMP_PHY_INIT_CFG(QSERDES_V4_20_5NM_TXn_PRE_STALL_LDO_BOOST_EN, 0x30),
+ QMP_PHY_INIT_CFG(QSERDES_V4_20_5NM_TXn_INTERFACE_SELECT, 0x3b),
+ QMP_PHY_INIT_CFG(QSERDES_V4_20_5NM_TXn_CLKBUF_ENABLE, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_V4_20_5NM_TXn_RESET_TSYNC_EN, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_V4_20_5NM_DP_TRAN_DRVR_EMP_EN, 0xf),
+ QMP_PHY_INIT_CFG(QSERDES_V4_20_5NM_TXn_PARRATE_REC_DETECT_IDLE_EN, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V4_20_5NM_DP_TX_INTERFACE_MODE, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V4_20_5NM_TXn_RES_CODE_LANE_OFFSET_TX, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_V4_20_5NM_TXn_RES_CODE_LANE_OFFSET_RX, 0x11),
+ QMP_PHY_INIT_CFG(QSERDES_V4_20_5NM_TXn_TX_BAND, 0x04),
+};
+
+static const struct qmp_phy_init_tbl sc8280xp_usb43dp_serdes_tbl[] = {
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_QSERDES_PLL_SSC_EN_CENTER, 0x01),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_QSERDES_PLL_SSC_PER1, 0x31),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_QSERDES_PLL_SSC_PER2, 0x01),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0xfd),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x0d),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0xfd),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x0d),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x0a),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_QSERDES_PLL_CP_CTRL_MODE0, 0x02),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_QSERDES_PLL_CP_CTRL_MODE1, 0x02),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_QSERDES_PLL_PLL_CCTRL_MODE0, 0x36),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_QSERDES_PLL_PLL_CCTRL_MODE1, 0x36),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_QSERDES_PLL_SYSCLK_EN_SEL, 0x1a),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_QSERDES_PLL_LOCK_CMP_EN, 0x04),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_QSERDES_PLL_LOCK_CMP1_MODE0, 0x14),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_QSERDES_PLL_LOCK_CMP2_MODE0, 0x34),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_QSERDES_PLL_LOCK_CMP1_MODE1, 0x34),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_QSERDES_PLL_LOCK_CMP2_MODE1, 0x82),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_QSERDES_PLL_DEC_START_MODE0, 0x04),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_QSERDES_PLL_DEC_START_MSB_MODE0, 0x01),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_QSERDES_PLL_DEC_START_MODE1, 0x04),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_QSERDES_PLL_DEC_START_MSB_MODE1, 0x01),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_QSERDES_PLL_DIV_FRAC_START1_MODE0, 0x55),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xd5),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x05),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_QSERDES_PLL_DIV_FRAC_START2_MODE1, 0xd5),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_QSERDES_PLL_VCO_TUNE_MAP, 0x02),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_QSERDES_PLL_VCO_TUNE1_MODE0, 0xd4),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_QSERDES_PLL_VCO_TUNE2_MODE0, 0x00),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_QSERDES_PLL_VCO_TUNE1_MODE1, 0xd4),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_QSERDES_PLL_VCO_TUNE2_MODE1, 0x00),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_QSERDES_PLL_HSCLK_SEL, 0x13),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_QSERDES_PLL_HSCLK_HS_SWITCH_SEL, 0x00),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_QSERDES_PLL_CORECLK_DIV_MODE0, 0x0a),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_QSERDES_PLL_CORECLK_DIV_MODE1, 0x04),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_QSERDES_PLL_CORE_CLK_EN, 0x60),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_QSERDES_PLL_CMN_CONFIG, 0x76),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_QSERDES_PLL_PLL_IVCO, 0xff),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0x20),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0x20),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_QSERDES_PLL_VCO_TUNE_INITVAL2, 0x00),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_QSERDES_PLL_VCO_TUNE_MAXVAL2, 0x01),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_QSERDES_PLL_SVS_MODE_CLK_SEL, 0x0a),
+};
+
+static const struct qmp_phy_init_tbl sc8280xp_usb43dp_tx_tbl[] = {
+ QMP_PHY_INIT_CFG(USB43DP_V5_5NM_QSERDES_TXA_LANE_MODE_1, 0x05),
+ QMP_PHY_INIT_CFG(USB43DP_V5_5NM_QSERDES_TXA_LANE_MODE_2, 0xc2),
+ QMP_PHY_INIT_CFG(USB43DP_V5_5NM_QSERDES_TXA_LANE_MODE_3, 0x10),
+ QMP_PHY_INIT_CFG(USB43DP_V5_5NM_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX, 0x1f),
+ QMP_PHY_INIT_CFG(USB43DP_V5_5NM_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX, 0x0a),
+};
+
+static const struct qmp_phy_init_tbl sc8280xp_usb43dp_rx_tbl[] = {
+ QMP_PHY_INIT_CFG(USB43DP_V5_5NM_QSERDES_RXA_SIGDET_CNTRL, 0x04),
+ QMP_PHY_INIT_CFG(USB43DP_V5_5NM_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL, 0x0e),
+ QMP_PHY_INIT_CFG(USB43DP_V5_5NM_QSERDES_RXA_SIGDET_ENABLES, 0x00),
+ QMP_PHY_INIT_CFG(USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE_0_1_B0, 0xd2),
+ QMP_PHY_INIT_CFG(USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE_0_1_B1, 0xd2),
+ QMP_PHY_INIT_CFG(USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE_0_1_B2, 0xdb),
+ QMP_PHY_INIT_CFG(USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE_0_1_B3, 0x21),
+ QMP_PHY_INIT_CFG(USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE_0_1_B4, 0x3f),
+ QMP_PHY_INIT_CFG(USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE_0_1_B5, 0x80),
+ QMP_PHY_INIT_CFG(USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE_0_1_B6, 0x45),
+ QMP_PHY_INIT_CFG(USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE_0_1_B7, 0x00),
+ QMP_PHY_INIT_CFG(USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE2_B0, 0x6b),
+ QMP_PHY_INIT_CFG(USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE2_B1, 0x63),
+ QMP_PHY_INIT_CFG(USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE2_B2, 0xb6),
+ QMP_PHY_INIT_CFG(USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE2_B3, 0x23),
+ QMP_PHY_INIT_CFG(USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE2_B4, 0x35),
+ QMP_PHY_INIT_CFG(USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE2_B5, 0x30),
+ QMP_PHY_INIT_CFG(USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE2_B6, 0x8e),
+ QMP_PHY_INIT_CFG(USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE2_B7, 0x00),
+ QMP_PHY_INIT_CFG(USB43DP_V5_5NM_QSERDES_RXA_RX_IVCM_CAL_CODE_OVERRIDE, 0x00),
+ QMP_PHY_INIT_CFG(USB43DP_V5_5NM_QSERDES_RXA_RX_IVCM_CAL_CTRL2, 0x80),
+ QMP_PHY_INIT_CFG(USB43DP_V5_5NM_QSERDES_RXA_RX_SUMMER_CAL_SPD_MODE, 0x1b),
+ QMP_PHY_INIT_CFG(USB43DP_V5_5NM_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET, 0x38),
+ QMP_PHY_INIT_CFG(USB43DP_V5_5NM_QSERDES_RXA_UCDR_PI_CONTROLS, 0x15),
+ QMP_PHY_INIT_CFG(USB43DP_V5_5NM_QSERDES_RXA_UCDR_SB2_GAIN2_RATE2, 0x0a),
+ QMP_PHY_INIT_CFG(USB43DP_V5_5NM_QSERDES_RXA_RX_IVCM_POSTCAL_OFFSET, 0x7c),
+ QMP_PHY_INIT_CFG(USB43DP_V5_5NM_QSERDES_RXA_VGA_CAL_CNTRL1, 0x00),
+ QMP_PHY_INIT_CFG(USB43DP_V5_5NM_QSERDES_RXA_VGA_CAL_MAN_VAL, 0x0d),
+ QMP_PHY_INIT_CFG(USB43DP_V5_5NM_QSERDES_RXA_DFE_DAC_ENABLE1, 0x00),
+ QMP_PHY_INIT_CFG(USB43DP_V5_5NM_QSERDES_RXA_DFE_3, 0x45),
+ QMP_PHY_INIT_CFG(USB43DP_V5_5NM_QSERDES_RXA_GM_CAL, 0x09),
+ QMP_PHY_INIT_CFG(USB43DP_V5_5NM_QSERDES_RXA_UCDR_FO_GAIN_RATE2, 0x09),
+ QMP_PHY_INIT_CFG(USB43DP_V5_5NM_QSERDES_RXA_UCDR_SO_GAIN_RATE2, 0x05),
+ QMP_PHY_INIT_CFG(USB43DP_V5_5NM_QSERDES_RXA_Q_PI_INTRINSIC_BIAS_RATE32, 0x3f),
+};
+
+static const struct qmp_phy_init_tbl sc8280xp_usb43dp_pcs_tbl[] = {
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_PCS_LOCK_DETECT_CONFIG1, 0xd0),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_PCS_LOCK_DETECT_CONFIG2, 0x07),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_PCS_LOCK_DETECT_CONFIG3, 0x20),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_PCS_LOCK_DETECT_CONFIG6, 0x13),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_PCS_REFGEN_REQ_CONFIG1, 0x21),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_PCS_RX_SIGDET_LVL, 0xaa),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_PCS_RX_CONFIG, 0x0a),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_PCS_ALIGN_DETECT_CONFIG1, 0x88),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_PCS_ALIGN_DETECT_CONFIG2, 0x13),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_PCS_PCS_TX_RX_CONFIG, 0x0c),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_PCS_EQ_CONFIG1, 0x4b),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_PCS_EQ_CONFIG5, 0x10),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
+ QMP_PHY_INIT_CFG(USB3_V5_5NM_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
+};
+
struct qmp_phy;
/* struct qmp_phy_cfg - per-PHY initialization config */
@@ -959,6 +1088,78 @@ static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = {
.dp_cfg = &sc8180x_dpphy_cfg,
};
+static const struct qmp_phy_cfg sc8280xp_usb43dp_usb_cfg = {
+ .type = PHY_TYPE_USB3,
+ .nlanes = 1,
+
+ .serdes_tbl = sc8280xp_usb43dp_serdes_tbl,
+ .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_serdes_tbl),
+ .tx_tbl = sc8280xp_usb43dp_tx_tbl,
+ .tx_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_tx_tbl),
+ .rx_tbl = sc8280xp_usb43dp_rx_tbl,
+ .rx_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_rx_tbl),
+ .pcs_tbl = sc8280xp_usb43dp_pcs_tbl,
+ .pcs_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_pcs_tbl),
+ .clk_list = qmp_v4_phy_clk_l,
+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
+ .reset_list = msm8996_usb3phy_reset_l,
+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
+ .vreg_list = qmp_phy_vreg_l,
+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+ .regs = qmp_v4_usb3phy_regs_layout,
+
+ .start_ctrl = SERDES_START | PCS_START,
+ .pwrdn_ctrl = SW_PWRDN,
+ .phy_status = PHYSTATUS,
+
+ .has_pwrdn_delay = true,
+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
+
+ .has_phy_dp_com_ctrl = true,
+ .is_dual_lane_phy = true,
+};
+
+static const struct qmp_phy_cfg sc8280xp_usb43dp_dp_cfg = {
+ .type = PHY_TYPE_DP,
+ .nlanes = 1,
+
+ .serdes_tbl = qmp_v4_dp_serdes_tbl,
+ .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
+ .tx_tbl = qmp_v420_5nm_dp_tx_tbl,
+ .tx_tbl_num = ARRAY_SIZE(qmp_v420_5nm_dp_tx_tbl),
+
+ .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
+ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
+ .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
+ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
+ .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
+ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
+ .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
+ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
+
+ .clk_list = qmp_v4_phy_clk_l,
+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
+ .reset_list = msm8996_usb3phy_reset_l,
+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
+ .vreg_list = qmp_phy_vreg_l,
+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+ .regs = qmp_v4_usb3phy_regs_layout,
+
+ .has_phy_dp_com_ctrl = true,
+ .is_dual_lane_phy = true,
+
+ .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
+ .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
+ .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
+ .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
+};
+
+static const struct qmp_phy_combo_cfg sc8280xp_usb43dpphy_combo_cfg = {
+ .usb_cfg = &sc8280xp_usb43dp_usb_cfg,
+ .dp_cfg = &sc8280xp_usb43dp_dp_cfg,
+};
+
static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
.type = PHY_TYPE_USB3,
.nlanes = 1,
@@ -2407,6 +2608,10 @@ static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = {
.compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
.data = &sc8180x_usb3dpphy_cfg,
},
+ {
+ .compatible = "qcom,sc8280xp-qmp-usb43dp-phy",
+ .data = &sc8280xp_usb43dpphy_combo_cfg,
+ },
{ }
};
MODULE_DEVICE_TABLE(of, qcom_qmp_combo_phy_of_match_table);
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index 06b2556ed93a..eb5705d1e32c 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -652,6 +652,19 @@
#define QSERDES_V4_20_TX_VMODE_CTRL1 0xc4
#define QSERDES_V4_20_TX_PI_QEC_CTRL 0xe0
+/* Only for QMP v4_20 5nm DP PHY - TX registers */
+#define QSERDES_V4_20_5NM_TXn_TX_BAND 0x24
+#define QSERDES_V4_20_5NM_TXn_CLKBUF_ENABLE 0x08
+#define QSERDES_V4_20_5NM_TXn_RESET_TSYNC_EN 0x1c
+#define QSERDES_V4_20_5NM_TXn_INTERFACE_SELECT 0x2c
+#define QSERDES_V4_20_5NM_DP_TRAN_DRVR_EMP_EN 0xc0
+#define QSERDES_V4_20_5NM_DP_TX_INTERFACE_MODE 0xc4
+#define QSERDES_V4_20_5NM_DP_VMODE_CTRL1 0xc8
+#define QSERDES_V4_20_5NM_TXn_PRE_STALL_LDO_BOOST_EN 0x20
+#define QSERDES_V4_20_5NM_TXn_RES_CODE_LANE_OFFSET_RX 0x3c
+#define QSERDES_V4_20_5NM_TXn_RES_CODE_LANE_OFFSET_TX 0x40
+#define QSERDES_V4_20_5NM_TXn_PARRATE_REC_DETECT_IDLE_EN 0x60
+
/* Only for QMP V4 PHY - RX registers */
#define QSERDES_V4_RX_UCDR_FO_GAIN 0x008
#define QSERDES_V4_RX_UCDR_SO_GAIN 0x014
--
2.35.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v2 0/5] phy: qcom: Add SC8280XP UNI and COMBO USB phys
2022-06-07 21:35 [PATCH v2 0/5] phy: qcom: Add SC8280XP UNI and COMBO USB phys Bjorn Andersson
` (4 preceding siblings ...)
2022-06-07 21:35 ` [PATCH v2 5/5] phy: qcom-qmp: Add sc8280xp USB/DP combo phys Bjorn Andersson
@ 2022-06-07 22:34 ` Dmitry Baryshkov
5 siblings, 0 replies; 16+ messages in thread
From: Dmitry Baryshkov @ 2022-06-07 22:34 UTC (permalink / raw)
To: Bjorn Andersson, Kishon Vijay Abraham I, Vinod Koul, Rob Herring,
Krzysztof Kozlowski, Manu Gautam
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel
On 08/06/2022 00:35, Bjorn Andersson wrote:
> The Qualcomm SC8280XP has two pairs of USB phys; a pair of combo phys and a
> pair of uni phys. Introduce support for these.
>
> This is based ontop of Dmitry's refactoring of the QMP driver:
> https://lore.kernel.org/all/20220602070909.1666068-1-dmitry.baryshkov@linaro.org/
>
> A first version of this series was posted with only the UNI phy, this fixes a
> few comments and add the combo phy as well.
>
> Bjorn Andersson (5):
> dt-bindings: phy: qcom,qmp: Add compatible for SC8280XP USB phys
> phy: qcom-qmp: Add USB3 5NM QMP UNI registers
> phy: qcom-qmp: Add USB4 5NM QMP combo PHY registers
I've noted, which symbols look close enough to be folded into existing
namespaces. Could you please doublecheck my analysis and merge the tables?
> phy: qcom-qmp: Add SC8280XP USB3 UNI phy
> phy: qcom-qmp: Add sc8280xp USB/DP combo phys
>
> .../devicetree/bindings/phy/qcom,qmp-phy.yaml | 2 +
> .../bindings/phy/qcom,qmp-usb3-dp-phy.yaml | 1 +
> drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 205 +++
> drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 138 ++
> drivers/phy/qualcomm/phy-qcom-qmp.h | 13 +
> .../phy/qualcomm/phy-qcom-usb3-5nm-qmp-uni.h | 617 +++++++
> .../qualcomm/phy-qcom-usb4-5nm-qmp-combo.h | 1547 +++++++++++++++++
> 7 files changed, 2523 insertions(+)
> create mode 100644 drivers/phy/qualcomm/phy-qcom-usb3-5nm-qmp-uni.h
> create mode 100644 drivers/phy/qualcomm/phy-qcom-usb4-5nm-qmp-combo.h
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 16+ messages in thread