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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id 4-20020a544184000000b0032f75714af1sm3422554oiy.18.2022.06.25.20.19.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Jun 2022 20:19:58 -0700 (PDT) Date: Sat, 25 Jun 2022 22:19:56 -0500 From: Bjorn Andersson To: Rajendra Nayak Cc: Krzysztof Kozlowski , Andy Gross , Georgi Djakov , Rob Herring , Catalin Marinas , Will Deacon , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Rob Herring Subject: Re: [PATCH v4 1/4] dt-bindings: interconnect: qcom,sdm845-cpu-bwmon: add BWMON device Message-ID: References: <20220601101140.170504-1-krzysztof.kozlowski@linaro.org> <20220601101140.170504-2-krzysztof.kozlowski@linaro.org> <3e4e504c-5a38-43cd-ea8d-afbbb72eacad@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Wed 22 Jun 06:58 CDT 2022, Rajendra Nayak wrote: > > > On 6/7/2022 12:20 PM, Krzysztof Kozlowski wrote: > > On 06/06/2022 23:11, Bjorn Andersson wrote: > > > On Wed 01 Jun 03:11 PDT 2022, Krzysztof Kozlowski wrote: > > > > > > > Add bindings for the Qualcomm Bandwidth Monitor device providing > > > > performance data on interconnects. The bindings describe only BWMON > > > > version 4, e.g. the instance on SDM845 between CPU and Last Level Cache > > > > Controller. > > > > > > > > Signed-off-by: Krzysztof Kozlowski > > > > Reviewed-by: Rob Herring > > > > Acked-by: Georgi Djakov > > > > --- > > > > .../interconnect/qcom,sdm845-cpu-bwmon.yaml | 97 +++++++++++++++++++ > > > > 1 file changed, 97 insertions(+) > > > > create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,sdm845-cpu-bwmon.yaml > > > > > > > > diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sdm845-cpu-bwmon.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sdm845-cpu-bwmon.yaml > > > > new file mode 100644 > > > > index 000000000000..8c82e06ee432 > > > > --- /dev/null > > > > +++ b/Documentation/devicetree/bindings/interconnect/qcom,sdm845-cpu-bwmon.yaml > > > > @@ -0,0 +1,97 @@ > > > > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > > > > +%YAML 1.2 > > > > +--- > > > > +$id: http://devicetree.org/schemas/interconnect/qcom,sdm845-cpu-bwmon.yaml# > > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > > + > > > > +title: Qualcomm Interconnect Bandwidth Monitor > > > > + > > > > +maintainers: > > > > + - Krzysztof Kozlowski > > > > + > > > > +description: > > > > + Bandwidth Monitor measures current throughput on buses between various NoC > > > > + fabrics and provides information when it crosses configured thresholds. > > > > + > > > > +properties: > > > > + compatible: > > > > + enum: > > > > + - qcom,sdm845-cpu-bwmon # BWMON v4 > > > > > > It seems the thing that's called bwmon v4 is compatible with a number of > > > different platforms, should we add a generic compatible to the binding > > > as well, to avoid having to update the implementation for each SoC? > > > > > > (I.e. "qcom,sdm845-cpu-bwmon", "qcom,bwmon-v4") > > it seems pretty useful to have the "qcom,bwmon-v4" and "qcom,bwmon-v5" > compatibles, I tried these patches on a sc7280 device which has a bwmon4 > between the cpu and caches (and also has a bwmon5 between the caches and DDR) > and the driver works with zero changes. > But does the '4' and '5' has a relation to the hardware? Or is just the 4th and 5th register layout supported by the downstream driver? Regards, Bjorn