* [PATCH 0/3] arm64: dts: qcom: sdm845-db845: Some i2c fixes
@ 2022-07-17 3:44 Bjorn Andersson
2022-07-17 3:44 ` [PATCH 1/3] arm64: dts: qcom: sdm845: Fill in GENI DMA references Bjorn Andersson
` (4 more replies)
0 siblings, 5 replies; 6+ messages in thread
From: Bjorn Andersson @ 2022-07-17 3:44 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio
Cc: Rob Herring, Krzysztof Kozlowski, linux-arm-msm, devicetree,
linux-kernel, vinod.koul
On my db845c (perhaps old firmware?) i2c14 is using GPI, so this enables that.
And while I'm touching it I added dma properties to all the geni i2c and spi
nodes and specified a default clock to avoid two warnings in the log during
boot.
Bjorn Andersson (3):
arm64: dts: qcom: sdm845: Fill in GENI DMA references
arm64: dts: qcom: sdm845-db845c: Enable gpi_dma1
arm64: dts: qcom: sdm845-db845c: Specify a i2c bus clocks
arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 6 ++
arch/arm64/boot/dts/qcom/sdm845.dtsi | 90 ++++++++++++++++++++++
2 files changed, 96 insertions(+)
--
2.35.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/3] arm64: dts: qcom: sdm845: Fill in GENI DMA references
2022-07-17 3:44 [PATCH 0/3] arm64: dts: qcom: sdm845-db845: Some i2c fixes Bjorn Andersson
@ 2022-07-17 3:44 ` Bjorn Andersson
2022-07-17 3:44 ` [PATCH 2/3] arm64: dts: qcom: sdm845-db845c: Enable gpi_dma1 Bjorn Andersson
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Bjorn Andersson @ 2022-07-17 3:44 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio
Cc: Rob Herring, Krzysztof Kozlowski, linux-arm-msm, devicetree,
linux-kernel, vinod.koul
The I2C and SPI might be configured in GPI DMA mode, fill in the
properties needed for this.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 90 ++++++++++++++++++++++++++++
1 file changed, 90 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 7fb10c2ef2fb..7735efd233e4 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -1208,6 +1208,9 @@ i2c0: i2c@880000 {
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
<&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 0 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -1262,6 +1265,9 @@ i2c1: i2c@884000 {
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
<&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 1 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -1278,6 +1284,9 @@ spi1: spi@884000 {
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
interconnect-names = "qup-core", "qup-config";
+ dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 1 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -1313,6 +1322,9 @@ i2c2: i2c@888000 {
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
<&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 2 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -1329,6 +1341,9 @@ spi2: spi@888000 {
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
interconnect-names = "qup-core", "qup-config";
+ dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 2 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -1364,6 +1379,9 @@ i2c3: i2c@88c000 {
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
<&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 3 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -1380,6 +1398,9 @@ spi3: spi@88c000 {
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
interconnect-names = "qup-core", "qup-config";
+ dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 3 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -1415,6 +1436,9 @@ i2c4: i2c@890000 {
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
<&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 4 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -1431,6 +1455,9 @@ spi4: spi@890000 {
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
interconnect-names = "qup-core", "qup-config";
+ dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 4 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -1466,6 +1493,9 @@ i2c5: i2c@894000 {
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
<&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 5 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -1482,6 +1512,9 @@ spi5: spi@894000 {
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
interconnect-names = "qup-core", "qup-config";
+ dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 5 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -1517,6 +1550,9 @@ i2c6: i2c@898000 {
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
<&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 6 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -1533,6 +1569,9 @@ spi6: spi@898000 {
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
interconnect-names = "qup-core", "qup-config";
+ dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 6 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -1580,6 +1619,9 @@ spi7: spi@89c000 {
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
interconnect-names = "qup-core", "qup-config";
+ dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 7 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -1653,6 +1695,9 @@ i2c8: i2c@a80000 {
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
<&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 0 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -1669,6 +1714,9 @@ spi8: spi@a80000 {
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
interconnect-names = "qup-core", "qup-config";
+ dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 0 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -1704,6 +1752,9 @@ i2c9: i2c@a84000 {
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
<&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 1 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -1720,6 +1771,9 @@ spi9: spi@a84000 {
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
interconnect-names = "qup-core", "qup-config";
+ dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 1 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -1755,6 +1809,9 @@ i2c10: i2c@a88000 {
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
<&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 2 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -1771,6 +1828,9 @@ spi10: spi@a88000 {
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
interconnect-names = "qup-core", "qup-config";
+ dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 2 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -1806,6 +1866,9 @@ i2c11: i2c@a8c000 {
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
<&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 3 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -1822,6 +1885,9 @@ spi11: spi@a8c000 {
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
interconnect-names = "qup-core", "qup-config";
+ dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 3 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -1857,6 +1923,9 @@ i2c12: i2c@a90000 {
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
<&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 4 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -1873,6 +1942,9 @@ spi12: spi@a90000 {
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
interconnect-names = "qup-core", "qup-config";
+ dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 4 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -1908,6 +1980,9 @@ i2c13: i2c@a94000 {
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
<&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 5 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -1924,6 +1999,9 @@ spi13: spi@a94000 {
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
interconnect-names = "qup-core", "qup-config";
+ dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 5 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -1959,6 +2037,9 @@ i2c14: i2c@a98000 {
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
<&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 6 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -1975,6 +2056,9 @@ spi14: spi@a98000 {
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
interconnect-names = "qup-core", "qup-config";
+ dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 6 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -2011,6 +2095,9 @@ i2c15: i2c@a9c000 {
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
<&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 7 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
};
spi15: spi@a9c000 {
@@ -2026,6 +2113,9 @@ spi15: spi@a9c000 {
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
interconnect-names = "qup-core", "qup-config";
+ dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 7 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
status = "disabled";
};
--
2.35.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/3] arm64: dts: qcom: sdm845-db845c: Enable gpi_dma1
2022-07-17 3:44 [PATCH 0/3] arm64: dts: qcom: sdm845-db845: Some i2c fixes Bjorn Andersson
2022-07-17 3:44 ` [PATCH 1/3] arm64: dts: qcom: sdm845: Fill in GENI DMA references Bjorn Andersson
@ 2022-07-17 3:44 ` Bjorn Andersson
2022-07-17 3:44 ` [PATCH 3/3] arm64: dts: qcom: sdm845-db845c: Specify a i2c bus clocks Bjorn Andersson
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Bjorn Andersson @ 2022-07-17 3:44 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio
Cc: Rob Herring, Krzysztof Kozlowski, linux-arm-msm, devicetree,
linux-kernel, vinod.koul
Enable gpi_dma1 so that i2c14 is able to find its DMA controller.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
index 4afdb72cc556..62ad67370d2b 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
+++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
@@ -443,6 +443,10 @@ &gpi_dma0 {
status = "okay";
};
+&gpi_dma1 {
+ status = "okay";
+};
+
&gpu {
status = "okay";
zap-shader {
--
2.35.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 3/3] arm64: dts: qcom: sdm845-db845c: Specify a i2c bus clocks
2022-07-17 3:44 [PATCH 0/3] arm64: dts: qcom: sdm845-db845: Some i2c fixes Bjorn Andersson
2022-07-17 3:44 ` [PATCH 1/3] arm64: dts: qcom: sdm845: Fill in GENI DMA references Bjorn Andersson
2022-07-17 3:44 ` [PATCH 2/3] arm64: dts: qcom: sdm845-db845c: Enable gpi_dma1 Bjorn Andersson
@ 2022-07-17 3:44 ` Bjorn Andersson
2022-07-18 5:31 ` [PATCH 0/3] arm64: dts: qcom: sdm845-db845: Some i2c fixes Vinod Koul
2022-07-19 4:47 ` Bjorn Andersson
4 siblings, 0 replies; 6+ messages in thread
From: Bjorn Andersson @ 2022-07-17 3:44 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio
Cc: Rob Herring, Krzysztof Kozlowski, linux-arm-msm, devicetree,
linux-kernel, vinod.koul
The kernel log contains complaints about i2c11 and i2c14 lacking
clock-frequency, specify a reasonable value to suppress this warning.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
index 62ad67370d2b..c6e2c571b452 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
+++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
@@ -499,12 +499,14 @@ lt9611_out: endpoint {
&i2c11 {
/* On Low speed expansion */
+ clock-frequency = <100000>;
label = "LS-I2C1";
status = "okay";
};
&i2c14 {
/* On Low speed expansion */
+ clock-frequency = <100000>;
label = "LS-I2C0";
status = "okay";
};
--
2.35.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 0/3] arm64: dts: qcom: sdm845-db845: Some i2c fixes
2022-07-17 3:44 [PATCH 0/3] arm64: dts: qcom: sdm845-db845: Some i2c fixes Bjorn Andersson
` (2 preceding siblings ...)
2022-07-17 3:44 ` [PATCH 3/3] arm64: dts: qcom: sdm845-db845c: Specify a i2c bus clocks Bjorn Andersson
@ 2022-07-18 5:31 ` Vinod Koul
2022-07-19 4:47 ` Bjorn Andersson
4 siblings, 0 replies; 6+ messages in thread
From: Vinod Koul @ 2022-07-18 5:31 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, linux-arm-msm,
devicetree, linux-kernel
On 16-07-22, 20:44, Bjorn Andersson wrote:
> On my db845c (perhaps old firmware?) i2c14 is using GPI, so this enables that.
> And while I'm touching it I added dma properties to all the geni i2c and spi
> nodes and specified a default clock to avoid two warnings in the log during
> boot.
Reviewed-by: Vinod Koul <vkoul@kernel.org>
--
~Vinod
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 0/3] arm64: dts: qcom: sdm845-db845: Some i2c fixes
2022-07-17 3:44 [PATCH 0/3] arm64: dts: qcom: sdm845-db845: Some i2c fixes Bjorn Andersson
` (3 preceding siblings ...)
2022-07-18 5:31 ` [PATCH 0/3] arm64: dts: qcom: sdm845-db845: Some i2c fixes Vinod Koul
@ 2022-07-19 4:47 ` Bjorn Andersson
4 siblings, 0 replies; 6+ messages in thread
From: Bjorn Andersson @ 2022-07-19 4:47 UTC (permalink / raw)
To: bjorn.andersson, Konrad Dybcio
Cc: robh+dt, vinod.koul, linux-arm-msm, linux-kernel, devicetree,
krzysztof.kozlowski+dt
On Sat, 16 Jul 2022 20:44:00 -0700, Bjorn Andersson wrote:
> On my db845c (perhaps old firmware?) i2c14 is using GPI, so this enables that.
> And while I'm touching it I added dma properties to all the geni i2c and spi
> nodes and specified a default clock to avoid two warnings in the log during
> boot.
>
> Bjorn Andersson (3):
> arm64: dts: qcom: sdm845: Fill in GENI DMA references
> arm64: dts: qcom: sdm845-db845c: Enable gpi_dma1
> arm64: dts: qcom: sdm845-db845c: Specify a i2c bus clocks
>
> [...]
Applied, thanks!
[1/3] arm64: dts: qcom: sdm845: Fill in GENI DMA references
commit: 0f064ae7cf703b0527de3a0608ef88548fdb5d9d
[2/3] arm64: dts: qcom: sdm845-db845c: Enable gpi_dma1
commit: 79cfb1124af9b55e082d9d3efbefa4d3fc8b3cdc
[3/3] arm64: dts: qcom: sdm845-db845c: Specify a i2c bus clocks
commit: 746ff2bfcec78cfd522b2a490e7207c3fe836634
Best regards,
--
Bjorn Andersson <bjorn.andersson@linaro.org>
^ permalink raw reply [flat|nested] 6+ messages in thread
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2022-07-17 3:44 [PATCH 0/3] arm64: dts: qcom: sdm845-db845: Some i2c fixes Bjorn Andersson
2022-07-17 3:44 ` [PATCH 1/3] arm64: dts: qcom: sdm845: Fill in GENI DMA references Bjorn Andersson
2022-07-17 3:44 ` [PATCH 2/3] arm64: dts: qcom: sdm845-db845c: Enable gpi_dma1 Bjorn Andersson
2022-07-17 3:44 ` [PATCH 3/3] arm64: dts: qcom: sdm845-db845c: Specify a i2c bus clocks Bjorn Andersson
2022-07-18 5:31 ` [PATCH 0/3] arm64: dts: qcom: sdm845-db845: Some i2c fixes Vinod Koul
2022-07-19 4:47 ` Bjorn Andersson
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