Re: [PATCH 6/8] phy: allwinner: phy-sun6i-mipi-dphy: Set enable bit last

[Paul Kocialkowski <paul.kocialkowski@bootlin.com>]

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Hi Samuel,

On Fri 12 Aug 22, 02:56, Samuel Holland wrote:
> The A100 variant of the DPHY requires configuring the analog registers
> before setting the global enable bit. Since this order also works on the
> other variants, always use it, to minimize the differences between them.

Did you get a chance to actually test this with either DSI/CSI-2 hardware?
I vaguely remember that the order mattered. Do you have an idea of what the
Allwinner BSP does too?

Otherwise I could give it a try, at least with my MIPI CSI-2 setup
that uses the driver.

Cheers,

Pau

> Signed-off-by: Samuel Holland <samuel@sholland.org>
> ---
> 
>  drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> index 625c6e1e9990..9698d68d0db7 100644
> --- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> +++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> @@ -183,10 +183,6 @@ static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
>  		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(3) |
>  		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(3));
>  
> -	regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG,
> -		     SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) |
> -		     SUN6I_DPHY_GCTL_EN);
> -
>  	regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
>  		     SUN6I_DPHY_ANA0_REG_PWS |
>  		     SUN6I_DPHY_ANA0_REG_DMPC |
> @@ -244,6 +240,10 @@ static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
>  			   SUN6I_DPHY_ANA2_EN_P2S_CPU_MASK,
>  			   SUN6I_DPHY_ANA2_EN_P2S_CPU(lanes_mask));
>  
> +	regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG,
> +		     SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) |
> +		     SUN6I_DPHY_GCTL_EN);
> +
>  	return 0;
>  }
>  
> -- 
> 2.35.1
> 

-- 
Paul Kocialkowski, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com

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