From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F17C4C00140 for ; Mon, 15 Aug 2022 08:54:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231558AbiHOIyY (ORCPT ); Mon, 15 Aug 2022 04:54:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45794 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229498AbiHOIyY (ORCPT ); Mon, 15 Aug 2022 04:54:24 -0400 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A39D120BF4 for ; Mon, 15 Aug 2022 01:54:22 -0700 (PDT) Received: by mail-wr1-x42c.google.com with SMTP id e27so3606149wra.11 for ; Mon, 15 Aug 2022 01:54:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc; bh=iidtuaE8s+DCGaLOdt5ZKpKtusZpSzaBfJPqYoME7mI=; b=UIl8fcznIabQRcconZq+r+VdCAMu5ynRV5wJw56zB6P8OflqhLPyyuLkzBWh3Aw54z AqXWK9SbrysFB8qbsSyQ6bN+EkJnaFnC+vC9pgVvZQcGvc6XsqocGWTXK2UmcICHX/1A wSSS1y/b64RblHHpj/qzpoc+Nforg0AzeBQ04wiyH/AYTx763jN3Mtf+Ea8rZTOcxUud gJkDE3fEyW78naqeAr0Eol/C9Z1zV2RmuAMvWeD+z6mVqXyjI05UReYGojWDsLYuuAK9 H0QyFVyZL+9xwLRxO51/TiAPf4HjjInFGcJbJiwys03F0jg49eoq67b7X9EJYPCV7VwS V9ww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc; bh=iidtuaE8s+DCGaLOdt5ZKpKtusZpSzaBfJPqYoME7mI=; b=g50iicV4vk7I8WV9LimkR9EyMdlrzs2MwL6c2RQEYyW1aG5DP5tYuEPwCEGx1Yj/Ey XI3FQTcgnOiRRMaHemVCuIpuVcyaNrxHXOIGEriC0ntp8Nyvs6tr+di2jfRKR/OvS4LY sxmqm5LZxFLoYx8YUX40enXOVvMBIrrBRJ5HShk2xqIhxMeR82J43Wook5CiQGd5f3W2 607OqsuCEJ4FNBnmsmi9LBrBqkU6iFLUq93c8feSc4s1poPWImj1JxyNdjh9Cd6fR7Zm gvfMGUw1LeWe9MspVyHnlJxEiJrQlJjgnixhiaE3C5iwpsSV4jW6WP8AaEjv5389sFFy 2sww== X-Gm-Message-State: ACgBeo3GJFc8DZdXl162x0I9/kHADJU6BluV/9fewW8r29bkvZAydK3R p5vp36Pjo/aRqqYev0K7gxnObw== X-Google-Smtp-Source: AA6agR6YiDuscaXokbybBjZAvFR/jtnraP/BMqaoEW68eHcfYMpWEyoDGJ/2ThjvAxYRi0M7YVM0Ew== X-Received: by 2002:a5d:4705:0:b0:21f:3890:8619 with SMTP id y5-20020a5d4705000000b0021f38908619mr7976536wrq.104.1660553661190; Mon, 15 Aug 2022 01:54:21 -0700 (PDT) Received: from linaro.org ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id a16-20020a056000051000b00223b8168b15sm6655136wrf.66.2022.08.15.01.54.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Aug 2022 01:54:20 -0700 (PDT) Date: Mon, 15 Aug 2022 11:54:18 +0300 From: Abel Vesa To: "Peng Fan (OSS)" Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, shawnguo@kernel.org, s.hauer@pengutronix.de, abelvesa@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Peng Fan , Ye Li , Jacky Bai Subject: Re: [PATCH V2 3/8] clk: imx: clk-composite-93: check slice busy Message-ID: References: <20220815013039.474970-1-peng.fan@oss.nxp.com> <20220815013039.474970-4-peng.fan@oss.nxp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220815013039.474970-4-peng.fan@oss.nxp.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 22-08-15 09:30:34, Peng Fan (OSS) wrote: > From: Peng Fan > > i.MX93 CCM ROOT STAT register has a SLICE_BUSY bit: > indication for clock generation logic is applying new setting. > 0b - Clock generation logic is not busy. > 1b - Clock generation logic is applying new setting. > > So when set parent/rate/gate, need check this bit. > > Introduce specific ops to do the work. > > Signed-off-by: Peng Fan > Reviewed-by: Ye Li > Reviewed-by: Jacky Bai Reviewed-by: Abel Vesa > --- > drivers/clk/imx/clk-composite-93.c | 163 ++++++++++++++++++++++++++++- > 1 file changed, 160 insertions(+), 3 deletions(-) > > diff --git a/drivers/clk/imx/clk-composite-93.c b/drivers/clk/imx/clk-composite-93.c > index b44619aa5ca5..19f4037e6cca 100644 > --- a/drivers/clk/imx/clk-composite-93.c > +++ b/drivers/clk/imx/clk-composite-93.c > @@ -9,20 +9,176 @@ > #include > #include > #include > +#include > #include > > #include "clk.h" > > +#define TIMEOUT_US 500U > + > #define CCM_DIV_SHIFT 0 > #define CCM_DIV_WIDTH 8 > #define CCM_MUX_SHIFT 8 > #define CCM_MUX_MASK 3 > #define CCM_OFF_SHIFT 24 > +#define CCM_BUSY_SHIFT 28 > > +#define STAT_OFFSET 0x4 > #define AUTHEN_OFFSET 0x30 > #define TZ_NS_SHIFT 9 > #define TZ_NS_MASK BIT(9) > > +static int imx93_clk_composite_wait_ready(struct clk_hw *hw, void __iomem *reg) > +{ > + int ret; > + u32 val; > + > + ret = readl_poll_timeout_atomic(reg + STAT_OFFSET, val, !(val & BIT(CCM_BUSY_SHIFT)), > + 0, TIMEOUT_US); > + if (ret) > + pr_err("Slice[%s] busy timeout\n", clk_hw_get_name(hw)); > + > + return ret; > +} > + > +static void imx93_clk_composite_gate_endisable(struct clk_hw *hw, int enable) > +{ > + struct clk_gate *gate = to_clk_gate(hw); > + unsigned long flags; > + u32 reg; > + > + if (gate->lock) > + spin_lock_irqsave(gate->lock, flags); > + > + reg = readl(gate->reg); > + > + if (enable) > + reg &= ~BIT(gate->bit_idx); > + else > + reg |= BIT(gate->bit_idx); > + > + writel(reg, gate->reg); > + > + imx93_clk_composite_wait_ready(hw, gate->reg); > + > + if (gate->lock) > + spin_unlock_irqrestore(gate->lock, flags); > +} > + > +static int imx93_clk_composite_gate_enable(struct clk_hw *hw) > +{ > + imx93_clk_composite_gate_endisable(hw, 1); > + > + return 0; > +} > + > +static void imx93_clk_composite_gate_disable(struct clk_hw *hw) > +{ > + imx93_clk_composite_gate_endisable(hw, 0); > +} > + > +static const struct clk_ops imx93_clk_composite_gate_ops = { > + .enable = imx93_clk_composite_gate_enable, > + .disable = imx93_clk_composite_gate_disable, > + .is_enabled = clk_gate_is_enabled, > +}; > + > +static unsigned long > +imx93_clk_composite_divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) > +{ > + return clk_divider_ops.recalc_rate(hw, parent_rate); > +} > + > +static long > +imx93_clk_composite_divider_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) > +{ > + return clk_divider_ops.round_rate(hw, rate, prate); > +} > + > +static int > +imx93_clk_composite_divider_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) > +{ > + return clk_divider_ops.determine_rate(hw, req); > +} > + > +static int imx93_clk_composite_divider_set_rate(struct clk_hw *hw, unsigned long rate, > + unsigned long parent_rate) > +{ > + struct clk_divider *divider = to_clk_divider(hw); > + int value; > + unsigned long flags = 0; > + u32 val; > + int ret; > + > + value = divider_get_val(rate, parent_rate, divider->table, divider->width, divider->flags); > + if (value < 0) > + return value; > + > + if (divider->lock) > + spin_lock_irqsave(divider->lock, flags); > + > + val = readl(divider->reg); > + val &= ~(clk_div_mask(divider->width) << divider->shift); > + val |= (u32)value << divider->shift; > + writel(val, divider->reg); > + > + ret = imx93_clk_composite_wait_ready(hw, divider->reg); > + > + if (divider->lock) > + spin_unlock_irqrestore(divider->lock, flags); > + > + return ret; > +} > + > +static const struct clk_ops imx93_clk_composite_divider_ops = { > + .recalc_rate = imx93_clk_composite_divider_recalc_rate, > + .round_rate = imx93_clk_composite_divider_round_rate, > + .determine_rate = imx93_clk_composite_divider_determine_rate, > + .set_rate = imx93_clk_composite_divider_set_rate, > +}; > + > +static u8 imx93_clk_composite_mux_get_parent(struct clk_hw *hw) > +{ > + return clk_mux_ops.get_parent(hw); > +} > + > +static int imx93_clk_composite_mux_set_parent(struct clk_hw *hw, u8 index) > +{ > + struct clk_mux *mux = to_clk_mux(hw); > + u32 val = clk_mux_index_to_val(mux->table, mux->flags, index); > + unsigned long flags = 0; > + u32 reg; > + int ret; > + > + if (mux->lock) > + spin_lock_irqsave(mux->lock, flags); > + > + reg = readl(mux->reg); > + reg &= ~(mux->mask << mux->shift); > + val = val << mux->shift; > + reg |= val; > + writel(reg, mux->reg); > + > + ret = imx93_clk_composite_wait_ready(hw, mux->reg); > + > + if (mux->lock) > + spin_unlock_irqrestore(mux->lock, flags); > + > + return ret; > +} > + > +static int > +imx93_clk_composite_mux_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) > +{ > + return clk_mux_ops.determine_rate(hw, req); > +} > + > +static const struct clk_ops imx93_clk_composite_mux_ops = { > + .get_parent = imx93_clk_composite_mux_get_parent, > + .set_parent = imx93_clk_composite_mux_set_parent, > + .determine_rate = imx93_clk_composite_mux_determine_rate, > +}; > + > struct clk_hw *imx93_clk_composite_flags(const char *name, const char * const *parent_names, > int num_parents, void __iomem *reg, > unsigned long flags) > @@ -74,9 +230,10 @@ struct clk_hw *imx93_clk_composite_flags(const char *name, const char * const *p > gate->flags = CLK_GATE_SET_TO_DISABLE; > > hw = clk_hw_register_composite(NULL, name, parent_names, num_parents, > - mux_hw, &clk_mux_ops, div_hw, > - &clk_divider_ops, gate_hw, > - &clk_gate_ops, flags | CLK_SET_RATE_NO_REPARENT); > + mux_hw, &imx93_clk_composite_mux_ops, div_hw, > + &imx93_clk_composite_divider_ops, gate_hw, > + &imx93_clk_composite_gate_ops, > + flags | CLK_SET_RATE_NO_REPARENT); > } > > if (IS_ERR(hw)) > -- > 2.37.1 >