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[98.239.145.235]) by smtp.gmail.com with ESMTPSA id fb6-20020a05622a480600b00342fcdc2d46sm8312778qtb.56.2022.08.15.08.00.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Aug 2022 08:00:17 -0700 (PDT) Date: Mon, 15 Aug 2022 11:00:16 -0400 From: Brian Masney To: Parikshit Pareek Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Andrew Halaney Subject: Re: [PATCH v3 2/3] arm64: dts: qcom: sa8295p: move common nodes to dtsi Message-ID: References: <20220812165453.11608-1-quic_ppareek@quicinc.com> <20220812165453.11608-3-quic_ppareek@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220812165453.11608-3-quic_ppareek@quicinc.com> User-Agent: Mutt/2.2.6 (2022-06-05) Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Fri, Aug 12, 2022 at 10:24:52PM +0530, Parikshit Pareek wrote: > There are many ADP boards with lot of common features. Move common > nodes to sa8540p-adp.dtsi file. This will be base for many ADP boards > to be introduced in near future. > > Signed-off-by: Parikshit Pareek > --- > arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 377 +-------------------- > arch/arm64/boot/dts/qcom/sa8540p-adp.dtsi | 384 ++++++++++++++++++++++ > 2 files changed, 385 insertions(+), 376 deletions(-) > create mode 100644 arch/arm64/boot/dts/qcom/sa8540p-adp.dtsi My understanding of the sa8295p auto board is that it has a single SoC. The sa8540p auto board has dual SoCs (same SoC variant as the sa8295p) with a PCIe interconnect between the two SoCs. I hate to bike shed on the name but perhaps the name sa8295p would be more fitting like you had it in v2, but ultimately leave it up to the maintainers on which name to use here. How will the dual SoCs in the sa8540p be represented in device tree? I assume just document the PCI endpoint to the other SoC? Then run the two SoCs independently and let them see the other SoC through PCIe? Brian