From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2100DC433F5 for ; Sat, 1 Oct 2022 11:15:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229451AbiJALPG (ORCPT ); Sat, 1 Oct 2022 07:15:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40176 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229436AbiJALPE (ORCPT ); Sat, 1 Oct 2022 07:15:04 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5586E3BC68; Sat, 1 Oct 2022 04:14:58 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 3EE9BB80DC6; Sat, 1 Oct 2022 11:14:57 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 353DDC433C1; Sat, 1 Oct 2022 11:14:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1664622895; bh=06zggjHa8kTBjzns75XbCc45MBQbTfIwinmOKApewzQ=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=qK4LDBiC9y8EK1KCnuG2t8wKBHZ4BZ9Irq+tLn1Ev1VSRh2ywrpnAkWNyu+QcS0r0 +0LnGgmf8aFMyCNAKp7+RKkB/REOYW1RfhMeG8o7CN01Vx/+fqz1sDjzDlbrKvMpAG Da7F1ejhJDbzaDZoO92IjdRPwSriLDZfp0Ozlc2LquSpF5tknkQl1dqTvKA+AZVU+E WINvoI56EqsTQSOfvVRAvXFB6Bi5fLGkGClbKZ33b8lFKizqd/z1FHJ9XLx7ovgjdo cQOWd4eJAUDqXPNwWCNdwx41cryB8tNvpZ3seLIF5ATBAB/myHlj/PlkJYFpZVu3Kd U7/aTDryQ8tvw== Date: Sat, 1 Oct 2022 12:14:49 +0100 From: Conor Dooley To: Hal Feng Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner , Marc Zyngier , Philipp Zabel , Stephen Boyd , Michael Turquette , Linus Walleij , Emil Renner Berthing , linux-kernel@vger.kernel.org Subject: Re: [PATCH v1 28/30] RISC-V: Add StarFive JH7110 VisionFive2 board device tree Message-ID: References: <20220929143225.17907-1-hal.feng@linux.starfivetech.com> <20220930075353.6842-1-hal.feng@linux.starfivetech.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20220930075353.6842-1-hal.feng@linux.starfivetech.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Fri, Sep 30, 2022 at 03:53:53PM +0800, Hal Feng wrote: > From: Emil Renner Berthing > > Add a minimal device tree for StarFive JH7110 VisionFive2 board. > Support booting and basic clock/reset/pinctrl/uart drivers. > I would like to see a link to the publicly available datasheet or documentation for the board (and for the SoC in patch 28) please. > Signed-off-by: Emil Renner Berthing > Signed-off-by: Jianlong Huang Ditto from patch 28 re: the SoB chain. > Signed-off-by: Hal Feng > --- > diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts > new file mode 100644 > index 000000000000..6b9fe32c7eac > --- /dev/null > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts > @@ -0,0 +1,91 @@ > +// SPDX-License-Identifier: GPL-2.0 OR MIT > +/* > + * Copyright (C) 2022 StarFive Technology Co., Ltd. > + * Copyright (C) 2022 Emil Renner Berthing > + */ > + > +/dts-v1/; > +#include "jh7110.dtsi" > +#include > +#include > + > +/ { > + model = "StarFive VisionFive V2"; > + compatible = "starfive,visionfive-v2", "starfive,jh7110"; > + > + aliases { > + serial0 = &uart0; > + }; Should we also have a chosen node here? > + > + cpus { > + timebase-frequency = <4000000>; > + }; > + > + memory@40000000 { > + device_type = "memory"; > + reg = <0x0 0x40000000 0x1 0x0>; What is going to happen to the 2 GB variant if they attempt to use this devicetree? > + }; > + > + reserved-memory { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + linux,cma { > + compatible = "shared-dma-pool"; > + reusable; > + size = <0x0 0x20000000>; > + alignment = <0x0 0x1000>; > + alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>; > + linux,cma-default; > + }; > + > + e24_mem: e24@c0000000 { I had a conversation previously with Icenowy [0] about the e24 on the jh7100 that didn't really come to a conclusion about how to represent it there - but looks like you've decided that it should be a remoteproc for the jh7100? Is this another situation where peripherals appear at different addresses for the e24 compared to the u74s? Or has that changed for the jh7100, and really the e24 should be described in the CPUs node? If it is the latter, you can pick the first patch from [0] into your series. 0 - https://lore.kernel.org/linux-riscv/e8543838cd221ab6699da16c985eed7514daa786.camel@icenowy.me/ > + reg = <0x0 0xc0110000 0x0 0xf0000>; > + no-map; > + }; > + > + xrp_reserved: xrpbuffer@f0000000 { "Following the generic-names recommended practice, node names should reflect the purpose of the node (ie. “framebuffer” or “dma-pool”)." I tried googling around for an explanation for what the xrp was, and all I could find was this out-of-tree text binding: https://github.com/foss-xtensa/xrp/blob/master/xrp-kernel/cdns%2Cxrp-hw-simple%2Cv1.txt Thanks, Conor. > + reg = <0x0 0xf0000000 0x0 0x01ffffff>, > + <0x0 0xf2000000 0x0 0x00001000>, > + <0x0 0xf2001000 0x0 0x00fff000>, > + <0x0 0xf3000000 0x0 0x00001000>; > + }; > + > + }; > + > + gpio-restart { > + compatible = "gpio-restart"; > + gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; > + priority = <224>; > + }; > +}; > + > +&gpio { > + uart0_pins: uart0-pins { > + uart0-pins-tx { > + starfive,pins = ; > + starfive,pin-ioconfig = ; > + starfive,pin-gpio-dout = ; > + starfive,pin-gpio-doen = ; > + }; > + > + uart0-pins-rx { > + starfive,pins = ; > + starfive,pinmux = ; > + starfive,pin-ioconfig = ; > + starfive,pin-gpio-doen = ; > + starfive,pin-gpio-din = ; > + }; > + }; > +}; > + > +&osc { > + clock-frequency = <24000000>; > +}; > + > +&uart0 { > + pinctrl-names = "default"; > + pinctrl-0 = <&uart0_pins>; > + status = "okay"; > +}; > -- > 2.17.1 >