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[69.109.179.158]) by smtp.gmail.com with ESMTPSA id eq24-20020a056870a91800b0011d02a3fa63sm1604819oab.14.2022.10.01.11.34.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 11:35:00 -0700 (PDT) Date: Sat, 1 Oct 2022 14:34:57 -0400 From: William Breathitt Gray To: Biju Das Cc: William Breathitt Gray , Rob Herring , Krzysztof Kozlowski , Philipp Zabel , Michael Turquette , Stephen Boyd , Geert Uytterhoeven , Lee Jones , Uwe =?iso-8859-1?Q?Kleine-K=F6nig?= , "linux-pwm@vger.kernel.org" , "linux-iio@vger.kernel.org" , "linux-clk@vger.kernel.org" , "devicetree@vger.kernel.org" , Chris Paterson , Biju Das , Prabhakar Mahadev Lad , "linux-renesas-soc@vger.kernel.org" Subject: Re: [PATCH RFC 0/8] Add RZ/G2L MTU3a MFD and Counter driver Message-ID: References: <20220926132114.60396-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="jIsWhV+AUqJpBfeK" Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org --jIsWhV+AUqJpBfeK Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Sat, Oct 01, 2022 at 06:03:37PM +0000, Biju Das wrote: > > What is the configuration when 32-bit phase counting mode is selected? >=20 > LWA Bit (MTU1/MTU2 Combination Longword Access Control) needs to set for = 32-bit phase counting mode. >=20 > b0 LWA 0 R/W MTU1/MTU2 Combination Longword Access Control > 0: 16-bit access is enabled. > 1: 32-bit access is enabled. >=20 > > Does MTCLKA and MTCLKB serve as the counting signals in this case, >=20 > For 16-bit and 32-bit counting signals same. We can set=20 >=20 > 1) MTU 1 and MTU2 signals as MTCLKA and MTCLKB >=20 > Or=20 >=20 > 2) MTU 1 signal as MTCLKA and MTCLKB and MTU2 signals as MTCLKC and MTCLKD I'm having trouble understanding this case. If 32-bit access is enabled by setting the LWA bit, and the MTU1 signals are configured as MTCLKA and MTCLKB while at the same time the MTU2 signals are configured as MTCLKC and MTCLKD, how is the 32-bit count value determined -- wouldn't MTU1 and MTU2 be counting independently if they each had separate input clocks fed to them? William Breathitt Gray >=20 >=20 > b1 PHCKSEL 1 R/W External Input Phase Clock Select > Selects the external clock pin for phase counting mode. > 0: MTCLKA and MTCLKB are selected for the external phase clock. > 1: MTCLKC and MTCLKD are selected for the external phase clock >=20 > > with overflows on the MTU1 register incrementing the MTU2 register? >=20 > No. that won't happen as we need to use different register for Long word = access >=20 > These are the regiters used > 16-bit:- TCNT{MTU1,MTU2}, TGRA{MTU1,MTU2}, and TGRB{MTU1,MTU2}, > 32-bit:- MTU1.TCNT_1_LW, MTU1.TGRA_1_LW and MTU1.TGRB_1_LW >=20 > Counter in MTU1 MTU1.TCNT Word MTU1.TCNT_1_LW Longword > Counter in MTU2 MTU2.TCNT Word >=20 > General register A in MTU1 MTU1.TGRA Word MTU1.TGRA_1_LW Longword > General register A in MTU2 MTU2.TGRA Word >=20 > General register B in MTU1 MTU1.TGRB Word MTU1.TGRB_1_LW Longword > General register B in MTU2 MTU2.TGRB Word >=20 > Cheers, > Biju --jIsWhV+AUqJpBfeK Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEARYKAB0WIQSNN83d4NIlKPjon7a1SFbKvhIjKwUCYziIUQAKCRC1SFbKvhIj K13sAP42H60oOCvp2BKUOKE2xETOT8PYhzcrCTmDBS3AIhPiigEApFKjur1P+nb3 xzbq/3l8xB60GCtwhLhgAKnrQxNCqgQ= =fYgv -----END PGP SIGNATURE----- --jIsWhV+AUqJpBfeK--