From: Lorenzo Pieralisi <lpieralisi@kernel.org>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: Marc Zyngier <maz@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>,
Sascha Bischoff <sascha.bischoff@arm.com>,
Timothy Hayes <timothy.hayes@arm.com>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH 22/24] irqchip/gic-v5: Add GICv5 ITS support
Date: Wed, 9 Apr 2025 15:37:04 +0200 [thread overview]
Message-ID: <Z/Z4AFYNQmxTApYi@lpieralisi> (raw)
In-Reply-To: <87tt6xtwnp.ffs@tglx>
On Wed, Apr 09, 2025 at 01:13:46PM +0200, Thomas Gleixner wrote:
> On Tue, Apr 08 2025 at 12:50, Lorenzo Pieralisi wrote:
> >
> > +void gicv5_irs_syncr(void)
> > +{
> > + u32 syncr;
> > + u32 statusr;
> > + int ret;
> > + struct gicv5_irs_chip_data *irs_data;
> > +
> > + irs_data = list_first_entry_or_null(&irs_nodes,
> > + struct gicv5_irs_chip_data, entry);
> > + if (WARN_ON(!irs_data))
> > + return;
> > +
> > + syncr = FIELD_PREP(GICV5_IRS_SYNCR_SYNC, 1);
> > + irs_writel(irs_data, syncr, GICV5_IRS_SYNCR);
> > +
> > + ret = readl_relaxed_poll_timeout_atomic(
> > + irs_data->irs_base + GICV5_IRS_SYNC_STATUSR, statusr,
> > + FIELD_GET(GICV5_IRS_SYNC_STATUSR_IDLE, statusr), 1,
> > + USEC_PER_SEC);
> > +
> > + if (ret == -ETIMEDOUT)
> > + pr_err_ratelimited("SYNCR timeout...\n");
>
> This timeout poll thing looks very familiar by now. Third variant :)
>
> > +static int gicv5_its_wait_for_invalidation(struct gicv5_its_chip_data *its)
> > +{
> > + int ret;
> > + u32 statusr;
> > +
> > + ret = readl_relaxed_poll_timeout_atomic(
> > + its->its_base + GICV5_ITS_STATUSR, statusr,
> > + FIELD_GET(GICV5_ITS_STATUSR_IDLE, statusr), 1,
> > + USEC_PER_SEC);
> > +
> > + if (ret == -ETIMEDOUT)
> > + pr_err_ratelimited("STATUSR timeout...\n");
> > +
> > + return ret;
> > +}
>
> And number four follows suit :)
>
> > +
> > +static void gicv5_its_syncr(struct gicv5_its_chip_data *its,
> > + struct gicv5_its_dev *its_dev)
> > +{
> > + int ret;
> > + u64 syncr;
> > + u32 statusr;
> > +
> > + syncr = FIELD_PREP(GICV5_ITS_SYNCR_SYNC, 1) |
> > + FIELD_PREP(GICV5_ITS_SYNCR_DEVICEID, its_dev->device_id);
> > +
> > + its_writeq(its, syncr, GICV5_ITS_SYNCR);
> > +
> > + ret = readl_relaxed_poll_timeout_atomic(
> > + its->its_base + GICV5_ITS_SYNC_STATUSR, statusr,
> > + FIELD_GET(GICV5_ITS_SYNC_STATUSR_IDLE, statusr), 1,
> > + USEC_PER_SEC);
> > +
> > + if (ret == -ETIMEDOUT)
> > + pr_err_ratelimited("SYNCR timeout...\n");
> > +}
>
> Along with #5
No question about it, I will consolidate them as much as I can, I
noticed while implementing them then focused on getting the driver
functionality in place and forgot to create a single function,
apologies.
Thanks,
Lorenzo
next prev parent reply other threads:[~2025-04-09 13:37 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-08 10:49 [PATCH 00/24] Arm GICv5: Host driver implementation Lorenzo Pieralisi
2025-04-08 10:50 ` [PATCH 01/24] Documentation: devicetree: bindings: Add GICv5 DT bindings Lorenzo Pieralisi
2025-04-08 12:26 ` Rob Herring (Arm)
2025-04-08 14:58 ` Lorenzo Pieralisi
2025-04-08 15:07 ` Rob Herring
2025-04-09 8:20 ` Lorenzo Pieralisi
2025-04-08 10:50 ` [PATCH 02/24] arm64/sysreg: Add GCIE field to ID_AA64PFR2_EL1 Lorenzo Pieralisi
2025-04-08 10:50 ` [PATCH 03/24] arm64/sysreg: Add ICC_PPI_PRIORITY<n>_EL1 Lorenzo Pieralisi
2025-04-08 10:50 ` [PATCH 04/24] arm64/sysreg: Add ICC_ICSR_EL1 Lorenzo Pieralisi
2025-04-08 10:50 ` [PATCH 05/24] arm64/sysreg: Add ICC_PPI_HMR<n>_EL1 Lorenzo Pieralisi
2025-04-08 10:50 ` [PATCH 06/24] arm64/sysreg: Add ICC_PPI_ENABLER<n>_EL1 Lorenzo Pieralisi
2025-04-08 10:50 ` [PATCH 07/24] arm64/sysreg: Add ICC_PPI_{C/S}ACTIVER<n>_EL1 Lorenzo Pieralisi
2025-04-08 10:50 ` [PATCH 08/24] arm64/sysreg: Add ICC_PPI_{C/S}PENDR<n>_EL1 Lorenzo Pieralisi
2025-04-08 10:50 ` [PATCH 09/24] arm64/sysreg: Add ICC_CR0_EL1 Lorenzo Pieralisi
2025-04-08 10:50 ` [PATCH 10/24] arm64/sysreg: Add ICC_PCR_EL1 Lorenzo Pieralisi
2025-04-08 10:50 ` [PATCH 11/24] arm64/sysreg: Add ICC_IDR0_EL1 Lorenzo Pieralisi
2025-04-08 10:50 ` [PATCH 12/24] arm64/sysreg: Add ICH_HFGRTR_EL2 Lorenzo Pieralisi
2025-04-08 10:50 ` [PATCH 13/24] arm64/sysreg: Add ICH_HFGWTR_EL2 Lorenzo Pieralisi
2025-04-09 7:48 ` Arnd Bergmann
2025-04-09 8:51 ` Lorenzo Pieralisi
2025-04-08 10:50 ` [PATCH 14/24] arm64/sysreg: Add ICH_HFGITR_EL2 Lorenzo Pieralisi
2025-04-08 10:50 ` [PATCH 15/24] arm64: Disable GICv5 read/write/instruction traps Lorenzo Pieralisi
2025-04-08 10:50 ` [PATCH 16/24] arm64: cpucaps: Add GCIE capability Lorenzo Pieralisi
2025-04-08 11:26 ` Mark Rutland
2025-04-08 15:02 ` Lorenzo Pieralisi
2025-04-08 10:50 ` [PATCH 17/24] arm64: smp: Support non-SGIs for IPIs Lorenzo Pieralisi
2025-04-08 10:50 ` [PATCH 18/24] irqchip/gic-v5: Add GICv5 PPI support Lorenzo Pieralisi
2025-04-08 21:42 ` Thomas Gleixner
2025-04-09 7:30 ` Lorenzo Pieralisi
2025-04-17 14:49 ` Lorenzo Pieralisi
2025-04-11 17:06 ` Lorenzo Pieralisi
2025-04-08 10:50 ` [PATCH 19/24] irqchip/gic-v5: Add GICv5 IRS/SPI support Lorenzo Pieralisi
2025-04-09 7:02 ` Thomas Gleixner
2025-04-09 7:40 ` Lorenzo Pieralisi
2025-04-08 10:50 ` [PATCH 20/24] irqchip/gic-v5: Add GICv5 LPI/IPI support Lorenzo Pieralisi
2025-04-09 8:23 ` Arnd Bergmann
2025-04-09 10:11 ` Lorenzo Pieralisi
2025-04-09 10:56 ` Arnd Bergmann
2025-04-09 13:15 ` Lorenzo Pieralisi
2025-04-09 14:25 ` Arnd Bergmann
2025-04-18 9:21 ` Lorenzo Pieralisi
2025-04-09 8:27 ` Thomas Gleixner
2025-04-09 10:30 ` Lorenzo Pieralisi
2025-04-11 9:26 ` Lorenzo Pieralisi
2025-04-11 9:55 ` Thomas Gleixner
2025-04-11 12:37 ` Lorenzo Pieralisi
2025-04-12 13:01 ` Liam R. Howlett
2025-04-14 8:26 ` Lorenzo Pieralisi
2025-04-14 14:37 ` Liam R. Howlett
2025-04-15 8:08 ` Lorenzo Pieralisi
2025-04-08 10:50 ` [PATCH 21/24] irqchip/gic-v5: Enable GICv5 SMP booting Lorenzo Pieralisi
2025-04-08 10:50 ` [PATCH 22/24] irqchip/gic-v5: Add GICv5 ITS support Lorenzo Pieralisi
2025-04-09 11:13 ` Thomas Gleixner
2025-04-09 13:37 ` Lorenzo Pieralisi [this message]
2025-04-09 18:57 ` Thomas Gleixner
2025-04-10 8:08 ` Lorenzo Pieralisi
2025-04-10 9:20 ` Thomas Gleixner
2025-04-08 10:50 ` [PATCH 23/24] irqchip/gic-v5: Add GICv5 IWB support Lorenzo Pieralisi
2025-04-08 10:50 ` [PATCH 24/24] arm64: Kconfig: Enable GICv5 Lorenzo Pieralisi
2025-04-09 13:44 ` kernel test robot
2025-04-09 14:04 ` Lorenzo Pieralisi
2025-04-09 14:07 ` Krzysztof Kozlowski
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=Z/Z4AFYNQmxTApYi@lpieralisi \
--to=lpieralisi@kernel.org \
--cc=catalin.marinas@arm.com \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=krzk+dt@kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=maz@kernel.org \
--cc=robh@kernel.org \
--cc=sascha.bischoff@arm.com \
--cc=tglx@linutronix.de \
--cc=timothy.hayes@arm.com \
--cc=will@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).