[PATCH 00/13] Update PHYTEC i.MX93 DTS

[PATCH 00/13] Update PHYTEC i.MX93 DTS

[Primoz Fiser]

Update i.MX93 device-tree sources in mainline for phyCORE-i.MX93 SoM and
phyBOARD-Segin-i.MX93 board with changes from the downstream kernel.

New SoM features:
 - PMIC support
 - EEPROM support
 - enhanced eMMC support
 - fix eMMC for ERR052021

New board features:
 - RTC support
 - CAN support
 - USB support
 - I2S audio support
 - 2nd Ethernet (EQOS interface)
 - enhanced SD-card support
 - fix SD-card for ERR052021

Primoz Fiser (13):
  arm64: dts: freescale: imx93-phycore-som: Add PMIC support
  arm64: dts: freescale: imx93-phycore-som: Add EEPROM support
  arm64: dts: freescale: imx93-phycore-som: Disable LED pull-up
  arm64: dts: freescale: imx93-phycore-som: Enhance eMMC pinctrl
  arm64: dts: freescale: imx93-phycore-som: Add eMMC no-1-8-v by default
  arm64: dts: freescale: imx93-phyboard-segin: Drop eMMC no-1-8-v flag
  arm64: dts: freescale: imx93-phyboard-segin: Disable SD-card
    write-protect
  arm64: dts: freescale: imx93-phyboard-segin: Fix SD-card pinctrl
  arm64: dts: freescale: imx93-phyboard-segin: Add RTC support
  arm64: dts: freescale: imx93-phyboard-segin: Add CAN support
  arm64: dts: freescale: imx93-phyboard-segin: Add USB support
  arm64: dts: freescale: imx93-phyboard-segin: Add I2S audio
  arm64: dts: freescale: imx93-phyboard-segin: Add EQOS Ethernet

 .../dts/freescale/imx93-phyboard-segin.dts    | 240 ++++++++++++++++--
 .../boot/dts/freescale/imx93-phycore-som.dtsi | 165 +++++++++++-
 2 files changed, 369 insertions(+), 36 deletions(-)

-- 
2.34.1

[PATCH 01/13] arm64: dts: freescale: imx93-phycore-som: Add PMIC support

[Primoz Fiser]

PMIC driver for PCA9451A used on phyCORE-i.MX93 SOM is available since
commit 5edeb7d31262 ("regulator: pca9450: add pca9451a support"). Add
support for it in the SOM device-tree.

Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
---
 .../boot/dts/freescale/imx93-phycore-som.dtsi | 97 +++++++++++++++++++
 1 file changed, 97 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
index 88c2657b50e6..507a71f9294b 100644
--- a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
@@ -72,6 +72,90 @@ ethphy1: ethernet-phy@1 {
 	};
 };
 
+/* I2C3 */
+&lpi2c3 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpi2c3>;
+	status = "okay";
+
+	pmic@25 {
+		compatible = "nxp,pca9451a";
+		reg = <0x25>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_pmic>;
+		interrupt-parent = <&gpio4>;
+		interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
+
+		regulators {
+			buck1: BUCK1 {
+				regulator-name = "VDD_SOC";
+				regulator-min-microvolt = <610000>;
+				regulator-max-microvolt = <950000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <3125>;
+			};
+
+			buck2: BUCK2 {
+				regulator-name = "VDDQ_0V6";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <600000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck4: BUCK4 {
+				regulator-name = "VDD_3V3_BUCK";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck5: BUCK5 {
+				regulator-name = "VDD_1V8";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck6: BUCK6 {
+				regulator-name = "VDD_1V1";
+				regulator-min-microvolt = <1100000>;
+				regulator-max-microvolt = <1100000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo1: LDO1 {
+				regulator-name = "PMIC_SNVS_1V8";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo4: LDO4 {
+				regulator-name = "VDD_0V8";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo5: LDO5 {
+				regulator-name = "NVCC_SD2";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
 /* eMMC */
 &usdhc1 {
 	pinctrl-names = "default";
@@ -108,6 +192,19 @@ MX93_PAD_I2C1_SDA__GPIO1_IO01		0x31e
 		>;
 	};
 
+	pinctrl_lpi2c3: lpi2c3grp {
+		fsl,pins = <
+			MX93_PAD_GPIO_IO28__LPI2C3_SDA		0x40000b9e
+			MX93_PAD_GPIO_IO29__LPI2C3_SCL		0x40000b9e
+		>;
+	};
+
+	pinctrl_pmic: pmicgrp {
+		fsl,pins = <
+			MX93_PAD_ENET2_RD3__GPIO4_IO27		0x31e
+		>;
+	};
+
 	pinctrl_usdhc1: usdhc1grp {
 		fsl,pins = <
 			MX93_PAD_SD1_CLK__USDHC1_CLK		0x179e
-- 
2.34.1

Re: [PATCH 01/13] arm64: dts: freescale: imx93-phycore-som: Add PMIC support

[Frank Li]

On Thu, Apr 10, 2025 at 11:02:39AM +0200, Primoz Fiser wrote:
> PMIC driver for PCA9451A used on phyCORE-i.MX93 SOM is available since
> commit 5edeb7d31262 ("regulator: pca9450: add pca9451a support"). Add
> support for it in the SOM device-tree.
>
> Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
> ---

Reviewed-by: Frank Li <Frank.Li@nxp.com>

>  .../boot/dts/freescale/imx93-phycore-som.dtsi | 97 +++++++++++++++++++
>  1 file changed, 97 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
> index 88c2657b50e6..507a71f9294b 100644
> --- a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
> @@ -72,6 +72,90 @@ ethphy1: ethernet-phy@1 {
>  	};
>  };
>
> +/* I2C3 */
> +&lpi2c3 {
> +	clock-frequency = <400000>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_lpi2c3>;
> +	status = "okay";
> +
> +	pmic@25 {
> +		compatible = "nxp,pca9451a";
> +		reg = <0x25>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_pmic>;
> +		interrupt-parent = <&gpio4>;
> +		interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
> +
> +		regulators {
> +			buck1: BUCK1 {
> +				regulator-name = "VDD_SOC";
> +				regulator-min-microvolt = <610000>;
> +				regulator-max-microvolt = <950000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +				regulator-ramp-delay = <3125>;
> +			};
> +
> +			buck2: BUCK2 {
> +				regulator-name = "VDDQ_0V6";
> +				regulator-min-microvolt = <600000>;
> +				regulator-max-microvolt = <600000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			buck4: BUCK4 {
> +				regulator-name = "VDD_3V3_BUCK";
> +				regulator-min-microvolt = <3300000>;
> +				regulator-max-microvolt = <3300000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			buck5: BUCK5 {
> +				regulator-name = "VDD_1V8";
> +				regulator-min-microvolt = <1800000>;
> +				regulator-max-microvolt = <1800000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			buck6: BUCK6 {
> +				regulator-name = "VDD_1V1";
> +				regulator-min-microvolt = <1100000>;
> +				regulator-max-microvolt = <1100000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			ldo1: LDO1 {
> +				regulator-name = "PMIC_SNVS_1V8";
> +				regulator-min-microvolt = <1800000>;
> +				regulator-max-microvolt = <1800000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			ldo4: LDO4 {
> +				regulator-name = "VDD_0V8";
> +				regulator-min-microvolt = <800000>;
> +				regulator-max-microvolt = <800000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			ldo5: LDO5 {
> +				regulator-name = "NVCC_SD2";
> +				regulator-min-microvolt = <1800000>;
> +				regulator-max-microvolt = <3300000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +		};
> +	};
> +};
> +
>  /* eMMC */
>  &usdhc1 {
>  	pinctrl-names = "default";
> @@ -108,6 +192,19 @@ MX93_PAD_I2C1_SDA__GPIO1_IO01		0x31e
>  		>;
>  	};
>
> +	pinctrl_lpi2c3: lpi2c3grp {
> +		fsl,pins = <
> +			MX93_PAD_GPIO_IO28__LPI2C3_SDA		0x40000b9e
> +			MX93_PAD_GPIO_IO29__LPI2C3_SCL		0x40000b9e
> +		>;
> +	};
> +
> +	pinctrl_pmic: pmicgrp {
> +		fsl,pins = <
> +			MX93_PAD_ENET2_RD3__GPIO4_IO27		0x31e
> +		>;
> +	};
> +
>  	pinctrl_usdhc1: usdhc1grp {
>  		fsl,pins = <
>  			MX93_PAD_SD1_CLK__USDHC1_CLK		0x179e
> --
> 2.34.1
>

[PATCH 02/13] arm64: dts: freescale: imx93-phycore-som: Add EEPROM support

[Primoz Fiser]

Add support for the EEPROM chip available on I2C3 bus (address 0x50),
used for the PHYTEC SOM detection.

Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
---
 arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
index 507a71f9294b..442ee067a047 100644
--- a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
@@ -154,6 +154,14 @@ ldo5: LDO5 {
 			};
 		};
 	};
+
+	/* EEPROM */
+	eeprom@50 {
+		compatible = "atmel,24c32";
+		pagesize = <32>;
+		reg = <0x50>;
+		vcc-supply = <&buck4>;
+	};
 };
 
 /* eMMC */
-- 
2.34.1

Re: [PATCH 02/13] arm64: dts: freescale: imx93-phycore-som: Add EEPROM support

[Frank Li]

On Thu, Apr 10, 2025 at 11:02:40AM +0200, Primoz Fiser wrote:
> Add support for the EEPROM chip available on I2C3 bus (address 0x50),
> used for the PHYTEC SOM detection.
>
> Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
> ---
>  arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi | 8 ++++++++
>  1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
> index 507a71f9294b..442ee067a047 100644
> --- a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
> @@ -154,6 +154,14 @@ ldo5: LDO5 {
>  			};
>  		};
>  	};
> +
> +	/* EEPROM */
> +	eeprom@50 {
> +		compatible = "atmel,24c32";
> +		pagesize = <32>;
> +		reg = <0x50>;

reg should be second property, move it ahead pagesize.

Frank
> +		vcc-supply = <&buck4>;
> +	};
>  };
>
>  /* eMMC */
> --
> 2.34.1
>

[PATCH 03/13] arm64: dts: freescale: imx93-phycore-som: Disable LED pull-up

[Primoz Fiser]

There is already an external pull-down resistor on the LED output line.
It makes no sense to have both pull-down and pull-up resistors enabled
at the same time. Thus disable the internal pull-down.

Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
---
 arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
index 442ee067a047..82f680d891c2 100644
--- a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
@@ -196,7 +196,7 @@ MX93_PAD_ENET2_TD2__ENET1_TX_CLK		0x4000050e
 
 	pinctrl_leds: ledsgrp {
 		fsl,pins = <
-			MX93_PAD_I2C1_SDA__GPIO1_IO01		0x31e
+			MX93_PAD_I2C1_SDA__GPIO1_IO01		0x11e
 		>;
 	};
 
-- 
2.34.1

Re: [PATCH 03/13] arm64: dts: freescale: imx93-phycore-som: Disable LED pull-up

[Frank Li]

On Thu, Apr 10, 2025 at 11:02:41AM +0200, Primoz Fiser wrote:
> There is already an external pull-down resistor on the LED output line.
> It makes no sense to have both pull-down and pull-up resistors enabled
> at the same time. Thus disable the internal pull-down.
>
> Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
> ---

Reviewed-by: Frank Li <Frank.Li@nxp.com>

>  arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
> index 442ee067a047..82f680d891c2 100644
> --- a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
> @@ -196,7 +196,7 @@ MX93_PAD_ENET2_TD2__ENET1_TX_CLK		0x4000050e
>
>  	pinctrl_leds: ledsgrp {
>  		fsl,pins = <
> -			MX93_PAD_I2C1_SDA__GPIO1_IO01		0x31e
> +			MX93_PAD_I2C1_SDA__GPIO1_IO01		0x11e
>  		>;
>  	};
>
> --
> 2.34.1
>

[PATCH 04/13] arm64: dts: freescale: imx93-phycore-som: Enhance eMMC pinctrl

[Primoz Fiser]

Improve eMMC on phyCORE-i.MX93 SOM by adding 100MHz and 200MHz pinctrl
modes. This enables to use eMMC at enhanced data rates (e.g. HS400).

While at it, apply a workaround for the i.MX93 chip errata ERR052021.

Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
---
 .../boot/dts/freescale/imx93-phycore-som.dtsi | 57 +++++++++++++++----
 1 file changed, 47 insertions(+), 10 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
index 82f680d891c2..3d84eed33074 100644
--- a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
@@ -166,8 +166,10 @@ eeprom@50 {
 
 /* eMMC */
 &usdhc1 {
-	pinctrl-names = "default";
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
 	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 	bus-width = <8>;
 	non-removable;
 	status = "okay";
@@ -213,18 +215,53 @@ MX93_PAD_ENET2_RD3__GPIO4_IO27		0x31e
 		>;
 	};
 
+	/* need to config the SION for data and cmd pad, refer to ERR052021 */
 	pinctrl_usdhc1: usdhc1grp {
 		fsl,pins = <
 			MX93_PAD_SD1_CLK__USDHC1_CLK		0x179e
-			MX93_PAD_SD1_CMD__USDHC1_CMD		0x1386
-			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x138e
-			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x1386
-			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x138e
-			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x1386
-			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x1386
-			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x1386
-			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x1386
-			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x1386
+			MX93_PAD_SD1_CMD__USDHC1_CMD		0x40001386
+			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x4000138e
+			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x40001386
+			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x4000138e
+			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x40001386
+			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x40001386
+			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x40001386
+			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x40001386
+			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x40001386
+			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x179e
+		>;
+	};
+
+	/* need to config the SION for data and cmd pad, refer to ERR052021 */
+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+		fsl,pins = <
+			MX93_PAD_SD1_CLK__USDHC1_CLK		0x17be
+			MX93_PAD_SD1_CMD__USDHC1_CMD		0x4000139e
+			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x4000138e
+			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x4000139e
+			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x400013be
+			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x4000139e
+			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x4000139e
+			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x4000139e
+			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x4000139e
+			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x4000139e
+			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x179e
+		>;
+	};
+
+	/* need to config the SION for data and cmd pad, refer to ERR052021 */
+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+		fsl,pins = <
+			MX93_PAD_SD1_CLK__USDHC1_CLK		0x17be
+			MX93_PAD_SD1_CMD__USDHC1_CMD		0x4000139e
+			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x4000139e
+			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x400013be
+			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x400013be
+			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x400013be
+			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x400013be
+			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x400013be
+			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x400013be
+			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x400013be
 			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x179e
 		>;
 	};
-- 
2.34.1

Re: [PATCH 04/13] arm64: dts: freescale: imx93-phycore-som: Enhance eMMC pinctrl

[Frank Li]

On Thu, Apr 10, 2025 at 11:02:42AM +0200, Primoz Fiser wrote:
> Improve eMMC on phyCORE-i.MX93 SOM by adding 100MHz and 200MHz pinctrl
> modes. This enables to use eMMC at enhanced data rates (e.g. HS400).
>
> While at it, apply a workaround for the i.MX93 chip errata ERR052021.
>
> Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
> ---
>  .../boot/dts/freescale/imx93-phycore-som.dtsi | 57 +++++++++++++++----
>  1 file changed, 47 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
> index 82f680d891c2..3d84eed33074 100644
> --- a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
> @@ -166,8 +166,10 @@ eeprom@50 {
>
>  /* eMMC */
>  &usdhc1 {
> -	pinctrl-names = "default";
> +	pinctrl-names = "default", "state_100mhz", "state_200mhz";
>  	pinctrl-0 = <&pinctrl_usdhc1>;
> +	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
> +	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
>  	bus-width = <8>;
>  	non-removable;
>  	status = "okay";
> @@ -213,18 +215,53 @@ MX93_PAD_ENET2_RD3__GPIO4_IO27		0x31e
>  		>;
>  	};
>
> +	/* need to config the SION for data and cmd pad, refer to ERR052021 */
>  	pinctrl_usdhc1: usdhc1grp {
>  		fsl,pins = <
>  			MX93_PAD_SD1_CLK__USDHC1_CLK		0x179e
> -			MX93_PAD_SD1_CMD__USDHC1_CMD		0x1386
> -			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x138e
> -			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x1386
> -			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x138e
> -			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x1386
> -			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x1386
> -			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x1386
> -			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x1386
> -			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x1386
> +			MX93_PAD_SD1_CMD__USDHC1_CMD		0x40001386
> +			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x4000138e
> +			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x40001386
> +			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x4000138e
> +			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x40001386
> +			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x40001386
> +			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x40001386
> +			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x40001386
> +			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x40001386
> +			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x179e
> +		>;
> +	};
> +
> +	/* need to config the SION for data and cmd pad, refer to ERR052021 */
> +	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
> +		fsl,pins = <
> +			MX93_PAD_SD1_CLK__USDHC1_CLK		0x17be
> +			MX93_PAD_SD1_CMD__USDHC1_CMD		0x4000139e
> +			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x4000138e

any reason why DATA0 is difference with other one?

> +			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x4000139e
> +			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x400013be
> +			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x4000139e
> +			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x4000139e
> +			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x4000139e
> +			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x4000139e
> +			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x4000139e
> +			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x179e
> +		>;
> +	};
> +
> +	/* need to config the SION for data and cmd pad, refer to ERR052021 */
> +	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
> +		fsl,pins = <
> +			MX93_PAD_SD1_CLK__USDHC1_CLK		0x17be
> +			MX93_PAD_SD1_CMD__USDHC1_CMD		0x4000139e
> +			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x4000139e

any reason why DATA0/DATA1 is difference with other one

Frank
> +			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x400013be
> +			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x400013be
> +			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x400013be
> +			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x400013be
> +			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x400013be
> +			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x400013be
> +			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x400013be
>  			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x179e
>  		>;
>  	};
> --
> 2.34.1
>

Re: [PATCH 04/13] arm64: dts: freescale: imx93-phycore-som: Enhance eMMC pinctrl

[Primoz Fiser]

Hi Frank,

On 10. 04. 25 16:56, Frank Li wrote:
> On Thu, Apr 10, 2025 at 11:02:42AM +0200, Primoz Fiser wrote:
>> Improve eMMC on phyCORE-i.MX93 SOM by adding 100MHz and 200MHz pinctrl
>> modes. This enables to use eMMC at enhanced data rates (e.g. HS400).
>>
>> While at it, apply a workaround for the i.MX93 chip errata ERR052021.
>>
>> Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
>> ---
>>  .../boot/dts/freescale/imx93-phycore-som.dtsi | 57 +++++++++++++++----
>>  1 file changed, 47 insertions(+), 10 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
>> index 82f680d891c2..3d84eed33074 100644
>> --- a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
>> +++ b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
>> @@ -166,8 +166,10 @@ eeprom@50 {
>>
>>  /* eMMC */
>>  &usdhc1 {
>> -	pinctrl-names = "default";
>> +	pinctrl-names = "default", "state_100mhz", "state_200mhz";
>>  	pinctrl-0 = <&pinctrl_usdhc1>;
>> +	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
>> +	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
>>  	bus-width = <8>;
>>  	non-removable;
>>  	status = "okay";
>> @@ -213,18 +215,53 @@ MX93_PAD_ENET2_RD3__GPIO4_IO27		0x31e
>>  		>;
>>  	};
>>
>> +	/* need to config the SION for data and cmd pad, refer to ERR052021 */
>>  	pinctrl_usdhc1: usdhc1grp {
>>  		fsl,pins = <
>>  			MX93_PAD_SD1_CLK__USDHC1_CLK		0x179e
>> -			MX93_PAD_SD1_CMD__USDHC1_CMD		0x1386
>> -			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x138e
>> -			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x1386
>> -			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x138e
>> -			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x1386
>> -			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x1386
>> -			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x1386
>> -			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x1386
>> -			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x1386
>> +			MX93_PAD_SD1_CMD__USDHC1_CMD		0x40001386
>> +			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x4000138e
>> +			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x40001386
>> +			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x4000138e
>> +			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x40001386
>> +			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x40001386
>> +			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x40001386
>> +			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x40001386
>> +			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x40001386
>> +			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x179e
>> +		>;
>> +	};
>> +
>> +	/* need to config the SION for data and cmd pad, refer to ERR052021 */
>> +	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
>> +		fsl,pins = <
>> +			MX93_PAD_SD1_CLK__USDHC1_CLK		0x17be
>> +			MX93_PAD_SD1_CMD__USDHC1_CMD		0x4000139e
>> +			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x4000138e
> 
> any reason why DATA0 is difference with other one?
> 
>> +			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x4000139e
>> +			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x400013be
>> +			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x4000139e
>> +			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x4000139e
>> +			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x4000139e
>> +			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x4000139e
>> +			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x4000139e
>> +			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x179e
>> +		>;
>> +	};
>> +
>> +	/* need to config the SION for data and cmd pad, refer to ERR052021 */
>> +	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
>> +		fsl,pins = <
>> +			MX93_PAD_SD1_CLK__USDHC1_CLK		0x17be
>> +			MX93_PAD_SD1_CMD__USDHC1_CMD		0x4000139e
>> +			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x4000139e
> 
> any reason why DATA0/DATA1 is difference with other one

Bus signal integrity envelope was measured and drive-strengths adjusted
accordingly by the PHYTEC hardware department to conform to the specs.

Values were thus determined empirically to adjust for differences in
signal impedance due to PCB layout.

BR,
Primoz

> 
> Frank
>> +			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x400013be
>> +			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x400013be
>> +			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x400013be
>> +			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x400013be
>> +			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x400013be
>> +			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x400013be
>> +			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x400013be
>>  			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x179e
>>  		>;
>>  	};
>> --
>> 2.34.1
>>

-- 
Primoz Fiser
phone: +386-41-390-545
email: primoz.fiser@norik.com
--
Norik systems d.o.o.
Your embedded software partner
Slovenia, EU
phone: +386-41-540-545
email: info@norik.com

Re: [PATCH 04/13] arm64: dts: freescale: imx93-phycore-som: Enhance eMMC pinctrl

[Frank Li]

On Fri, Apr 11, 2025 at 08:29:05AM +0200, Primoz Fiser wrote:
> Hi Frank,
>
> On 10. 04. 25 16:56, Frank Li wrote:
> > On Thu, Apr 10, 2025 at 11:02:42AM +0200, Primoz Fiser wrote:
> >> Improve eMMC on phyCORE-i.MX93 SOM by adding 100MHz and 200MHz pinctrl
> >> modes. This enables to use eMMC at enhanced data rates (e.g. HS400).
> >>
> >> While at it, apply a workaround for the i.MX93 chip errata ERR052021.
> >>
> >> Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
> >> ---
> >>  .../boot/dts/freescale/imx93-phycore-som.dtsi | 57 +++++++++++++++----
> >>  1 file changed, 47 insertions(+), 10 deletions(-)
> >>
> >> diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
> >> index 82f680d891c2..3d84eed33074 100644
> >> --- a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
> >> +++ b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
> >> @@ -166,8 +166,10 @@ eeprom@50 {
> >>
> >>  /* eMMC */
> >>  &usdhc1 {
> >> -	pinctrl-names = "default";
> >> +	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> >>  	pinctrl-0 = <&pinctrl_usdhc1>;
> >> +	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
> >> +	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
> >>  	bus-width = <8>;
> >>  	non-removable;
> >>  	status = "okay";
> >> @@ -213,18 +215,53 @@ MX93_PAD_ENET2_RD3__GPIO4_IO27		0x31e
> >>  		>;
> >>  	};
> >>
> >> +	/* need to config the SION for data and cmd pad, refer to ERR052021 */
> >>  	pinctrl_usdhc1: usdhc1grp {
> >>  		fsl,pins = <
> >>  			MX93_PAD_SD1_CLK__USDHC1_CLK		0x179e
> >> -			MX93_PAD_SD1_CMD__USDHC1_CMD		0x1386
> >> -			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x138e
> >> -			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x1386
> >> -			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x138e
> >> -			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x1386
> >> -			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x1386
> >> -			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x1386
> >> -			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x1386
> >> -			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x1386
> >> +			MX93_PAD_SD1_CMD__USDHC1_CMD		0x40001386
> >> +			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x4000138e
> >> +			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x40001386
> >> +			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x4000138e
> >> +			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x40001386
> >> +			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x40001386
> >> +			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x40001386
> >> +			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x40001386
> >> +			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x40001386
> >> +			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x179e
> >> +		>;
> >> +	};
> >> +
> >> +	/* need to config the SION for data and cmd pad, refer to ERR052021 */
> >> +	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
> >> +		fsl,pins = <
> >> +			MX93_PAD_SD1_CLK__USDHC1_CLK		0x17be
> >> +			MX93_PAD_SD1_CMD__USDHC1_CMD		0x4000139e
> >> +			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x4000138e
> >
> > any reason why DATA0 is difference with other one?
> >
> >> +			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x4000139e
> >> +			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x400013be
> >> +			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x4000139e
> >> +			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x4000139e
> >> +			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x4000139e
> >> +			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x4000139e
> >> +			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x4000139e
> >> +			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x179e
> >> +		>;
> >> +	};
> >> +
> >> +	/* need to config the SION for data and cmd pad, refer to ERR052021 */
> >> +	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
> >> +		fsl,pins = <
> >> +			MX93_PAD_SD1_CLK__USDHC1_CLK		0x17be
> >> +			MX93_PAD_SD1_CMD__USDHC1_CMD		0x4000139e
> >> +			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x4000139e
> >
> > any reason why DATA0/DATA1 is difference with other one
>
> Bus signal integrity envelope was measured and drive-strengths adjusted
> accordingly by the PHYTEC hardware department to conform to the specs.
>
> Values were thus determined empirically to adjust for differences in
> signal impedance due to PCB layout.

Okay thanks, I just to make sure it is not typo.

Frank
>
> BR,
> Primoz
>
> >
> > Frank
> >> +			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x400013be
> >> +			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x400013be
> >> +			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x400013be
> >> +			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x400013be
> >> +			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x400013be
> >> +			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x400013be
> >> +			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x400013be
> >>  			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x179e
> >>  		>;
> >>  	};
> >> --
> >> 2.34.1
> >>
>
> --
> Primoz Fiser
> phone: +386-41-390-545
> email: primoz.fiser@norik.com
> --
> Norik systems d.o.o.
> Your embedded software partner
> Slovenia, EU
> phone: +386-41-540-545
> email: info@norik.com

[PATCH 05/13] arm64: dts: freescale: imx93-phycore-som: Add eMMC no-1-8-v by default

[Primoz Fiser]

Add property 'no-1-8-v' by default to usdhc1 (eMMC) node. Bootloader
will take care of deleting the property in case SOM supports HS400 mode
(1.8V IO voltage feature flag has to be set in the EEPROM).

Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
---
 arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
index 3d84eed33074..d6589d26c875 100644
--- a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
@@ -172,6 +172,7 @@ &usdhc1 {
 	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 	bus-width = <8>;
 	non-removable;
+	no-1-8-v;
 	status = "okay";
 };
 
-- 
2.34.1

Re: [PATCH 05/13] arm64: dts: freescale: imx93-phycore-som: Add eMMC no-1-8-v by default

[Frank Li]

On Thu, Apr 10, 2025 at 11:02:43AM +0200, Primoz Fiser wrote:
> Add property 'no-1-8-v' by default to usdhc1 (eMMC) node. Bootloader
> will take care of deleting the property in case SOM supports HS400 mode
> (1.8V IO voltage feature flag has to be set in the EEPROM).

what means of EEPROM here?

Generally eMMC worked fixed voltage, why need 'no-1-8-v' here, even no
HS400 support.

Frank
>
> Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
> ---
>  arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
> index 3d84eed33074..d6589d26c875 100644
> --- a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
> @@ -172,6 +172,7 @@ &usdhc1 {
>  	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
>  	bus-width = <8>;
>  	non-removable;
> +	no-1-8-v;
>  	status = "okay";
>  };
>
> --
> 2.34.1
>

Re: [PATCH 05/13] arm64: dts: freescale: imx93-phycore-som: Add eMMC no-1-8-v by default

[Primoz Fiser]

Hi Frank,

On 10. 04. 25 17:01, Frank Li wrote:
> On Thu, Apr 10, 2025 at 11:02:43AM +0200, Primoz Fiser wrote:
>> Add property 'no-1-8-v' by default to usdhc1 (eMMC) node. Bootloader
>> will take care of deleting the property in case SOM supports HS400 mode
>> (1.8V IO voltage feature flag has to be set in the EEPROM).
> 
> what means of EEPROM here?
> 
> Generally eMMC worked fixed voltage, why need 'no-1-8-v' here, even no
> HS400 support.

The phyCORE-i.MX93 SoM comes in two variants, one with 3.3V VDD_IO and
the other one with 1.8V VDD_IO voltage set.

The 3.3V variant can only support DDR52 mode, while 1.8V variant will
support HS400ES eMMC mode.

The information about VDD_IO option is encoded in the SoM's EEPROM. We
read EEPROM in the bootloader and clear "no-1-8-v" flag in case of 1.8V
SOM variant is detected.

In case of EEPROM error (erased or read error) the fall-back option has
to support both SoM variants, hence the "no-1-8-v" flag has to be set by
default.

BR,
Primoz



> 
> Frank
>>
>> Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
>> ---
>>  arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
>> index 3d84eed33074..d6589d26c875 100644
>> --- a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
>> +++ b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
>> @@ -172,6 +172,7 @@ &usdhc1 {
>>  	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
>>  	bus-width = <8>;
>>  	non-removable;
>> +	no-1-8-v;
>>  	status = "okay";
>>  };
>>
>> --
>> 2.34.1
>>

-- 
Primoz Fiser
phone: +386-41-390-545
email: primoz.fiser@norik.com
--
Norik systems d.o.o.
Your embedded software partner
Slovenia, EU
phone: +386-41-540-545
email: info@norik.com

Re: [PATCH 05/13] arm64: dts: freescale: imx93-phycore-som: Add eMMC no-1-8-v by default

[Frank Li]

On Fri, Apr 11, 2025 at 08:51:18AM +0200, Primoz Fiser wrote:
> Hi Frank,
>
> On 10. 04. 25 17:01, Frank Li wrote:
> > On Thu, Apr 10, 2025 at 11:02:43AM +0200, Primoz Fiser wrote:
> >> Add property 'no-1-8-v' by default to usdhc1 (eMMC) node. Bootloader
> >> will take care of deleting the property in case SOM supports HS400 mode
> >> (1.8V IO voltage feature flag has to be set in the EEPROM).
> >
> > what means of EEPROM here?
> >
> > Generally eMMC worked fixed voltage, why need 'no-1-8-v' here, even no
> > HS400 support.
>
> The phyCORE-i.MX93 SoM comes in two variants, one with 3.3V VDD_IO and
> the other one with 1.8V VDD_IO voltage set.
>
> The 3.3V variant can only support DDR52 mode, while 1.8V variant will
> support HS400ES eMMC mode.
>
> The information about VDD_IO option is encoded in the SoM's EEPROM. We
> read EEPROM in the bootloader and clear "no-1-8-v" flag in case of 1.8V
> SOM variant is detected.
>
> In case of EEPROM error (erased or read error) the fall-back option has
> to support both SoM variants, hence the "no-1-8-v" flag has to be set by
> default.

Thanks, can add such detail information at commit message.

Frank

>
> BR,
> Primoz
>
>
>
> >
> > Frank
> >>
> >> Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
> >> ---
> >>  arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi | 1 +
> >>  1 file changed, 1 insertion(+)
> >>
> >> diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
> >> index 3d84eed33074..d6589d26c875 100644
> >> --- a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
> >> +++ b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
> >> @@ -172,6 +172,7 @@ &usdhc1 {
> >>  	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
> >>  	bus-width = <8>;
> >>  	non-removable;
> >> +	no-1-8-v;
> >>  	status = "okay";
> >>  };
> >>
> >> --
> >> 2.34.1
> >>
>
> --
> Primoz Fiser
> phone: +386-41-390-545
> email: primoz.fiser@norik.com
> --
> Norik systems d.o.o.
> Your embedded software partner
> Slovenia, EU
> phone: +386-41-540-545
> email: info@norik.com

[PATCH 06/13] arm64: dts: freescale: imx93-phyboard-segin: Drop eMMC no-1-8-v flag

[Primoz Fiser]

Drop redundant 'no-1-8-v' flag from usdhc1 (eMMC) node. Flag is now set
by default in the SOM include file (imx93-phycore-som.dtsi).

Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
---
 arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
index 85fb188b057f..902b523fc92c 100644
--- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
+++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
@@ -40,11 +40,6 @@ &lpuart1 {
 	status = "okay";
 };
 
-/* eMMC */
-&usdhc1 {
-	no-1-8-v;
-};
-
 /* SD-Card */
 &usdhc2 {
 	pinctrl-names = "default", "state_100mhz", "state_200mhz";
-- 
2.34.1

Re: [PATCH 06/13] arm64: dts: freescale: imx93-phyboard-segin: Drop eMMC no-1-8-v flag

[Frank Li]

On Thu, Apr 10, 2025 at 11:02:44AM +0200, Primoz Fiser wrote:
> Drop redundant 'no-1-8-v' flag from usdhc1 (eMMC) node. Flag is now set
> by default in the SOM include file (imx93-phycore-som.dtsi).
>
> Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
> ---

Reviewed-by: Frank Li <Frank.Li@nxp.com>

>  arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts | 5 -----
>  1 file changed, 5 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
> index 85fb188b057f..902b523fc92c 100644
> --- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
> +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
> @@ -40,11 +40,6 @@ &lpuart1 {
>  	status = "okay";
>  };
>
> -/* eMMC */
> -&usdhc1 {
> -	no-1-8-v;
> -};
> -
>  /* SD-Card */
>  &usdhc2 {
>  	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> --
> 2.34.1
>

Re: [PATCH 06/13] arm64: dts: freescale: imx93-phyboard-segin: Drop eMMC no-1-8-v flag

[Stefan Wahren]

Hi Primoz,

Am 10.04.25 um 11:02 schrieb Primoz Fiser:
> Drop redundant 'no-1-8-v' flag from usdhc1 (eMMC) node. Flag is now set
> by default in the SOM include file (imx93-phycore-som.dtsi).
>
> Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
i think, Patch 5 and this one should be squashed together.

Regards
> ---
>   arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts | 5 -----
>   1 file changed, 5 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
> index 85fb188b057f..902b523fc92c 100644
> --- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
> +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
> @@ -40,11 +40,6 @@ &lpuart1 {
>   	status = "okay";
>   };
>
> -/* eMMC */
> -&usdhc1 {
> -	no-1-8-v;
> -};
> -
>   /* SD-Card */
>   &usdhc2 {
>   	pinctrl-names = "default", "state_100mhz", "state_200mhz";

Re: [PATCH 06/13] arm64: dts: freescale: imx93-phyboard-segin: Drop eMMC no-1-8-v flag

[Primoz Fiser]

Hi Stefan,

On 12. 04. 25 18:23, Stefan Wahren wrote:
> Hi Primoz,
> 
> Am 10.04.25 um 11:02 schrieb Primoz Fiser:
>> Drop redundant 'no-1-8-v' flag from usdhc1 (eMMC) node. Flag is now set
>> by default in the SOM include file (imx93-phycore-som.dtsi).
>>
>> Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
> i think, Patch 5 and this one should be squashed together.

I intentionally split these series into SoM and board related patches.

I see no benefit in squashing #5 and #6.

Also, I already got Frank's Reviewed-by tag on this patch.

Thus I would like to keep them separate as is.

Thanks,
BR,
Primoz

> 
> Regards
>> ---
>>   arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts | 5 -----
>>   1 file changed, 5 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
>> b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
>> index 85fb188b057f..902b523fc92c 100644
>> --- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
>> +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
>> @@ -40,11 +40,6 @@ &lpuart1 {
>>       status = "okay";
>>   };
>>
>> -/* eMMC */
>> -&usdhc1 {
>> -    no-1-8-v;
>> -};
>> -
>>   /* SD-Card */
>>   &usdhc2 {
>>       pinctrl-names = "default", "state_100mhz", "state_200mhz";
> 

-- 
Primoz Fiser
phone: +386-41-390-545
email: primoz.fiser@norik.com
--
Norik systems d.o.o.
Your embedded software partner
Slovenia, EU
phone: +386-41-540-545
email: info@norik.com

Re: [PATCH 06/13] arm64: dts: freescale: imx93-phyboard-segin: Drop eMMC no-1-8-v flag

[Stefan Wahren]

Hi Primoz,

Am 14.04.25 um 12:39 schrieb Primoz Fiser:
> Hi Stefan,
>
> On 12. 04. 25 18:23, Stefan Wahren wrote:
>> Hi Primoz,
>>
>> Am 10.04.25 um 11:02 schrieb Primoz Fiser:
>>> Drop redundant 'no-1-8-v' flag from usdhc1 (eMMC) node. Flag is now set
>>> by default in the SOM include file (imx93-phycore-som.dtsi).
>>>
>>> Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
>> i think, Patch 5 and this one should be squashed together.
> I intentionally split these series into SoM and board related patches.
>
> I see no benefit in squashing #5 and #6.
 From my understanding both changes belong together, because you 
actually moved the property from board to SoM level. Otherwise in case 
there is something wrong later, both patches need to be reverted.
> Also, I already got Frank's Reviewed-by tag on this patch.
This wouldn't invalidate Frank's review.

Just my two cents

[PATCH 07/13] arm64: dts: freescale: imx93-phyboard-segin: Disable SD-card write-protect

[Primoz Fiser]

Add disable-wp flag (write-protect) to usdhc2 node (SD-card) to get rid
of the following kernel boot warning:

  host does not support reading read-only switch, assuming write-enable

Micro SD cards can't be physically write-protected like full-sized
cards. Thus disable this feature.

Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
---
 arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
index 902b523fc92c..3d5cd0561362 100644
--- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
+++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
@@ -48,6 +48,7 @@ &usdhc2 {
 	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
 	bus-width = <4>;
 	cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
+	disable-wp;
 	no-mmc;
 	no-sdio;
 	vmmc-supply = <&reg_usdhc2_vmmc>;
-- 
2.34.1

Re: [PATCH 07/13] arm64: dts: freescale: imx93-phyboard-segin: Disable SD-card write-protect

[Frank Li]

On Thu, Apr 10, 2025 at 11:02:45AM +0200, Primoz Fiser wrote:
> Add disable-wp flag (write-protect) to usdhc2 node (SD-card) to get rid
> of the following kernel boot warning:
>
>   host does not support reading read-only switch, assuming write-enable
>
> Micro SD cards can't be physically write-protected like full-sized
> cards. Thus disable this feature.

"Thus add disable-wp property".

Frank
>
> Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
> ---
>  arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
> index 902b523fc92c..3d5cd0561362 100644
> --- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
> +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
> @@ -48,6 +48,7 @@ &usdhc2 {
>  	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
>  	bus-width = <4>;
>  	cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
> +	disable-wp;
>  	no-mmc;
>  	no-sdio;
>  	vmmc-supply = <&reg_usdhc2_vmmc>;
> --
> 2.34.1
>

[PATCH 08/13] arm64: dts: freescale: imx93-phyboard-segin: Fix SD-card pinctrl

[Primoz Fiser]

Until now, all usdhc2 (SD-card) pinctrl labels pointed to one pinctrl
group "usdhc2grp" which was overwritten twice by the 100 and 200 MHz
modes. Fix this by using unique pinctrl names.

While at it, apply i.MX93 chip errata ERR052021 workaround and adjust
pinctrl drive-strengths to improve signal integrity. Drive-strength
values come from the downstream PHYTEC kernel and were devised and
verified by the hardware department measurements.

Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
---
 .../dts/freescale/imx93-phyboard-segin.dts    | 47 ++++++++++---------
 1 file changed, 25 insertions(+), 22 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
index 3d5cd0561362..525f52789f8b 100644
--- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
+++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
@@ -75,39 +75,42 @@ MX93_PAD_SD2_CD_B__GPIO3_IO00		0x31e
 		>;
 	};
 
+	/* need to config the SION for data and cmd pad, refer to ERR052021 */
 	pinctrl_usdhc2_default: usdhc2grp {
 		fsl,pins = <
-			MX93_PAD_SD2_CLK__USDHC2_CLK		0x179e
-			MX93_PAD_SD2_CMD__USDHC2_CMD		0x139e
-			MX93_PAD_SD2_DATA0__USDHC2_DATA0	0x138e
-			MX93_PAD_SD2_DATA1__USDHC2_DATA1	0x138e
-			MX93_PAD_SD2_DATA2__USDHC2_DATA2	0x138e
-			MX93_PAD_SD2_DATA3__USDHC2_DATA3	0x139e
+			MX93_PAD_SD2_CLK__USDHC2_CLK		0x159e
+			MX93_PAD_SD2_CMD__USDHC2_CMD		0x4000139e
+			MX93_PAD_SD2_DATA0__USDHC2_DATA0	0x4000138e
+			MX93_PAD_SD2_DATA1__USDHC2_DATA1	0x4000138e
+			MX93_PAD_SD2_DATA2__USDHC2_DATA2	0x4000138e
+			MX93_PAD_SD2_DATA3__USDHC2_DATA3	0x4000139e
 			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e
 		>;
 	};
 
-	pinctrl_usdhc2_100mhz: usdhc2grp {
+	/* need to config the SION for data and cmd pad, refer to ERR052021 */
+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
 		fsl,pins = <
-			MX93_PAD_SD2_CLK__USDHC2_CLK            0x179e
-			MX93_PAD_SD2_CMD__USDHC2_CMD            0x139e
-			MX93_PAD_SD2_DATA0__USDHC2_DATA0        0x138e
-			MX93_PAD_SD2_DATA1__USDHC2_DATA1        0x138e
-			MX93_PAD_SD2_DATA2__USDHC2_DATA2        0x139e
-			MX93_PAD_SD2_DATA3__USDHC2_DATA3        0x139e
-			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT    0x51e
+			MX93_PAD_SD2_CLK__USDHC2_CLK		0x159e
+			MX93_PAD_SD2_CMD__USDHC2_CMD		0x4000139e
+			MX93_PAD_SD2_DATA0__USDHC2_DATA0	0x4000138e
+			MX93_PAD_SD2_DATA1__USDHC2_DATA1	0x4000138e
+			MX93_PAD_SD2_DATA2__USDHC2_DATA2	0x4000139e
+			MX93_PAD_SD2_DATA3__USDHC2_DATA3	0x4000139e
+			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e
 		>;
 	};
 
-	pinctrl_usdhc2_200mhz: usdhc2grp {
+	/* need to config the SION for data and cmd pad, refer to ERR052021 */
+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
 		fsl,pins = <
-			MX93_PAD_SD2_CLK__USDHC2_CLK            0x178e
-			MX93_PAD_SD2_CMD__USDHC2_CMD            0x139e
-			MX93_PAD_SD2_DATA0__USDHC2_DATA0        0x139e
-			MX93_PAD_SD2_DATA1__USDHC2_DATA1        0x139e
-			MX93_PAD_SD2_DATA2__USDHC2_DATA2        0x139e
-			MX93_PAD_SD2_DATA3__USDHC2_DATA3        0x139e
-			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT    0x51e
+			MX93_PAD_SD2_CLK__USDHC2_CLK		0x158e
+			MX93_PAD_SD2_CMD__USDHC2_CMD		0x4000139e
+			MX93_PAD_SD2_DATA0__USDHC2_DATA0	0x4000139e
+			MX93_PAD_SD2_DATA1__USDHC2_DATA1	0x4000139e
+			MX93_PAD_SD2_DATA2__USDHC2_DATA2	0x4000139e
+			MX93_PAD_SD2_DATA3__USDHC2_DATA3	0x4000139e
+			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e
 		>;
 	};
 };
-- 
2.34.1

Re: [PATCH 08/13] arm64: dts: freescale: imx93-phyboard-segin: Fix SD-card pinctrl

[Frank Li]

On Thu, Apr 10, 2025 at 11:02:46AM +0200, Primoz Fiser wrote:
> Until now, all usdhc2 (SD-card) pinctrl labels pointed to one pinctrl
> group "usdhc2grp" which was overwritten twice by the 100 and 200 MHz
> modes. Fix this by using unique pinctrl names.
>
> While at it, apply i.MX93 chip errata ERR052021 workaround and adjust

Errata link here!

> pinctrl drive-strengths to improve signal integrity. Drive-strength
> values come from the downstream PHYTEC kernel and were devised and
> verified by the hardware department measurements.
>
> Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
> ---
>  .../dts/freescale/imx93-phyboard-segin.dts    | 47 ++++++++++---------
>  1 file changed, 25 insertions(+), 22 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
> index 3d5cd0561362..525f52789f8b 100644
> --- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
> +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
> @@ -75,39 +75,42 @@ MX93_PAD_SD2_CD_B__GPIO3_IO00		0x31e
>  		>;
>  	};
>
> +	/* need to config the SION for data and cmd pad, refer to ERR052021 */

errata's implement need seperate patch

Frank
>  	pinctrl_usdhc2_default: usdhc2grp {
>  		fsl,pins = <
> -			MX93_PAD_SD2_CLK__USDHC2_CLK		0x179e
> -			MX93_PAD_SD2_CMD__USDHC2_CMD		0x139e
> -			MX93_PAD_SD2_DATA0__USDHC2_DATA0	0x138e
> -			MX93_PAD_SD2_DATA1__USDHC2_DATA1	0x138e
> -			MX93_PAD_SD2_DATA2__USDHC2_DATA2	0x138e
> -			MX93_PAD_SD2_DATA3__USDHC2_DATA3	0x139e
> +			MX93_PAD_SD2_CLK__USDHC2_CLK		0x159e
> +			MX93_PAD_SD2_CMD__USDHC2_CMD		0x4000139e
> +			MX93_PAD_SD2_DATA0__USDHC2_DATA0	0x4000138e
> +			MX93_PAD_SD2_DATA1__USDHC2_DATA1	0x4000138e
> +			MX93_PAD_SD2_DATA2__USDHC2_DATA2	0x4000138e
> +			MX93_PAD_SD2_DATA3__USDHC2_DATA3	0x4000139e
>  			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e
>  		>;
>  	};
>
> -	pinctrl_usdhc2_100mhz: usdhc2grp {
> +	/* need to config the SION for data and cmd pad, refer to ERR052021 */
> +	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
>  		fsl,pins = <
> -			MX93_PAD_SD2_CLK__USDHC2_CLK            0x179e
> -			MX93_PAD_SD2_CMD__USDHC2_CMD            0x139e
> -			MX93_PAD_SD2_DATA0__USDHC2_DATA0        0x138e
> -			MX93_PAD_SD2_DATA1__USDHC2_DATA1        0x138e
> -			MX93_PAD_SD2_DATA2__USDHC2_DATA2        0x139e
> -			MX93_PAD_SD2_DATA3__USDHC2_DATA3        0x139e
> -			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT    0x51e
> +			MX93_PAD_SD2_CLK__USDHC2_CLK		0x159e
> +			MX93_PAD_SD2_CMD__USDHC2_CMD		0x4000139e
> +			MX93_PAD_SD2_DATA0__USDHC2_DATA0	0x4000138e
> +			MX93_PAD_SD2_DATA1__USDHC2_DATA1	0x4000138e
> +			MX93_PAD_SD2_DATA2__USDHC2_DATA2	0x4000139e
> +			MX93_PAD_SD2_DATA3__USDHC2_DATA3	0x4000139e
> +			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e
>  		>;
>  	};
>
> -	pinctrl_usdhc2_200mhz: usdhc2grp {
> +	/* need to config the SION for data and cmd pad, refer to ERR052021 */
> +	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
>  		fsl,pins = <
> -			MX93_PAD_SD2_CLK__USDHC2_CLK            0x178e
> -			MX93_PAD_SD2_CMD__USDHC2_CMD            0x139e
> -			MX93_PAD_SD2_DATA0__USDHC2_DATA0        0x139e
> -			MX93_PAD_SD2_DATA1__USDHC2_DATA1        0x139e
> -			MX93_PAD_SD2_DATA2__USDHC2_DATA2        0x139e
> -			MX93_PAD_SD2_DATA3__USDHC2_DATA3        0x139e
> -			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT    0x51e
> +			MX93_PAD_SD2_CLK__USDHC2_CLK		0x158e
> +			MX93_PAD_SD2_CMD__USDHC2_CMD		0x4000139e
> +			MX93_PAD_SD2_DATA0__USDHC2_DATA0	0x4000139e
> +			MX93_PAD_SD2_DATA1__USDHC2_DATA1	0x4000139e
> +			MX93_PAD_SD2_DATA2__USDHC2_DATA2	0x4000139e
> +			MX93_PAD_SD2_DATA3__USDHC2_DATA3	0x4000139e
> +			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e
>  		>;
>  	};
>  };
> --
> 2.34.1
>

[PATCH 09/13] arm64: dts: freescale: imx93-phyboard-segin: Add RTC support

[Primoz Fiser]

Add support for RTC clock connected via I2C on phyBOARD-Segin-i.MX93.
Make I2C RTC the default clock by configuring the aliases.

Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
---
 .../dts/freescale/imx93-phyboard-segin.dts    | 36 +++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
index 525f52789f8b..38b89398e646 100644
--- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
+++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
@@ -17,6 +17,11 @@ /{
 	compatible = "phytec,imx93-phyboard-segin", "phytec,imx93-phycore-som",
 		     "fsl,imx93";
 
+	aliases {
+		rtc0 = &i2c_rtc;
+		rtc1 = &bbnsm_rtc;
+	};
+
 	chosen {
 		stdout-path = &lpuart1;
 	};
@@ -33,6 +38,24 @@ reg_usdhc2_vmmc: regulator-usdhc2 {
 	};
 };
 
+/* I2C2 */
+&lpi2c2 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpi2c2>;
+	status = "okay";
+
+	/* RTC */
+	i2c_rtc: rtc@68 {
+		compatible = "microcrystal,rv4162";
+		reg = <0x68>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_rtc>;
+		interrupt-parent = <&gpio4>;
+		interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
+	};
+};
+
 /* Console */
 &lpuart1 {
 	pinctrl-names = "default";
@@ -56,6 +79,13 @@ &usdhc2 {
 };
 
 &iomuxc {
+	pinctrl_lpi2c2: lpi2c2grp {
+		fsl,pins = <
+			MX93_PAD_I2C2_SCL__LPI2C2_SCL		0x40000b9e
+			MX93_PAD_I2C2_SDA__LPI2C2_SDA		0x40000b9e
+		>;
+	};
+
 	pinctrl_uart1: uart1grp {
 		fsl,pins = <
 			MX93_PAD_UART1_RXD__LPUART1_RX		0x31e
@@ -69,6 +99,12 @@ MX93_PAD_SD2_RESET_B__GPIO3_IO07	0x31e
 		>;
 	};
 
+	pinctrl_rtc: rtcgrp {
+		fsl,pins = <
+			MX93_PAD_ENET2_RD2__GPIO4_IO26		0x31e
+		>;
+	};
+
 	pinctrl_usdhc2_cd: usdhc2cdgrp {
 		fsl,pins = <
 			MX93_PAD_SD2_CD_B__GPIO3_IO00		0x31e
-- 
2.34.1

Re: [PATCH 09/13] arm64: dts: freescale: imx93-phyboard-segin: Add RTC support

[Frank Li]

On Thu, Apr 10, 2025 at 11:02:47AM +0200, Primoz Fiser wrote:
> Add support for RTC clock connected via I2C on phyBOARD-Segin-i.MX93.
> Make I2C RTC the default clock by configuring the aliases.

"Add support for RTC connected via I2C on phyBOARD-Segin-i.MX93. Set
default RTC by configuring the aliases."

Frank
>
> Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
> ---
>  .../dts/freescale/imx93-phyboard-segin.dts    | 36 +++++++++++++++++++
>  1 file changed, 36 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
> index 525f52789f8b..38b89398e646 100644
> --- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
> +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
> @@ -17,6 +17,11 @@ /{
>  	compatible = "phytec,imx93-phyboard-segin", "phytec,imx93-phycore-som",
>  		     "fsl,imx93";
>
> +	aliases {
> +		rtc0 = &i2c_rtc;
> +		rtc1 = &bbnsm_rtc;
> +	};
> +
>  	chosen {
>  		stdout-path = &lpuart1;
>  	};
> @@ -33,6 +38,24 @@ reg_usdhc2_vmmc: regulator-usdhc2 {
>  	};
>  };
>
> +/* I2C2 */
> +&lpi2c2 {
> +	clock-frequency = <400000>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_lpi2c2>;
> +	status = "okay";
> +
> +	/* RTC */
> +	i2c_rtc: rtc@68 {
> +		compatible = "microcrystal,rv4162";
> +		reg = <0x68>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_rtc>;
> +		interrupt-parent = <&gpio4>;
> +		interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
> +	};
> +};
> +
>  /* Console */
>  &lpuart1 {
>  	pinctrl-names = "default";
> @@ -56,6 +79,13 @@ &usdhc2 {
>  };
>
>  &iomuxc {
> +	pinctrl_lpi2c2: lpi2c2grp {
> +		fsl,pins = <
> +			MX93_PAD_I2C2_SCL__LPI2C2_SCL		0x40000b9e
> +			MX93_PAD_I2C2_SDA__LPI2C2_SDA		0x40000b9e
> +		>;
> +	};
> +
>  	pinctrl_uart1: uart1grp {
>  		fsl,pins = <
>  			MX93_PAD_UART1_RXD__LPUART1_RX		0x31e
> @@ -69,6 +99,12 @@ MX93_PAD_SD2_RESET_B__GPIO3_IO07	0x31e
>  		>;
>  	};
>
> +	pinctrl_rtc: rtcgrp {
> +		fsl,pins = <
> +			MX93_PAD_ENET2_RD2__GPIO4_IO26		0x31e
> +		>;
> +	};
> +

keep order by node name.

Frank
>  	pinctrl_usdhc2_cd: usdhc2cdgrp {
>  		fsl,pins = <
>  			MX93_PAD_SD2_CD_B__GPIO3_IO00		0x31e
> --
> 2.34.1
>

Re: [PATCH 09/13] arm64: dts: freescale: imx93-phyboard-segin: Add RTC support

[Primoz Fiser]

Hi Frank,

On 10. 04. 25 17:12, Frank Li wrote:
> On Thu, Apr 10, 2025 at 11:02:47AM +0200, Primoz Fiser wrote:
>> Add support for RTC clock connected via I2C on phyBOARD-Segin-i.MX93.
>> Make I2C RTC the default clock by configuring the aliases.
> 
> "Add support for RTC connected via I2C on phyBOARD-Segin-i.MX93. Set
> default RTC by configuring the aliases."
> 
> Frank
>>
>> Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
>> ---
>>  .../dts/freescale/imx93-phyboard-segin.dts    | 36 +++++++++++++++++++
>>  1 file changed, 36 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
>> index 525f52789f8b..38b89398e646 100644
>> --- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
>> +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
>> @@ -17,6 +17,11 @@ /{
>>  	compatible = "phytec,imx93-phyboard-segin", "phytec,imx93-phycore-som",
>>  		     "fsl,imx93";
>>
>> +	aliases {
>> +		rtc0 = &i2c_rtc;
>> +		rtc1 = &bbnsm_rtc;
>> +	};
>> +
>>  	chosen {
>>  		stdout-path = &lpuart1;
>>  	};
>> @@ -33,6 +38,24 @@ reg_usdhc2_vmmc: regulator-usdhc2 {
>>  	};
>>  };
>>
>> +/* I2C2 */
>> +&lpi2c2 {
>> +	clock-frequency = <400000>;
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <&pinctrl_lpi2c2>;
>> +	status = "okay";
>> +
>> +	/* RTC */
>> +	i2c_rtc: rtc@68 {
>> +		compatible = "microcrystal,rv4162";
>> +		reg = <0x68>;
>> +		pinctrl-names = "default";
>> +		pinctrl-0 = <&pinctrl_rtc>;
>> +		interrupt-parent = <&gpio4>;
>> +		interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
>> +	};
>> +};
>> +
>>  /* Console */
>>  &lpuart1 {
>>  	pinctrl-names = "default";
>> @@ -56,6 +79,13 @@ &usdhc2 {
>>  };
>>
>>  &iomuxc {
>> +	pinctrl_lpi2c2: lpi2c2grp {
>> +		fsl,pins = <
>> +			MX93_PAD_I2C2_SCL__LPI2C2_SCL		0x40000b9e
>> +			MX93_PAD_I2C2_SDA__LPI2C2_SDA		0x40000b9e
>> +		>;
>> +	};
>> +
>>  	pinctrl_uart1: uart1grp {
>>  		fsl,pins = <
>>  			MX93_PAD_UART1_RXD__LPUART1_RX		0x31e
>> @@ -69,6 +99,12 @@ MX93_PAD_SD2_RESET_B__GPIO3_IO07	0x31e
>>  		>;
>>  	};
>>
>> +	pinctrl_rtc: rtcgrp {
>> +		fsl,pins = <
>> +			MX93_PAD_ENET2_RD2__GPIO4_IO26		0x31e
>> +		>;
>> +	};
>> +
> 
> keep order by node name.
> 

pinctrl_uart1 was out of order since beginning.

I will create a separate patch to this series ordering nodes
alphabetically as a last step.

OK?


> Frank
>>  	pinctrl_usdhc2_cd: usdhc2cdgrp {
>>  		fsl,pins = <
>>  			MX93_PAD_SD2_CD_B__GPIO3_IO00		0x31e
>> --
>> 2.34.1
>>

-- 
Primoz Fiser
phone: +386-41-390-545
email: primoz.fiser@norik.com
--
Norik systems d.o.o.
Your embedded software partner
Slovenia, EU
phone: +386-41-540-545
email: info@norik.com

[PATCH 10/13] arm64: dts: freescale: imx93-phyboard-segin: Add CAN support

[Primoz Fiser]

Add support for CAN networking on phyBOARD-Segin-i.MX93 via the flexcan1
interface. The CAN1_EN regulator enables the SN65HVD234 CAN transceiver
chip.

Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
---
 .../dts/freescale/imx93-phyboard-segin.dts    | 32 +++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
index 38b89398e646..027a34dbaf04 100644
--- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
+++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
@@ -26,6 +26,17 @@ chosen {
 		stdout-path = &lpuart1;
 	};
 
+	reg_flexcan1_en: regulator-flexcan1-en {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_reg_flexcan1_en>;
+		regulator-max-microvolt = <3300000>;
+		regulator-min-microvolt = <3300000>;
+		regulator-name = "CAN1_EN";
+	};
+
 	reg_usdhc2_vmmc: regulator-usdhc2 {
 		compatible = "regulator-fixed";
 		enable-active-high;
@@ -38,6 +49,14 @@ reg_usdhc2_vmmc: regulator-usdhc2 {
 	};
 };
 
+/* CAN */
+&flexcan1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan1>;
+	xceiver-supply = <&reg_flexcan1_en>;
+	status = "okay";
+};
+
 /* I2C2 */
 &lpi2c2 {
 	clock-frequency = <400000>;
@@ -79,6 +98,19 @@ &usdhc2 {
 };
 
 &iomuxc {
+	pinctrl_flexcan1: flexcan1grp {
+		fsl,pins = <
+			MX93_PAD_PDM_BIT_STREAM0__CAN1_RX	0x139e
+			MX93_PAD_PDM_CLK__CAN1_TX		0x139e
+		>;
+	};
+
+	pinctrl_reg_flexcan1_en: regflexcan1engrp {
+		fsl,pins = <
+			MX93_PAD_ENET2_TD3__GPIO4_IO16		0x31e
+		>;
+	};
+
 	pinctrl_lpi2c2: lpi2c2grp {
 		fsl,pins = <
 			MX93_PAD_I2C2_SCL__LPI2C2_SCL		0x40000b9e
-- 
2.34.1

Re: [PATCH 10/13] arm64: dts: freescale: imx93-phyboard-segin: Add CAN support

[Frank Li]

On Thu, Apr 10, 2025 at 11:02:48AM +0200, Primoz Fiser wrote:
> Add support for CAN networking on phyBOARD-Segin-i.MX93 via the flexcan1
> interface. The CAN1_EN regulator enables the SN65HVD234 CAN transceiver
> chip.

Can you use drivers/phy/phy-can-transceiver.c to enable CAN phy instead
of use hacked regulator-flexcan1-en.

Frank

>
> Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
> ---
>  .../dts/freescale/imx93-phyboard-segin.dts    | 32 +++++++++++++++++++
>  1 file changed, 32 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
> index 38b89398e646..027a34dbaf04 100644
> --- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
> +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
> @@ -26,6 +26,17 @@ chosen {
>  		stdout-path = &lpuart1;
>  	};
>
> +	reg_flexcan1_en: regulator-flexcan1-en {
> +		compatible = "regulator-fixed";
> +		enable-active-high;
> +		gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_reg_flexcan1_en>;
> +		regulator-max-microvolt = <3300000>;
> +		regulator-min-microvolt = <3300000>;
> +		regulator-name = "CAN1_EN";
> +	};
> +
>  	reg_usdhc2_vmmc: regulator-usdhc2 {
>  		compatible = "regulator-fixed";
>  		enable-active-high;
> @@ -38,6 +49,14 @@ reg_usdhc2_vmmc: regulator-usdhc2 {
>  	};
>  };
>
> +/* CAN */
> +&flexcan1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_flexcan1>;
> +	xceiver-supply = <&reg_flexcan1_en>;
> +	status = "okay";
> +};
> +
>  /* I2C2 */
>  &lpi2c2 {
>  	clock-frequency = <400000>;
> @@ -79,6 +98,19 @@ &usdhc2 {
>  };
>
>  &iomuxc {
> +	pinctrl_flexcan1: flexcan1grp {
> +		fsl,pins = <
> +			MX93_PAD_PDM_BIT_STREAM0__CAN1_RX	0x139e
> +			MX93_PAD_PDM_CLK__CAN1_TX		0x139e
> +		>;
> +	};
> +
> +	pinctrl_reg_flexcan1_en: regflexcan1engrp {
> +		fsl,pins = <
> +			MX93_PAD_ENET2_TD3__GPIO4_IO16		0x31e
> +		>;
> +	};
> +
>  	pinctrl_lpi2c2: lpi2c2grp {
>  		fsl,pins = <
>  			MX93_PAD_I2C2_SCL__LPI2C2_SCL		0x40000b9e
> --
> 2.34.1
>

Re: [PATCH 10/13] arm64: dts: freescale: imx93-phyboard-segin: Add CAN support

[Primoz Fiser]

Hi Frank,

On 10. 04. 25 17:23, Frank Li wrote:
> On Thu, Apr 10, 2025 at 11:02:48AM +0200, Primoz Fiser wrote:
>> Add support for CAN networking on phyBOARD-Segin-i.MX93 via the flexcan1
>> interface. The CAN1_EN regulator enables the SN65HVD234 CAN transceiver
>> chip.
> 
> Can you use drivers/phy/phy-can-transceiver.c to enable CAN phy instead
> of use hacked regulator-flexcan1-en.

Sorry can't do.

This doesn't align with other i.MX PHYTEC products using flexcan such as
imx8mp-phyboard-pollux-rdk.dts.

Even the i.MX93 EVK uses the same mechanism.

BR,
Primoz


> 
> Frank
> 
>>
>> Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
>> ---
>>  .../dts/freescale/imx93-phyboard-segin.dts    | 32 +++++++++++++++++++
>>  1 file changed, 32 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
>> index 38b89398e646..027a34dbaf04 100644
>> --- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
>> +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
>> @@ -26,6 +26,17 @@ chosen {
>>  		stdout-path = &lpuart1;
>>  	};
>>
>> +	reg_flexcan1_en: regulator-flexcan1-en {
>> +		compatible = "regulator-fixed";
>> +		enable-active-high;
>> +		gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>;
>> +		pinctrl-names = "default";
>> +		pinctrl-0 = <&pinctrl_reg_flexcan1_en>;
>> +		regulator-max-microvolt = <3300000>;
>> +		regulator-min-microvolt = <3300000>;
>> +		regulator-name = "CAN1_EN";
>> +	};
>> +
>>  	reg_usdhc2_vmmc: regulator-usdhc2 {
>>  		compatible = "regulator-fixed";
>>  		enable-active-high;
>> @@ -38,6 +49,14 @@ reg_usdhc2_vmmc: regulator-usdhc2 {
>>  	};
>>  };
>>
>> +/* CAN */
>> +&flexcan1 {
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <&pinctrl_flexcan1>;
>> +	xceiver-supply = <&reg_flexcan1_en>;
>> +	status = "okay";
>> +};
>> +
>>  /* I2C2 */
>>  &lpi2c2 {
>>  	clock-frequency = <400000>;
>> @@ -79,6 +98,19 @@ &usdhc2 {
>>  };
>>
>>  &iomuxc {
>> +	pinctrl_flexcan1: flexcan1grp {
>> +		fsl,pins = <
>> +			MX93_PAD_PDM_BIT_STREAM0__CAN1_RX	0x139e
>> +			MX93_PAD_PDM_CLK__CAN1_TX		0x139e
>> +		>;
>> +	};
>> +
>> +	pinctrl_reg_flexcan1_en: regflexcan1engrp {
>> +		fsl,pins = <
>> +			MX93_PAD_ENET2_TD3__GPIO4_IO16		0x31e
>> +		>;
>> +	};
>> +
>>  	pinctrl_lpi2c2: lpi2c2grp {
>>  		fsl,pins = <
>>  			MX93_PAD_I2C2_SCL__LPI2C2_SCL		0x40000b9e
>> --
>> 2.34.1
>>

-- 
Primoz Fiser
phone: +386-41-390-545
email: primoz.fiser@norik.com
--
Norik systems d.o.o.
Your embedded software partner
Slovenia, EU
phone: +386-41-540-545
email: info@norik.com

Re: [PATCH 10/13] arm64: dts: freescale: imx93-phyboard-segin: Add CAN support

[Frank Li]

On Fri, Apr 11, 2025 at 10:08:21AM +0200, Primoz Fiser wrote:
> Hi Frank,
>
> On 10. 04. 25 17:23, Frank Li wrote:
> > On Thu, Apr 10, 2025 at 11:02:48AM +0200, Primoz Fiser wrote:
> >> Add support for CAN networking on phyBOARD-Segin-i.MX93 via the flexcan1
> >> interface. The CAN1_EN regulator enables the SN65HVD234 CAN transceiver
> >> chip.
> >
> > Can you use drivers/phy/phy-can-transceiver.c to enable CAN phy instead
> > of use hacked regulator-flexcan1-en.
>
> Sorry can't do.
>
> This doesn't align with other i.MX PHYTEC products using flexcan such as
> imx8mp-phyboard-pollux-rdk.dts.
>
> Even the i.MX93 EVK uses the same mechanism.

I think previous method is NOT good enough. Suggest involve CAN and PHY
maintainer to discuss these.

Frank

>
> BR,
> Primoz
>
>
> >
> > Frank
> >
> >>
> >> Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
> >> ---
> >>  .../dts/freescale/imx93-phyboard-segin.dts    | 32 +++++++++++++++++++
> >>  1 file changed, 32 insertions(+)
> >>
> >> diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
> >> index 38b89398e646..027a34dbaf04 100644
> >> --- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
> >> +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
> >> @@ -26,6 +26,17 @@ chosen {
> >>  		stdout-path = &lpuart1;
> >>  	};
> >>
> >> +	reg_flexcan1_en: regulator-flexcan1-en {
> >> +		compatible = "regulator-fixed";
> >> +		enable-active-high;
> >> +		gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>;
> >> +		pinctrl-names = "default";
> >> +		pinctrl-0 = <&pinctrl_reg_flexcan1_en>;
> >> +		regulator-max-microvolt = <3300000>;
> >> +		regulator-min-microvolt = <3300000>;
> >> +		regulator-name = "CAN1_EN";
> >> +	};
> >> +
> >>  	reg_usdhc2_vmmc: regulator-usdhc2 {
> >>  		compatible = "regulator-fixed";
> >>  		enable-active-high;
> >> @@ -38,6 +49,14 @@ reg_usdhc2_vmmc: regulator-usdhc2 {
> >>  	};
> >>  };
> >>
> >> +/* CAN */
> >> +&flexcan1 {
> >> +	pinctrl-names = "default";
> >> +	pinctrl-0 = <&pinctrl_flexcan1>;
> >> +	xceiver-supply = <&reg_flexcan1_en>;
> >> +	status = "okay";
> >> +};
> >> +
> >>  /* I2C2 */
> >>  &lpi2c2 {
> >>  	clock-frequency = <400000>;
> >> @@ -79,6 +98,19 @@ &usdhc2 {
> >>  };
> >>
> >>  &iomuxc {
> >> +	pinctrl_flexcan1: flexcan1grp {
> >> +		fsl,pins = <
> >> +			MX93_PAD_PDM_BIT_STREAM0__CAN1_RX	0x139e
> >> +			MX93_PAD_PDM_CLK__CAN1_TX		0x139e
> >> +		>;
> >> +	};
> >> +
> >> +	pinctrl_reg_flexcan1_en: regflexcan1engrp {
> >> +		fsl,pins = <
> >> +			MX93_PAD_ENET2_TD3__GPIO4_IO16		0x31e
> >> +		>;
> >> +	};
> >> +
> >>  	pinctrl_lpi2c2: lpi2c2grp {
> >>  		fsl,pins = <
> >>  			MX93_PAD_I2C2_SCL__LPI2C2_SCL		0x40000b9e
> >> --
> >> 2.34.1
> >>
>
> --
> Primoz Fiser
> phone: +386-41-390-545
> email: primoz.fiser@norik.com
> --
> Norik systems d.o.o.
> Your embedded software partner
> Slovenia, EU
> phone: +386-41-540-545
> email: info@norik.com

Re: [PATCH 10/13] arm64: dts: freescale: imx93-phyboard-segin: Add CAN support

[Marc Kleine-Budde]

[-- Attachment #1: Type: text/plain, Size: 1368 bytes --]

On 11.04.2025 10:30:18, Frank Li wrote:
> On Fri, Apr 11, 2025 at 10:08:21AM +0200, Primoz Fiser wrote:
> > Hi Frank,
> >
> > On 10. 04. 25 17:23, Frank Li wrote:
> > > On Thu, Apr 10, 2025 at 11:02:48AM +0200, Primoz Fiser wrote:
> > >> Add support for CAN networking on phyBOARD-Segin-i.MX93 via the flexcan1
> > >> interface. The CAN1_EN regulator enables the SN65HVD234 CAN transceiver
> > >> chip.
> > >
> > > Can you use drivers/phy/phy-can-transceiver.c to enable CAN phy instead
> > > of use hacked regulator-flexcan1-en.
> >
> > Sorry can't do.
> >
> > This doesn't align with other i.MX PHYTEC products using flexcan such as
> > imx8mp-phyboard-pollux-rdk.dts.
> >
> > Even the i.MX93 EVK uses the same mechanism.
> 
> I think previous method is NOT good enough. Suggest involve CAN and PHY
> maintainer to discuss these.

Since d80bfde3c57a ("can: flexcan: add transceiver capabilities"), which
git mainline with v6.15-rc1 there is proper PHY support in the flexcan
driver. So from my point of view, there's no need to stick to regulator
hack.

regards,
Marc

-- 
Pengutronix e.K.                 | Marc Kleine-Budde          |
Embedded Linux                   | https://www.pengutronix.de |
Vertretung Nürnberg              | Phone: +49-5121-206917-129 |
Amtsgericht Hildesheim, HRA 2686 | Fax:   +49-5121-206917-9   |

[-- Attachment #2: signature.asc --]
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Re: [PATCH 10/13] arm64: dts: freescale: imx93-phyboard-segin: Add CAN support

[Primoz Fiser]

Hi Marc and Frank,

On 12. 04. 25 15:41, Marc Kleine-Budde wrote:
> On 11.04.2025 10:30:18, Frank Li wrote:
>> On Fri, Apr 11, 2025 at 10:08:21AM +0200, Primoz Fiser wrote:
>>> Hi Frank,
>>>
>>> On 10. 04. 25 17:23, Frank Li wrote:
>>>> On Thu, Apr 10, 2025 at 11:02:48AM +0200, Primoz Fiser wrote:
>>>>> Add support for CAN networking on phyBOARD-Segin-i.MX93 via the flexcan1
>>>>> interface. The CAN1_EN regulator enables the SN65HVD234 CAN transceiver
>>>>> chip.
>>>>
>>>> Can you use drivers/phy/phy-can-transceiver.c to enable CAN phy instead
>>>> of use hacked regulator-flexcan1-en.
>>>
>>> Sorry can't do.
>>>
>>> This doesn't align with other i.MX PHYTEC products using flexcan such as
>>> imx8mp-phyboard-pollux-rdk.dts.
>>>
>>> Even the i.MX93 EVK uses the same mechanism.
>>
>> I think previous method is NOT good enough. Suggest involve CAN and PHY
>> maintainer to discuss these.
> 
> Since d80bfde3c57a ("can: flexcan: add transceiver capabilities"), which
> git mainline with v6.15-rc1 there is proper PHY support in the flexcan
> driver. So from my point of view, there's no need to stick to regulator
> hack.

This arrived at the perfect moment. Just in time :)

I will switch to this mechanism in v2.

Thank you both for your input.

BR,
Primoz

> 
> regards,
> Marc
> 

-- 
Primoz Fiser
phone: +386-41-390-545
email: primoz.fiser@norik.com
--
Norik systems d.o.o.
Your embedded software partner
Slovenia, EU
phone: +386-41-540-545
email: info@norik.com

[PATCH 11/13] arm64: dts: freescale: imx93-phyboard-segin: Add USB support

[Primoz Fiser]

Add support for both USB controllers. Set first controller in OTG mode
(USB micro-AB connector X8) and the second one in host mode (USB type A
connector X7) by default. Note, the second controller is not OTG capable
due to HW design choice.

Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
---
 .../boot/dts/freescale/imx93-phyboard-segin.dts     | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
index 027a34dbaf04..faad3c3e627c 100644
--- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
+++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
@@ -82,6 +82,19 @@ &lpuart1 {
 	status = "okay";
 };
 
+/* USB  */
+&usbotg1 {
+	disable-over-current;
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&usbotg2 {
+	disable-over-current;
+	dr_mode = "host";
+	status = "okay";
+};
+
 /* SD-Card */
 &usdhc2 {
 	pinctrl-names = "default", "state_100mhz", "state_200mhz";
-- 
2.34.1

Re: [PATCH 11/13] arm64: dts: freescale: imx93-phyboard-segin: Add USB support

[Frank Li]

On Thu, Apr 10, 2025 at 11:02:49AM +0200, Primoz Fiser wrote:
> Add support for both USB controllers. Set first controller in OTG mode
> (USB micro-AB connector X8) and the second one in host mode (USB type A
> connector X7) by default. Note, the second controller is not OTG capable
> due to HW design choice.

I think note is reduntant. USB type A connector means host only.

Frank
>
> Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
> ---
>  .../boot/dts/freescale/imx93-phyboard-segin.dts     | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
> index 027a34dbaf04..faad3c3e627c 100644
> --- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
> +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
> @@ -82,6 +82,19 @@ &lpuart1 {
>  	status = "okay";
>  };
>
> +/* USB  */
> +&usbotg1 {
> +	disable-over-current;
> +	dr_mode = "otg";
> +	status = "okay";
> +};
> +
> +&usbotg2 {
> +	disable-over-current;
> +	dr_mode = "host";
> +	status = "okay";
> +};
> +
>  /* SD-Card */
>  &usdhc2 {
>  	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> --
> 2.34.1
>

Re: [PATCH 11/13] arm64: dts: freescale: imx93-phyboard-segin: Add USB support

[Ahmad Fatoum]

On 10.04.25 17:25, Frank Li wrote:
> On Thu, Apr 10, 2025 at 11:02:49AM +0200, Primoz Fiser wrote:
>> Add support for both USB controllers. Set first controller in OTG mode
>> (USB micro-AB connector X8) and the second one in host mode (USB type A
>> connector X7) by default. Note, the second controller is not OTG capable
>> due to HW design choice.
> 
> I think note is reduntant. USB type A connector means host only.

It's not uncommon for flashing to happen via a USB-A to USB-A cable, even
if it's against the spec. I'd say the note is useful.

Thanks,
Ahmad

> Frank
>>
>> Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
>> ---
>>  .../boot/dts/freescale/imx93-phyboard-segin.dts     | 13 +++++++++++++
>>  1 file changed, 13 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
>> index 027a34dbaf04..faad3c3e627c 100644
>> --- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
>> +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
>> @@ -82,6 +82,19 @@ &lpuart1 {
>>  	status = "okay";
>>  };
>>
>> +/* USB  */
>> +&usbotg1 {
>> +	disable-over-current;
>> +	dr_mode = "otg";
>> +	status = "okay";
>> +};
>> +
>> +&usbotg2 {
>> +	disable-over-current;
>> +	dr_mode = "host";
>> +	status = "okay";
>> +};
>> +
>>  /* SD-Card */
>>  &usdhc2 {
>>  	pinctrl-names = "default", "state_100mhz", "state_200mhz";
>> --
>> 2.34.1
>>
> 
> 


-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

[PATCH 12/13] arm64: dts: freescale: imx93-phyboard-segin: Add I2S audio

[Primoz Fiser]

Add support for I2S audio found on phyBOARD-Segin-i.MX93. Audio codec
TLV320AIC3007 is connected to SAI1 interface as a DAI master. MCLK is
provided from the SAI's internal audio PLL (19.2 MHz).

Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
---
 .../dts/freescale/imx93-phyboard-segin.dts    | 75 +++++++++++++++++++
 1 file changed, 75 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
index faad3c3e627c..08574b146400 100644
--- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
+++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
@@ -37,6 +37,20 @@ reg_flexcan1_en: regulator-flexcan1-en {
 		regulator-name = "CAN1_EN";
 	};
 
+	reg_sound_1v8: regulator-sound-1v8 {
+		compatible = "regulator-fixed";
+		regulator-max-microvolt = <1800000>;
+		regulator-min-microvolt = <1800000>;
+		regulator-name = "VCC1V8_AUDIO";
+	};
+
+	reg_sound_3v3: regulator-sound-3v3 {
+		compatible = "regulator-fixed";
+		regulator-max-microvolt = <3300000>;
+		regulator-min-microvolt = <3300000>;
+		regulator-name = "VCC3V3_ANALOG";
+	};
+
 	reg_usdhc2_vmmc: regulator-usdhc2 {
 		compatible = "regulator-fixed";
 		enable-active-high;
@@ -47,6 +61,34 @@ reg_usdhc2_vmmc: regulator-usdhc2 {
 		regulator-max-microvolt = <3300000>;
 		regulator-name = "VCC_SD";
 	};
+
+	sound: sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "phyBOARD-Segin-TLV320AIC3007";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,bitclock-master = <&dailink_master>;
+		simple-audio-card,frame-master = <&dailink_master>;
+		simple-audio-card,widgets =
+			"Line", "Line In",
+			"Line", "Line Out",
+			"Speaker", "Speaker";
+		simple-audio-card,routing =
+			"Line Out", "LLOUT",
+			"Line Out", "RLOUT",
+			"Speaker", "SPOP",
+			"Speaker", "SPOM",
+			"LINE1L", "Line In",
+			"LINE1R", "Line In";
+
+		simple-audio-card,cpu {
+			sound-dai = <&sai1>;
+		};
+
+		dailink_master: simple-audio-card,codec {
+			sound-dai = <&audio_codec>;
+			clocks = <&clk IMX93_CLK_SAI1>;
+		};
+	};
 };
 
 /* CAN */
@@ -64,6 +106,18 @@ &lpi2c2 {
 	pinctrl-0 = <&pinctrl_lpi2c2>;
 	status = "okay";
 
+	/* Codec */
+	audio_codec: audio-codec@18 {
+		compatible = "ti,tlv320aic3007";
+		reg = <0x18>;
+		#sound-dai-cells = <0>;
+
+		AVDD-supply = <&reg_sound_3v3>;
+		IOVDD-supply = <&reg_sound_3v3>;
+		DRVDD-supply = <&reg_sound_3v3>;
+		DVDD-supply = <&reg_sound_1v8>;
+	};
+
 	/* RTC */
 	i2c_rtc: rtc@68 {
 		compatible = "microcrystal,rv4162";
@@ -82,6 +136,17 @@ &lpuart1 {
 	status = "okay";
 };
 
+/* Audio */
+&sai1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sai1>;
+	assigned-clocks = <&clk IMX93_CLK_SAI1>;
+	assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
+	assigned-clock-rates = <19200000>;
+	fsl,sai-mclk-direction-output;
+	status = "okay";
+};
+
 /* USB  */
 &usbotg1 {
 	disable-over-current;
@@ -150,6 +215,16 @@ MX93_PAD_ENET2_RD2__GPIO4_IO26		0x31e
 		>;
 	};
 
+	pinctrl_sai1: sai1grp {
+		fsl,pins = <
+			MX93_PAD_UART2_RXD__SAI1_MCLK		0x1202
+			MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC	0x1202
+			MX93_PAD_SAI1_TXC__SAI1_TX_BCLK		0x1202
+			MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00	0x1402
+			MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00	0x1402
+		>;
+	};
+
 	pinctrl_usdhc2_cd: usdhc2cdgrp {
 		fsl,pins = <
 			MX93_PAD_SD2_CD_B__GPIO3_IO00		0x31e
-- 
2.34.1

Re: [PATCH 12/13] arm64: dts: freescale: imx93-phyboard-segin: Add I2S audio

[Frank Li]

On Thu, Apr 10, 2025 at 11:02:50AM +0200, Primoz Fiser wrote:
> Add support for I2S audio found on phyBOARD-Segin-i.MX93. Audio codec
> TLV320AIC3007 is connected to SAI1 interface as a DAI master. MCLK is
> provided from the SAI's internal audio PLL (19.2 MHz).
>
> Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
> ---
>  .../dts/freescale/imx93-phyboard-segin.dts    | 75 +++++++++++++++++++
>  1 file changed, 75 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
> index faad3c3e627c..08574b146400 100644
> --- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
> +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
> @@ -37,6 +37,20 @@ reg_flexcan1_en: regulator-flexcan1-en {
>  		regulator-name = "CAN1_EN";
>  	};
>
> +	reg_sound_1v8: regulator-sound-1v8 {
> +		compatible = "regulator-fixed";
> +		regulator-max-microvolt = <1800000>;
> +		regulator-min-microvolt = <1800000>;
> +		regulator-name = "VCC1V8_AUDIO";
> +	};
> +
> +	reg_sound_3v3: regulator-sound-3v3 {
> +		compatible = "regulator-fixed";
> +		regulator-max-microvolt = <3300000>;
> +		regulator-min-microvolt = <3300000>;
> +		regulator-name = "VCC3V3_ANALOG";
> +	};
> +
>  	reg_usdhc2_vmmc: regulator-usdhc2 {
>  		compatible = "regulator-fixed";
>  		enable-active-high;
> @@ -47,6 +61,34 @@ reg_usdhc2_vmmc: regulator-usdhc2 {
>  		regulator-max-microvolt = <3300000>;
>  		regulator-name = "VCC_SD";
>  	};
> +
> +	sound: sound {
> +		compatible = "simple-audio-card";
> +		simple-audio-card,name = "phyBOARD-Segin-TLV320AIC3007";
> +		simple-audio-card,format = "i2s";
> +		simple-audio-card,bitclock-master = <&dailink_master>;
> +		simple-audio-card,frame-master = <&dailink_master>;
> +		simple-audio-card,widgets =
> +			"Line", "Line In",
> +			"Line", "Line Out",
> +			"Speaker", "Speaker";
> +		simple-audio-card,routing =
> +			"Line Out", "LLOUT",
> +			"Line Out", "RLOUT",
> +			"Speaker", "SPOP",
> +			"Speaker", "SPOM",
> +			"LINE1L", "Line In",
> +			"LINE1R", "Line In";
> +
> +		simple-audio-card,cpu {
> +			sound-dai = <&sai1>;
> +		};
> +
> +		dailink_master: simple-audio-card,codec {
> +			sound-dai = <&audio_codec>;
> +			clocks = <&clk IMX93_CLK_SAI1>;
> +		};
> +	};
>  };
>
>  /* CAN */
> @@ -64,6 +106,18 @@ &lpi2c2 {
>  	pinctrl-0 = <&pinctrl_lpi2c2>;
>  	status = "okay";
>
> +	/* Codec */
> +	audio_codec: audio-codec@18 {
> +		compatible = "ti,tlv320aic3007";
> +		reg = <0x18>;
> +		#sound-dai-cells = <0>;
> +

needn't empty line here.

Reviewed-by: Frank Li <Frank.Li@nxp.com>

> +		AVDD-supply = <&reg_sound_3v3>;
> +		IOVDD-supply = <&reg_sound_3v3>;
> +		DRVDD-supply = <&reg_sound_3v3>;
> +		DVDD-supply = <&reg_sound_1v8>;
> +	};
> +
>  	/* RTC */
>  	i2c_rtc: rtc@68 {
>  		compatible = "microcrystal,rv4162";
> @@ -82,6 +136,17 @@ &lpuart1 {
>  	status = "okay";
>  };
>
> +/* Audio */
> +&sai1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_sai1>;
> +	assigned-clocks = <&clk IMX93_CLK_SAI1>;
> +	assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
> +	assigned-clock-rates = <19200000>;
> +	fsl,sai-mclk-direction-output;
> +	status = "okay";
> +};
> +
>  /* USB  */
>  &usbotg1 {
>  	disable-over-current;
> @@ -150,6 +215,16 @@ MX93_PAD_ENET2_RD2__GPIO4_IO26		0x31e
>  		>;
>  	};
>
> +	pinctrl_sai1: sai1grp {
> +		fsl,pins = <
> +			MX93_PAD_UART2_RXD__SAI1_MCLK		0x1202
> +			MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC	0x1202
> +			MX93_PAD_SAI1_TXC__SAI1_TX_BCLK		0x1202
> +			MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00	0x1402
> +			MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00	0x1402
> +		>;
> +	};
> +
>  	pinctrl_usdhc2_cd: usdhc2cdgrp {
>  		fsl,pins = <
>  			MX93_PAD_SD2_CD_B__GPIO3_IO00		0x31e
> --
> 2.34.1
>

[PATCH 13/13] arm64: dts: freescale: imx93-phyboard-segin: Add EQOS Ethernet

[Primoz Fiser]

Add support for the carrier-board Micrel KSZ8081 Ethernet PHY. This is a
10/100Mbit PHY connected to the EQOS interface and shares MDIO bus with
the Ethernet PHY located on the SoM (FEC interface).

Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
---
 .../dts/freescale/imx93-phyboard-segin.dts    | 35 +++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
index 08574b146400..92f0cb6eca26 100644
--- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
+++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
@@ -91,6 +91,28 @@ dailink_master: simple-audio-card,codec {
 	};
 };
 
+/* Ethernet */
+&eqos {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_eqos>;
+	phy-mode = "rmii";
+	phy-handle = <&ethphy2>;
+	assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
+				 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
+	assigned-clock-rates = <100000000>, <50000000>;
+	status = "okay";
+};
+
+&mdio {
+	ethphy2: ethernet-phy@2 {
+		compatible = "ethernet-phy-id0022.1561";
+		reg = <2>;
+		clocks = <&clk IMX93_CLK_ENET_REF_PHY>;
+		clock-names = "rmii-ref";
+		micrel,led-mode = <1>;
+	};
+};
+
 /* CAN */
 &flexcan1 {
 	pinctrl-names = "default";
@@ -176,6 +198,19 @@ &usdhc2 {
 };
 
 &iomuxc {
+	pinctrl_eqos: eqosgrp {
+		fsl,pins = <
+			MX93_PAD_ENET1_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK	0x4000050e
+			MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0		0x57e
+			MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1		0x57e
+			MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0		0x50e
+			MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1		0x50e
+			MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL	0x57e
+			MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL	0x50e
+			MX93_PAD_ENET1_RXC__ENET_QOS_RX_ER		0x57e
+		>;
+	};
+
 	pinctrl_flexcan1: flexcan1grp {
 		fsl,pins = <
 			MX93_PAD_PDM_BIT_STREAM0__CAN1_RX	0x139e
-- 
2.34.1

Re: [PATCH 13/13] arm64: dts: freescale: imx93-phyboard-segin: Add EQOS Ethernet

[Frank Li]

On Thu, Apr 10, 2025 at 11:02:51AM +0200, Primoz Fiser wrote:
> Add support for the carrier-board Micrel KSZ8081 Ethernet PHY. This is a
> 10/100Mbit PHY connected to the EQOS interface and shares MDIO bus with
> the Ethernet PHY located on the SoM (FEC interface).
>
> Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
> ---

Reviewed-by: Frank Li <Frank.Li@nxp.com>

>  .../dts/freescale/imx93-phyboard-segin.dts    | 35 +++++++++++++++++++
>  1 file changed, 35 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
> index 08574b146400..92f0cb6eca26 100644
> --- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
> +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
> @@ -91,6 +91,28 @@ dailink_master: simple-audio-card,codec {
>  	};
>  };
>
> +/* Ethernet */
> +&eqos {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_eqos>;
> +	phy-mode = "rmii";
> +	phy-handle = <&ethphy2>;
> +	assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
> +				 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
> +	assigned-clock-rates = <100000000>, <50000000>;
> +	status = "okay";
> +};
> +
> +&mdio {
> +	ethphy2: ethernet-phy@2 {
> +		compatible = "ethernet-phy-id0022.1561";
> +		reg = <2>;
> +		clocks = <&clk IMX93_CLK_ENET_REF_PHY>;
> +		clock-names = "rmii-ref";
> +		micrel,led-mode = <1>;
> +	};
> +};
> +
>  /* CAN */
>  &flexcan1 {
>  	pinctrl-names = "default";
> @@ -176,6 +198,19 @@ &usdhc2 {
>  };
>
>  &iomuxc {
> +	pinctrl_eqos: eqosgrp {
> +		fsl,pins = <
> +			MX93_PAD_ENET1_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK	0x4000050e
> +			MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0		0x57e
> +			MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1		0x57e
> +			MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0		0x50e
> +			MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1		0x50e
> +			MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL	0x57e
> +			MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL	0x50e
> +			MX93_PAD_ENET1_RXC__ENET_QOS_RX_ER		0x57e
> +		>;
> +	};
> +
>  	pinctrl_flexcan1: flexcan1grp {
>  		fsl,pins = <
>  			MX93_PAD_PDM_BIT_STREAM0__CAN1_RX	0x139e
> --
> 2.34.1
>