[PATCH v3 0/3] Add clock controller support for Spacemit K1

[PATCH v3 0/3] Add clock controller support for Spacemit K1

[Haylen Chu]

The clock tree of Spacemit K1 is managed by several independent
controllers in different SoC parts. In this series, all clock hardwares
in APBS, MPMU, APBC and APMU, are implemented. With some changes to UART
driver, CPU cores and UARTs could be brought up (see below). More clocks
will be implemented later soon.

No device tree changes are included since Spacemit K1 UART needs two
clocks to operate, but for now the driver gets only one. I would like to
defer the changes until this is resolved.

This driver has been tested on BananaPi-F3 board and successfully
brought up I2C, RTC, mmc and ethernet controllers. A clock tree dump
could be obtained here[1].

[1]: https://gist.github.com/heylenayy/ebc6316692dd3aff56575dbf0eb4f1a9

Link: https://developer.spacemit.com/documentation?token=LCrKwWDasiJuROkVNusc2pWTnEb

Changed from v2
- dt-binding fixes
- misc improvements in code
- drop unnecessary spinlock in the driver
- implement missing bus clocks
- Link to v2: https://lore.kernel.org/all/SEYPR01MB4221829A2CD4D4C1704BABD7D7602@SEYPR01MB4221.apcprd01.prod.exchangelabs.com/

Changed from v1
- add SoC prefix (k1)
- relicense dt-binding header
- misc fixes and style improvements for dt-binding
- document spacemit,k1-syscon
- implement all APBS, MPMU, APBC and APMU clocks
- code cleanup
- Link to v1: https://lore.kernel.org/all/SEYPR01MB4221B3178F5233EAB5149E41D7902@SEYPR01MB4221.apcprd01.prod.exchangelabs.com/

Haylen Chu (3):
  dt-bindings: clock: spacemit: Add clock controllers of Spacemit K1 SoC
  dt-bindings: soc: spacemit: Add spacemit,k1-syscon
  clk: spacemit: Add clock support for Spacemit K1 SoC

 .../bindings/clock/spacemit,k1-ccu.yaml       |   57 +
 .../soc/spacemit/spacemit,k1-syscon.yaml      |   86 +
 drivers/clk/Kconfig                           |    1 +
 drivers/clk/Makefile                          |    1 +
 drivers/clk/spacemit/Kconfig                  |   20 +
 drivers/clk/spacemit/Makefile                 |    5 +
 drivers/clk/spacemit/ccu-k1.c                 | 1747 +++++++++++++++++
 drivers/clk/spacemit/ccu_common.h             |   62 +
 drivers/clk/spacemit/ccu_ddn.c                |  146 ++
 drivers/clk/spacemit/ccu_ddn.h                |   85 +
 drivers/clk/spacemit/ccu_mix.c                |  296 +++
 drivers/clk/spacemit/ccu_mix.h                |  336 ++++
 drivers/clk/spacemit/ccu_pll.c                |  198 ++
 drivers/clk/spacemit/ccu_pll.h                |   80 +
 include/dt-bindings/clock/spacemit,k1-ccu.h   |  246 +++
 15 files changed, 3366 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/spacemit,k1-ccu.yaml
 create mode 100644 Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml
 create mode 100644 drivers/clk/spacemit/Kconfig
 create mode 100644 drivers/clk/spacemit/Makefile
 create mode 100644 drivers/clk/spacemit/ccu-k1.c
 create mode 100644 drivers/clk/spacemit/ccu_common.h
 create mode 100644 drivers/clk/spacemit/ccu_ddn.c
 create mode 100644 drivers/clk/spacemit/ccu_ddn.h
 create mode 100644 drivers/clk/spacemit/ccu_mix.c
 create mode 100644 drivers/clk/spacemit/ccu_mix.h
 create mode 100644 drivers/clk/spacemit/ccu_pll.c
 create mode 100644 drivers/clk/spacemit/ccu_pll.h
 create mode 100644 include/dt-bindings/clock/spacemit,k1-ccu.h


base-commit: 2d5404caa8c7bb5c4e0435f94b28834ae5456623
prerequisite-patch-id: 47dcf6861f7d434d25855b379e6d7ef4ce369c9c
prerequisite-patch-id: 77787fe82911923aff15ccf565e8fa451538c3a6
prerequisite-patch-id: b0bdb1742d96c5738f05262c3b0059102761390b
prerequisite-patch-id: 3927d39d8d77e35d5bfe53d9950da574ff8f2054
prerequisite-patch-id: a98039136a4796252a6029e474f03906f2541643
prerequisite-patch-id: c95f6dc0547a2a63a76e3cba0cf5c623b212b4e6
prerequisite-patch-id: 66e750e438ee959ddc2a6f0650814a2d8c989139
prerequisite-patch-id: 29a0fd8c36c1a4340f0d0b68a4c34d2b8abfb1ab
prerequisite-patch-id: 0bdfff661c33c380d1cf00a6c68688e05f88c0b3
prerequisite-patch-id: 99f15718e0bfbb7ed1a96dfa19f35841b004dae9
-- 
2.47.0

[PATCH v3 1/3] dt-bindings: clock: spacemit: Add clock controllers of Spacemit K1 SoC

[Haylen Chu]

Add definition for the clock controllers of Spacemit K1 SoC. The clock
tree is managed by several SoC parts thus different compatible strings
are introduced for each.

Signed-off-by: Haylen Chu <heylenay@4d2.org>
---
 .../bindings/clock/spacemit,k1-ccu.yaml       |  57 ++++
 include/dt-bindings/clock/spacemit,k1-ccu.h   | 246 ++++++++++++++++++
 2 files changed, 303 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/spacemit,k1-ccu.yaml
 create mode 100644 include/dt-bindings/clock/spacemit,k1-ccu.h

diff --git a/Documentation/devicetree/bindings/clock/spacemit,k1-ccu.yaml b/Documentation/devicetree/bindings/clock/spacemit,k1-ccu.yaml
new file mode 100644
index 000000000000..9a12ac29c6e2
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/spacemit,k1-ccu.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/spacemit,k1-ccu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Spacemit K1 SoC Clock Controller
+
+maintainers:
+  - Haylen Chu <heylenay@4d2.org>
+
+properties:
+  compatible:
+    enum:
+      - spacemit,k1-ccu-apbs
+      - spacemit,k1-ccu-mpmu
+      - spacemit,k1-ccu-apbc
+      - spacemit,k1-ccu-apmu
+
+  clocks:
+    maxItems: 4
+
+  clock-names:
+    items:
+      - const: osc_32k
+      - const: vctcxo_1m
+      - const: vctcxo_3m
+      - const: vctcxo_24m
+
+  spacemit,mpmu:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description:
+      Phandle to the syscon managing "Main PMU (MPMU)" registers. It is used to
+      check PLL lock status.
+
+  "#clock-cells":
+    const: 1
+    description:
+      See <dt-bindings/clock/spacemit,k1-ccu.h> for valid indices.
+
+required:
+  - compatible
+  - clocks
+  - clock-names
+  - "#clock-cells"
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: spacemit,k1-ccu-apbs
+    then:
+      required:
+        - spacemit,mpmu
+
+additionalProperties: false
diff --git a/include/dt-bindings/clock/spacemit,k1-ccu.h b/include/dt-bindings/clock/spacemit,k1-ccu.h
new file mode 100644
index 000000000000..71760355b304
--- /dev/null
+++ b/include/dt-bindings/clock/spacemit,k1-ccu.h
@@ -0,0 +1,246 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2024 Haylen Chu <heylenay@outlook.com>
+ */
+
+#ifndef _DT_BINDINGS_SPACEMIT_CCU_H_
+#define _DT_BINDINGS_SPACEMIT_CCU_H_
+
+/*	APBS clocks	*/
+#define CLK_PLL1		0
+#define CLK_PLL2		1
+#define CLK_PLL3		2
+#define CLK_PLL1_D2		3
+#define CLK_PLL1_D3		4
+#define CLK_PLL1_D4		5
+#define CLK_PLL1_D5		6
+#define CLK_PLL1_D6		7
+#define CLK_PLL1_D7		8
+#define CLK_PLL1_D8		9
+#define CLK_PLL1_D11		10
+#define CLK_PLL1_D13		11
+#define CLK_PLL1_D23		12
+#define CLK_PLL1_D64		13
+#define CLK_PLL1_D10_AUD	14
+#define CLK_PLL1_D100_AUD	15
+#define CLK_PLL2_D1		16
+#define CLK_PLL2_D2		17
+#define CLK_PLL2_D3		18
+#define CLK_PLL2_D4		19
+#define CLK_PLL2_D5		20
+#define CLK_PLL2_D6		21
+#define CLK_PLL2_D7		22
+#define CLK_PLL2_D8		23
+#define CLK_PLL3_D1		24
+#define CLK_PLL3_D2		25
+#define CLK_PLL3_D3		26
+#define CLK_PLL3_D4		27
+#define CLK_PLL3_D5		28
+#define CLK_PLL3_D6		29
+#define CLK_PLL3_D7		30
+#define CLK_PLL3_D8		31
+#define CLK_PLL3_80		32
+#define CLK_PLL3_40		33
+#define CLK_PLL3_20		34
+#define CLK_APBS_NUM		35
+
+/*	MPMU clocks	*/
+#define CLK_PLL1_307P2		0
+#define CLK_PLL1_76P8		1
+#define CLK_PLL1_61P44		2
+#define CLK_PLL1_153P6		3
+#define CLK_PLL1_102P4		4
+#define CLK_PLL1_51P2		5
+#define CLK_PLL1_51P2_AP	6
+#define CLK_PLL1_57P6		7
+#define CLK_PLL1_25P6		8
+#define CLK_PLL1_12P8		9
+#define CLK_PLL1_12P8_WDT	10
+#define CLK_PLL1_6P4		11
+#define CLK_PLL1_3P2		12
+#define CLK_PLL1_1P6		13
+#define CLK_PLL1_0P8		14
+#define CLK_PLL1_351		15
+#define CLK_PLL1_409P6		16
+#define CLK_PLL1_204P8		17
+#define CLK_PLL1_491		18
+#define CLK_PLL1_245P76		19
+#define CLK_PLL1_614		20
+#define CLK_PLL1_47P26		21
+#define CLK_PLL1_31P5		22
+#define CLK_PLL1_819		23
+#define CLK_PLL1_1228		24
+#define CLK_SLOW_UART		25
+#define CLK_SLOW_UART1		26
+#define CLK_SLOW_UART2		27
+#define CLK_WDT			28
+#define CLK_RIPC		29
+#define CLK_I2S_SYSCLK		30
+#define CLK_I2S_BCLK		31
+#define CLK_APB			32
+#define CLK_WDT_BUS		33
+#define CLK_MPMU_NUM		34
+
+/*	APBC clocks	*/
+#define CLK_UART0		0
+#define CLK_UART2		1
+#define CLK_UART3		2
+#define CLK_UART4		3
+#define CLK_UART5		4
+#define CLK_UART6		5
+#define CLK_UART7		6
+#define CLK_UART8		7
+#define CLK_UART9		8
+#define CLK_GPIO		9
+#define CLK_PWM0		10
+#define CLK_PWM1		11
+#define CLK_PWM2		12
+#define CLK_PWM3		13
+#define CLK_PWM4		14
+#define CLK_PWM5		15
+#define CLK_PWM6		16
+#define CLK_PWM7		17
+#define CLK_PWM8		18
+#define CLK_PWM9		19
+#define CLK_PWM10		20
+#define CLK_PWM11		21
+#define CLK_PWM12		22
+#define CLK_PWM13		23
+#define CLK_PWM14		24
+#define CLK_PWM15		25
+#define CLK_PWM16		26
+#define CLK_PWM17		27
+#define CLK_PWM18		28
+#define CLK_PWM19		29
+#define CLK_SSP3		30
+#define CLK_RTC			31
+#define CLK_TWSI0		32
+#define CLK_TWSI1		33
+#define CLK_TWSI2		34
+#define CLK_TWSI4		35
+#define CLK_TWSI5		36
+#define CLK_TWSI6		37
+#define CLK_TWSI7		38
+#define CLK_TWSI8		39
+#define CLK_TIMERS1		40
+#define CLK_TIMERS2		41
+#define CLK_AIB			42
+#define CLK_ONEWIRE		43
+#define CLK_SSPA0		44
+#define CLK_SSPA1		45
+#define CLK_DRO			46
+#define CLK_IR			47
+#define CLK_TSEN		48
+#define CLK_IPC_AP2AUD		49
+#define CLK_CAN0		50
+#define CLK_CAN0_BUS		51
+#define CLK_UART0_BUS		52
+#define CLK_UART2_BUS		53
+#define CLK_UART3_BUS		54
+#define CLK_UART4_BUS		55
+#define CLK_UART5_BUS		56
+#define CLK_UART6_BUS		57
+#define CLK_UART7_BUS		58
+#define CLK_UART8_BUS		59
+#define CLK_UART9_BUS		60
+#define CLK_GPIO_BUS		61
+#define CLK_PWM0_BUS		62
+#define CLK_PWM1_BUS		63
+#define CLK_PWM2_BUS		64
+#define CLK_PWM3_BUS		65
+#define CLK_PWM4_BUS		66
+#define CLK_PWM5_BUS		67
+#define CLK_PWM6_BUS		68
+#define CLK_PWM7_BUS		69
+#define CLK_PWM8_BUS		70
+#define CLK_PWM9_BUS		71
+#define CLK_PWM10_BUS		72
+#define CLK_PWM11_BUS		73
+#define CLK_PWM12_BUS		74
+#define CLK_PWM13_BUS		75
+#define CLK_PWM14_BUS		76
+#define CLK_PWM15_BUS		77
+#define CLK_PWM16_BUS		78
+#define CLK_PWM17_BUS		79
+#define CLK_PWM18_BUS		80
+#define CLK_PWM19_BUS		81
+#define CLK_SSP3_BUS		82
+#define CLK_RTC_BUS		83
+#define CLK_TWSI0_BUS		84
+#define CLK_TWSI1_BUS		85
+#define CLK_TWSI2_BUS		86
+#define CLK_TWSI4_BUS		87
+#define CLK_TWSI5_BUS		88
+#define CLK_TWSI6_BUS		89
+#define CLK_TWSI7_BUS		90
+#define CLK_TWSI8_BUS		91
+#define CLK_TIMERS1_BUS		92
+#define CLK_TIMERS2_BUS		93
+#define CLK_AIB_BUS		94
+#define CLK_ONEWIRE_BUS		95
+#define CLK_SSPA0_BUS		96
+#define CLK_SSPA1_BUS		97
+#define CLK_TSEN_BUS		98
+#define CLK_IPC_AP2AUD_BUS	99
+#define CLK_APBC_NUM		100
+
+/*	APMU clocks	*/
+#define CLK_CCI550		0
+#define CLK_CPU_C0_HI		1
+#define CLK_CPU_C0_CORE		2
+#define CLK_CPU_C0_ACE		3
+#define CLK_CPU_C0_TCM		4
+#define CLK_CPU_C1_HI		5
+#define CLK_CPU_C1_CORE		6
+#define CLK_CPU_C1_ACE		7
+#define CLK_CCIC_4X		8
+#define CLK_CCIC1PHY		9
+#define CLK_SDH_AXI		10
+#define CLK_SDH0		11
+#define CLK_SDH1		12
+#define CLK_SDH2		13
+#define CLK_USB_P1		14
+#define CLK_USB_AXI		15
+#define CLK_USB30		16
+#define CLK_QSPI		17
+#define CLK_QSPI_BUS		18
+#define CLK_DMA			19
+#define CLK_AES			20
+#define CLK_VPU			21
+#define CLK_GPU			22
+#define CLK_EMMC		23
+#define CLK_EMMC_X		24
+#define CLK_AUDIO		25
+#define CLK_HDMI		26
+#define CLK_PMUA_ACLK		27
+#define CLK_PCIE0		28
+#define CLK_PCIE1		29
+#define CLK_PCIE2		30
+#define CLK_EMAC0_BUS		31
+#define CLK_EMAC0_PTP		32
+#define CLK_EMAC1_BUS		33
+#define CLK_EMAC1_PTP		34
+#define CLK_JPG			35
+#define CLK_CCIC2PHY		36
+#define CLK_CCIC3PHY		37
+#define CLK_CSI			38
+#define CLK_CAMM0		39
+#define CLK_CAMM1		40
+#define CLK_CAMM2		41
+#define CLK_ISP_CPP		42
+#define CLK_ISP_BUS		43
+#define CLK_ISP			44
+#define CLK_DPU_MCLK		45
+#define CLK_DPU_ESC		46
+#define CLK_DPU_BIT		47
+#define CLK_DPU_PXCLK		48
+#define CLK_DPU_HCLK		49
+#define CLK_DPU_SPI		50
+#define CLK_DPU_SPI_HBUS	51
+#define CLK_DPU_SPIBUS		52
+#define CLK_DPU_SPI_ACLK	53
+#define CLK_V2D			54
+#define CLK_EMMC_BUS		55
+#define CLK_APMU_NUM		56
+
+#endif /* _DT_BINDINGS_SPACEMIT_CCU_H_ */
-- 
2.47.0

Re: [PATCH v3 1/3] dt-bindings: clock: spacemit: Add clock controllers of Spacemit K1 SoC

[Krzysztof Kozlowski]

On 26/11/2024 15:31, Haylen Chu wrote:
> +
> +properties:
> +  compatible:
> +    enum:
> +      - spacemit,k1-ccu-apbs
> +      - spacemit,k1-ccu-mpmu
> +      - spacemit,k1-ccu-apbc
> +      - spacemit,k1-ccu-apmu
> +
> +  clocks:
> +    maxItems: 4
> +
> +  clock-names:
> +    items:
> +      - const: osc_32k

osc

> +      - const: vctcxo_1m
> +      - const: vctcxo_3m
> +      - const: vctcxo_24m
> +
> +  spacemit,mpmu:
> +    $ref: /schemas/types.yaml#/definitions/phandle
> +    description:
> +      Phandle to the syscon managing "Main PMU (MPMU)" registers. It is used to
> +      check PLL lock status.

Why your example does not have it? Example code is supposed to be complete.

Best regards,
Krzysztof

Re: [PATCH v3 1/3] dt-bindings: clock: spacemit: Add clock controllers of Spacemit K1 SoC

[Krzysztof Kozlowski]

On Tue, Nov 26, 2024 at 03:48:33PM +0100, Krzysztof Kozlowski wrote:
> On 26/11/2024 15:31, Haylen Chu wrote:
> > +
> > +properties:
> > +  compatible:
> > +    enum:
> > +      - spacemit,k1-ccu-apbs
> > +      - spacemit,k1-ccu-mpmu
> > +      - spacemit,k1-ccu-apbc
> > +      - spacemit,k1-ccu-apmu
> > +
> > +  clocks:
> > +    maxItems: 4
> > +
> > +  clock-names:
> > +    items:
> > +      - const: osc_32k
> 
> osc
> 
> > +      - const: vctcxo_1m
> > +      - const: vctcxo_3m
> > +      - const: vctcxo_24m
> > +
> > +  spacemit,mpmu:
> > +    $ref: /schemas/types.yaml#/definitions/phandle
> > +    description:
> > +      Phandle to the syscon managing "Main PMU (MPMU)" registers. It is used to
> > +      check PLL lock status.
> 
> Why your example does not have it? Example code is supposed to be complete.

I think I understand why - this is for only one variant? But then this
should be disallowed in your binding for others. Currently your binding
says that it is required for one and allowed for others.

Best regards,
Krzysztof

Re: [PATCH v3 1/3] dt-bindings: clock: spacemit: Add clock controllers of Spacemit K1 SoC

[Haylen Chu]

On Wed, Nov 27, 2024 at 09:03:11AM +0100, Krzysztof Kozlowski wrote:
> On Tue, Nov 26, 2024 at 03:48:33PM +0100, Krzysztof Kozlowski wrote:
> > On 26/11/2024 15:31, Haylen Chu wrote:
> > > +
> > > +properties:
> > > +  compatible:
> > > +    enum:
> > > +      - spacemit,k1-ccu-apbs
> > > +      - spacemit,k1-ccu-mpmu
> > > +      - spacemit,k1-ccu-apbc
> > > +      - spacemit,k1-ccu-apmu
> > > +
> > > +  clocks:
> > > +    maxItems: 4
> > > +
> > > +  clock-names:
> > > +    items:
> > > +      - const: osc_32k
> > 
> > osc
> > 
> > > +      - const: vctcxo_1m
> > > +      - const: vctcxo_3m
> > > +      - const: vctcxo_24m
> > > +
> > > +  spacemit,mpmu:
> > > +    $ref: /schemas/types.yaml#/definitions/phandle
> > > +    description:
> > > +      Phandle to the syscon managing "Main PMU (MPMU)" registers. It is used to
> > > +      check PLL lock status.
> > 
> > Why your example does not have it? Example code is supposed to be complete.
> 
> I think I understand why - this is for only one variant?

Yes, currently all implemented PLLs are located at APBS region, thus
this property is only meaningful in spacemit,k1-ccu-apbs.

> But then this
> should be disallowed in your binding for others. Currently your binding
> says that it is required for one and allowed for others.

Thanks for the correction. I'm considering moving the definition of
spacemit,mpmu to the if block as well. Is it the correct way to disallow
its usage in other variants?

> 
> Best regards,
> Krzysztof

Thanks,
Haylen Chu

[PATCH v3 2/3] dt-bindings: soc: spacemit: Add spacemit,k1-syscon

[Haylen Chu]

Add documentation to describe Spacemit K1 system controller registers.

Signed-off-by: Haylen Chu <heylenay@4d2.org>
---
 .../soc/spacemit/spacemit,k1-syscon.yaml      | 86 +++++++++++++++++++
 1 file changed, 86 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml

diff --git a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml
new file mode 100644
index 000000000000..b9f20190a70a
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/spacemit/spacemit,k1-syscon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Spacemit K1 SoC System Controller
+
+maintainers:
+  - Haylen Chu <heylenay@4d2.org>
+
+description:
+  The Spacemit K1 SoC system controller provides access to shared register files
+  for related SoC modules, such as clock controller and reset controller.
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - spacemit,k1-apbc-syscon
+          - spacemit,k1-apbs-syscon
+          - spacemit,k1-apmu-syscon
+          - spacemit,k1-mpmu-syscon
+      - const: syscon
+      - const: simple-mfd
+
+  reg:
+    maxItems: 1
+
+  clock-controller:
+    $ref: /schemas/clock/spacemit,k1-ccu.yaml#
+    type: object
+
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 1
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+
+examples:
+  - |
+    osc_32k: clock-32k {
+        compatible = "fixed-clock";
+        clock-frequency = <32000>;
+        clock-output-names = "osc_32k";
+        #clock-cells = <0>;
+    };
+
+    vctcxo_1m: clock-1m {
+        compatible = "fixed-clock";
+        clock-frequency = <1000000>;
+        clock-output-names = "vctcxo_1m";
+        #clock-cells = <0>;
+    };
+
+    vctcxo_3m: clock-3m {
+        compatible = "fixed-clock";
+        clock-frequency = <3000000>;
+        clock-output-names = "vctcxo_3m";
+        #clock-cells = <0>;
+    };
+
+    vctcxo_24m: clock-24m {
+        compatible = "fixed-clock";
+        clock-frequency = <24000000>;
+        clock-output-names = "vctcxo_24m";
+        #clock-cells = <0>;
+    };
+
+    system-controller@d4050000 {
+        compatible = "spacemit,k1-mpmu-syscon", "syscon", "simple-mfd";
+        reg = <0xd4050000 0x209c>;
+
+        clock-controller {
+            compatible = "spacemit,k1-ccu-mpmu";
+            clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>;
+            clock-names = "osc_32k", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m";
+            #clock-cells = <1>;
+        };
+    };
-- 
2.47.0

Re: [PATCH v3 2/3] dt-bindings: soc: spacemit: Add spacemit,k1-syscon

[Krzysztof Kozlowski]

On 26/11/2024 15:31, Haylen Chu wrote:
> Add documentation to describe Spacemit K1 system controller registers.
> 
> Signed-off-by: Haylen Chu <heylenay@4d2.org>
> ---
>  .../soc/spacemit/spacemit,k1-syscon.yaml      | 86 +++++++++++++++++++
>  1 file changed, 86 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml
> 
> diff --git a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml
> new file mode 100644
> index 000000000000..b9f20190a70a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml
> @@ -0,0 +1,86 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/soc/spacemit/spacemit,k1-syscon.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Spacemit K1 SoC System Controller
> +
> +maintainers:
> +  - Haylen Chu <heylenay@4d2.org>
> +
> +description:
> +  The Spacemit K1 SoC system controller provides access to shared register files
> +  for related SoC modules, such as clock controller and reset controller.
> +
> +properties:
> +  compatible:
> +    items:
> +      - enum:
> +          - spacemit,k1-apbc-syscon
> +          - spacemit,k1-apbs-syscon
> +          - spacemit,k1-apmu-syscon
> +          - spacemit,k1-mpmu-syscon
> +      - const: syscon
> +      - const: simple-mfd
> +
> +  reg:
> +    maxItems: 1
> +
> +  clock-controller:
> +    $ref: /schemas/clock/spacemit,k1-ccu.yaml#
> +    type: object
> +
> +  "#address-cells":
> +    const: 1
> +
> +  "#size-cells":
> +    const: 1
Nothing improved. That's a no-go.

<form letter>
This is a friendly reminder during the review process.

It seems my or other reviewer's previous comments were not fully
addressed. Maybe the feedback got lost between the quotes, maybe you
just forgot to apply it. Please go back to the previous discussion and
either implement all requested changes or keep discussing them.

Thank you.
</form letter>

Best regards,
Krzysztof

Re: [PATCH v3 2/3] dt-bindings: soc: spacemit: Add spacemit,k1-syscon

[Krzysztof Kozlowski]

On 26/11/2024 15:31, Haylen Chu wrote:
> +examples:
> +  - |
> +    osc_32k: clock-32k {
> +        compatible = "fixed-clock";
> +        clock-frequency = <32000>;
> +        clock-output-names = "osc_32k";
> +        #clock-cells = <0>;
> +    };
> +
> +    vctcxo_1m: clock-1m {
> +        compatible = "fixed-clock";
> +        clock-frequency = <1000000>;
> +        clock-output-names = "vctcxo_1m";
> +        #clock-cells = <0>;
> +    };
> +
> +    vctcxo_3m: clock-3m {
> +        compatible = "fixed-clock";
> +        clock-frequency = <3000000>;
> +        clock-output-names = "vctcxo_3m";
> +        #clock-cells = <0>;
> +    };
> +
> +    vctcxo_24m: clock-24m {
> +        compatible = "fixed-clock";
> +        clock-frequency = <24000000>;
> +        clock-output-names = "vctcxo_24m";
> +        #clock-cells = <0>;
> +    };

Drop all above. Your changelog is poor - does not explain this at all.
Write changelogs which detail what you did and why.

Best regards,
Krzysztof

Re: [PATCH v3 2/3] dt-bindings: soc: spacemit: Add spacemit,k1-syscon

[Haylen Chu]

On Tue, Nov 26, 2024 at 03:50:30PM +0100, Krzysztof Kozlowski wrote:
> On 26/11/2024 15:31, Haylen Chu wrote:
> > +examples:
> > +  - |
> > +    osc_32k: clock-32k {
> > +        compatible = "fixed-clock";
> > +        clock-frequency = <32000>;
> > +        clock-output-names = "osc_32k";
> > +        #clock-cells = <0>;
> > +    };
> > +
> > +    vctcxo_1m: clock-1m {
> > +        compatible = "fixed-clock";
> > +        clock-frequency = <1000000>;
> > +        clock-output-names = "vctcxo_1m";
> > +        #clock-cells = <0>;
> > +    };
> > +
> > +    vctcxo_3m: clock-3m {
> > +        compatible = "fixed-clock";
> > +        clock-frequency = <3000000>;
> > +        clock-output-names = "vctcxo_3m";
> > +        #clock-cells = <0>;
> > +    };
> > +
> > +    vctcxo_24m: clock-24m {
> > +        compatible = "fixed-clock";
> > +        clock-frequency = <24000000>;
> > +        clock-output-names = "vctcxo_24m";
> > +        #clock-cells = <0>;
> > +    };
> 
> Drop all above. Your changelog is poor - does not explain this at all.
> Write changelogs which detail what you did and why.

Thanks, I forgot that missing phandle references are acceptable in
dt-binding examples. This and other required changes in v2 that I forgot
to apply will be adapted in v4.

> 
> Best regards,
> Krzysztof

Thanks,
Haylen Chu

[PATCH v3 3/3] clk: spacemit: Add clock support for Spacemit K1 SoC

[Haylen Chu]

The clock tree of K1 SoC contains three main types of clock hardware
(PLL/DDN/MIX) and is managed by several independent controllers in
different SoC parts (APBC, APBS and etc.), thus different compatible
strings are added to distinguish them.

Some controllers may share IO region with reset controller and other low
speed peripherals like watchdog, so all register operations are done
through regmap to avoid competition.

Signed-off-by: Haylen Chu <heylenay@4d2.org>
---
 drivers/clk/Kconfig               |    1 +
 drivers/clk/Makefile              |    1 +
 drivers/clk/spacemit/Kconfig      |   20 +
 drivers/clk/spacemit/Makefile     |    5 +
 drivers/clk/spacemit/ccu-k1.c     | 1747 +++++++++++++++++++++++++++++
 drivers/clk/spacemit/ccu_common.h |   62 +
 drivers/clk/spacemit/ccu_ddn.c    |  146 +++
 drivers/clk/spacemit/ccu_ddn.h    |   85 ++
 drivers/clk/spacemit/ccu_mix.c    |  296 +++++
 drivers/clk/spacemit/ccu_mix.h    |  336 ++++++
 drivers/clk/spacemit/ccu_pll.c    |  198 ++++
 drivers/clk/spacemit/ccu_pll.h    |   80 ++
 12 files changed, 2977 insertions(+)
 create mode 100644 drivers/clk/spacemit/Kconfig
 create mode 100644 drivers/clk/spacemit/Makefile
 create mode 100644 drivers/clk/spacemit/ccu-k1.c
 create mode 100644 drivers/clk/spacemit/ccu_common.h
 create mode 100644 drivers/clk/spacemit/ccu_ddn.c
 create mode 100644 drivers/clk/spacemit/ccu_ddn.h
 create mode 100644 drivers/clk/spacemit/ccu_mix.c
 create mode 100644 drivers/clk/spacemit/ccu_mix.h
 create mode 100644 drivers/clk/spacemit/ccu_pll.c
 create mode 100644 drivers/clk/spacemit/ccu_pll.h

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 299bc678ed1b..fa8b5e8f2926 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -498,6 +498,7 @@ source "drivers/clk/samsung/Kconfig"
 source "drivers/clk/sifive/Kconfig"
 source "drivers/clk/socfpga/Kconfig"
 source "drivers/clk/sophgo/Kconfig"
+source "drivers/clk/spacemit/Kconfig"
 source "drivers/clk/sprd/Kconfig"
 source "drivers/clk/starfive/Kconfig"
 source "drivers/clk/sunxi/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index fb8878a5d7d9..e82ece2d0095 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -129,6 +129,7 @@ obj-$(CONFIG_COMMON_CLK_SAMSUNG)	+= samsung/
 obj-$(CONFIG_CLK_SIFIVE)		+= sifive/
 obj-y					+= socfpga/
 obj-y					+= sophgo/
+obj-y					+= spacemit/
 obj-$(CONFIG_PLAT_SPEAR)		+= spear/
 obj-y					+= sprd/
 obj-$(CONFIG_ARCH_STI)			+= st/
diff --git a/drivers/clk/spacemit/Kconfig b/drivers/clk/spacemit/Kconfig
new file mode 100644
index 000000000000..76090cd85668
--- /dev/null
+++ b/drivers/clk/spacemit/Kconfig
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config SPACEMIT_CCU
+	tristate "Clock support for Spacemit SoCs"
+	default y
+	depends on ARCH_SPACEMIT || COMPILE_TEST
+	select MFD_SYSCON
+	help
+	  Say Y to enable clock controller unit support for Spacemit SoCs.
+
+if SPACEMIT_CCU
+
+config SPACEMIT_K1_CCU
+	tristate "Support for Spacemit K1 SoC"
+	default y
+	depends on ARCH_SPACEMIT || COMPILE_TEST
+	help
+	  Support for clock controller unit in Spacemit K1 SoC.
+
+endif
diff --git a/drivers/clk/spacemit/Makefile b/drivers/clk/spacemit/Makefile
new file mode 100644
index 000000000000..9d1d5f759eb1
--- /dev/null
+++ b/drivers/clk/spacemit/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_SPACEMIT_CCU)	+= ccu_pll.o ccu_mix.o ccu_ddn.o
+
+obj-$(CONFIG_SPACEMIT_K1_CCU)	+= ccu-k1.o
diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c
new file mode 100644
index 000000000000..0b003fba4a8b
--- /dev/null
+++ b/drivers/clk/spacemit/ccu-k1.c
@@ -0,0 +1,1747 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2024 SpacemiT Technology Co. Ltd
+ * Copyright (c) 2024 Haylen Chu <heylenay@outlook.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include "ccu_common.h"
+#include "ccu_pll.h"
+#include "ccu_mix.h"
+#include "ccu_ddn.h"
+
+#include <dt-bindings/clock/spacemit,k1-ccu.h>
+
+/*	APBS register offset	*/
+/*	pll1	*/
+#define APB_SPARE1_REG			0x100
+#define APB_SPARE2_REG			0x104
+#define APB_SPARE3_REG			0x108
+/*	pll2	*/
+#define APB_SPARE7_REG			0x118
+#define APB_SPARE8_REG			0x11c
+#define APB_SPARE9_REG			0x120
+/*	pll3	*/
+#define APB_SPARE10_REG			0x124
+#define APB_SPARE11_REG			0x128
+#define APB_SPARE12_REG			0x12c
+
+/* MPMU register offset */
+#define MPMU_POSR			0x10
+#define POSR_PLL1_LOCK			BIT(27)
+#define POSR_PLL2_LOCK			BIT(28)
+#define POSR_PLL3_LOCK			BIT(29)
+
+#define MPMU_WDTPCR			0x200
+#define MPMU_RIPCCR			0x210
+#define MPMU_ACGR			0x1024
+#define MPMU_SUCCR			0x14
+#define MPMU_ISCCR			0x44
+#define MPMU_SUCCR_1			0x10b0
+#define MPMU_APBCSCR			0x1050
+
+/* APBC register offset */
+#define APBC_UART1_CLK_RST		0x0
+#define APBC_UART2_CLK_RST		0x4
+#define APBC_GPIO_CLK_RST		0x8
+#define APBC_PWM0_CLK_RST		0xc
+#define APBC_PWM1_CLK_RST		0x10
+#define APBC_PWM2_CLK_RST		0x14
+#define APBC_PWM3_CLK_RST		0x18
+#define APBC_TWSI8_CLK_RST		0x20
+#define APBC_UART3_CLK_RST		0x24
+#define APBC_RTC_CLK_RST		0x28
+#define APBC_TWSI0_CLK_RST		0x2c
+#define APBC_TWSI1_CLK_RST		0x30
+#define APBC_TIMERS1_CLK_RST		0x34
+#define APBC_TWSI2_CLK_RST		0x38
+#define APBC_AIB_CLK_RST		0x3c
+#define APBC_TWSI4_CLK_RST		0x40
+#define APBC_TIMERS2_CLK_RST		0x44
+#define APBC_ONEWIRE_CLK_RST		0x48
+#define APBC_TWSI5_CLK_RST		0x4c
+#define APBC_DRO_CLK_RST		0x58
+#define APBC_IR_CLK_RST			0x5c
+#define APBC_TWSI6_CLK_RST		0x60
+#define APBC_COUNTER_CLK_SEL		0x64
+#define APBC_TWSI7_CLK_RST		0x68
+#define APBC_TSEN_CLK_RST		0x6c
+#define APBC_UART4_CLK_RST		0x70
+#define APBC_UART5_CLK_RST		0x74
+#define APBC_UART6_CLK_RST		0x78
+#define APBC_SSP3_CLK_RST		0x7c
+#define APBC_SSPA0_CLK_RST		0x80
+#define APBC_SSPA1_CLK_RST		0x84
+#define APBC_IPC_AP2AUD_CLK_RST		0x90
+#define APBC_UART7_CLK_RST		0x94
+#define APBC_UART8_CLK_RST		0x98
+#define APBC_UART9_CLK_RST		0x9c
+#define APBC_CAN0_CLK_RST		0xa0
+#define APBC_PWM4_CLK_RST		0xa8
+#define APBC_PWM5_CLK_RST		0xac
+#define APBC_PWM6_CLK_RST		0xb0
+#define APBC_PWM7_CLK_RST		0xb4
+#define APBC_PWM8_CLK_RST		0xb8
+#define APBC_PWM9_CLK_RST		0xbc
+#define APBC_PWM10_CLK_RST		0xc0
+#define APBC_PWM11_CLK_RST		0xc4
+#define APBC_PWM12_CLK_RST		0xc8
+#define APBC_PWM13_CLK_RST		0xcc
+#define APBC_PWM14_CLK_RST		0xd0
+#define APBC_PWM15_CLK_RST		0xd4
+#define APBC_PWM16_CLK_RST		0xd8
+#define APBC_PWM17_CLK_RST		0xdc
+#define APBC_PWM18_CLK_RST		0xe0
+#define APBC_PWM19_CLK_RST		0xe4
+
+/* APMU register offset */
+#define APMU_CCI550_CLK_CTRL		0x300
+#define APMU_CPU_C0_CLK_CTRL		0x38C
+#define APMU_CPU_C1_CLK_CTRL		0x390
+#define APMU_JPG_CLK_RES_CTRL		0x20
+#define APMU_CSI_CCIC2_CLK_RES_CTRL	0x24
+#define APMU_ISP_CLK_RES_CTRL		0x38
+#define APMU_LCD_CLK_RES_CTRL1		0x44
+#define APMU_LCD_SPI_CLK_RES_CTRL	0x48
+#define APMU_LCD_CLK_RES_CTRL2		0x4c
+#define APMU_CCIC_CLK_RES_CTRL		0x50
+#define APMU_SDH0_CLK_RES_CTRL		0x54
+#define APMU_SDH1_CLK_RES_CTRL		0x58
+#define APMU_USB_CLK_RES_CTRL		0x5c
+#define APMU_QSPI_CLK_RES_CTRL		0x60
+#define APMU_USB_CLK_RES_CTRL		0x5c
+#define APMU_DMA_CLK_RES_CTRL		0x64
+#define APMU_AES_CLK_RES_CTRL		0x68
+#define APMU_VPU_CLK_RES_CTRL		0xa4
+#define APMU_GPU_CLK_RES_CTRL		0xcc
+#define APMU_SDH2_CLK_RES_CTRL		0xe0
+#define APMU_PMUA_MC_CTRL		0xe8
+#define APMU_PMU_CC2_AP			0x100
+#define APMU_PMUA_EM_CLK_RES_CTRL	0x104
+#define APMU_AUDIO_CLK_RES_CTRL		0x14c
+#define APMU_HDMI_CLK_RES_CTRL		0x1B8
+#define APMU_CCI550_CLK_CTRL		0x300
+#define APMU_ACLK_CLK_CTRL		0x388
+#define APMU_CPU_C0_CLK_CTRL		0x38C
+#define APMU_CPU_C1_CLK_CTRL		0x390
+#define APMU_PCIE_CLK_RES_CTRL_0	0x3cc
+#define APMU_PCIE_CLK_RES_CTRL_1	0x3d4
+#define APMU_PCIE_CLK_RES_CTRL_2	0x3dc
+#define APMU_EMAC0_CLK_RES_CTRL		0x3e4
+#define APMU_EMAC1_CLK_RES_CTRL		0x3ec
+
+/*	APBS clocks start	*/
+
+/* Frequency of pll{1,2} should not be updated at runtime */
+static const struct ccu_pll_rate_tbl pll1_rate_tbl[] = {
+	CCU_PLL_RATE(2457600000UL, 0x64, 0xdd, 0x50, 0x00, 0x33, 0x0ccccd),
+};
+
+static const struct ccu_pll_rate_tbl pll2_rate_tbl[] = {
+	CCU_PLL_RATE(3000000000UL, 0x66, 0xdd, 0x50, 0x00, 0x3f, 0xe00000),
+};
+
+static const struct ccu_pll_rate_tbl pll3_rate_tbl[] = {
+	CCU_PLL_RATE(3000000000UL, 0x66, 0xdd, 0x50, 0x00, 0x3f, 0xe00000),
+	CCU_PLL_RATE(3200000000UL, 0x67, 0xdd, 0x50, 0x00, 0x43, 0xeaaaab),
+	CCU_PLL_RATE(2457600000UL, 0x64, 0xdd, 0x50, 0x00, 0x33, 0x0ccccd),
+};
+
+static CCU_PLL_DEFINE(pll1, "pll1", pll1_rate_tbl,
+		      APB_SPARE1_REG, APB_SPARE2_REG, APB_SPARE3_REG,
+		      MPMU_POSR, POSR_PLL1_LOCK, 0);
+static CCU_PLL_DEFINE(pll2, "pll2", pll2_rate_tbl,
+		      APB_SPARE7_REG, APB_SPARE8_REG, APB_SPARE9_REG,
+		      MPMU_POSR, POSR_PLL2_LOCK, 0);
+static CCU_PLL_DEFINE(pll3, "pll3", pll3_rate_tbl,
+		      APB_SPARE10_REG, APB_SPARE11_REG, APB_SPARE12_REG,
+		      MPMU_POSR, POSR_PLL3_LOCK, 0);
+
+static CCU_GATE_FACTOR_DEFINE(pll1_d2, "pll1_d2", CCU_PARENT_HW(pll1),
+			      APB_SPARE2_REG,
+			      BIT(1), BIT(1), 0, 2, 1, 0);
+static CCU_GATE_FACTOR_DEFINE(pll1_d3, "pll1_d3", CCU_PARENT_HW(pll1),
+			      APB_SPARE2_REG,
+			      BIT(2), BIT(2), 0, 3, 1, 0);
+static CCU_GATE_FACTOR_DEFINE(pll1_d4, "pll1_d4", CCU_PARENT_HW(pll1),
+			      APB_SPARE2_REG,
+			      BIT(3), BIT(3), 0, 4, 1, 0);
+static CCU_GATE_FACTOR_DEFINE(pll1_d5, "pll1_d5", CCU_PARENT_HW(pll1),
+			      APB_SPARE2_REG,
+			      BIT(4), BIT(4), 0, 5, 1, 0);
+static CCU_GATE_FACTOR_DEFINE(pll1_d6, "pll1_d6", CCU_PARENT_HW(pll1),
+			      APB_SPARE2_REG,
+			      BIT(5), BIT(5), 0, 6, 1, 0);
+static CCU_GATE_FACTOR_DEFINE(pll1_d7, "pll1_d7", CCU_PARENT_HW(pll1),
+			      APB_SPARE2_REG,
+			      BIT(6), BIT(6), 0, 7, 1, 0);
+static CCU_GATE_FACTOR_DEFINE(pll1_d8, "pll1_d8", CCU_PARENT_HW(pll1),
+			      APB_SPARE2_REG,
+			      BIT(7), BIT(7), 0, 8, 1, 0);
+static CCU_GATE_FACTOR_DEFINE(pll1_d11_223p4, "pll1_d11_223p4", CCU_PARENT_HW(pll1),
+			      APB_SPARE2_REG,
+			      BIT(15), BIT(15), 0, 11, 1, 0);
+static CCU_GATE_FACTOR_DEFINE(pll1_d13_189, "pll1_d13_189", CCU_PARENT_HW(pll1),
+			      APB_SPARE2_REG,
+			      BIT(16), BIT(16), 0, 13, 1, 0);
+static CCU_GATE_FACTOR_DEFINE(pll1_d23_106p8, "pll1_d23_106p8", CCU_PARENT_HW(pll1),
+			      APB_SPARE2_REG,
+			      BIT(20), BIT(20), 0, 23, 1, 0);
+static CCU_GATE_FACTOR_DEFINE(pll1_d64_38p4, "pll1_d64_38p4", CCU_PARENT_HW(pll1),
+			      APB_SPARE2_REG,
+			      BIT(0), BIT(0), 0, 64, 1, 0);
+static CCU_GATE_FACTOR_DEFINE(pll1_aud_245p7, "pll1_aud_245p7", CCU_PARENT_HW(pll1),
+			      APB_SPARE2_REG,
+			      BIT(10), BIT(10), 0, 10, 1, 0);
+static CCU_GATE_FACTOR_DEFINE(pll1_aud_24p5, "pll1_aud_24p5", CCU_PARENT_HW(pll1),
+			      APB_SPARE2_REG,
+			      BIT(11), BIT(11), 0, 100, 1, 0);
+
+static CCU_GATE_FACTOR_DEFINE(pll2_d1, "pll2_d1", CCU_PARENT_HW(pll2),
+			      APB_SPARE8_REG,
+			      BIT(0), BIT(0), 0, 1, 1, 0);
+static CCU_GATE_FACTOR_DEFINE(pll2_d2, "pll2_d2", CCU_PARENT_HW(pll2),
+			      APB_SPARE8_REG,
+			      BIT(1), BIT(1), 0, 2, 1, 0);
+static CCU_GATE_FACTOR_DEFINE(pll2_d3, "pll2_d3", CCU_PARENT_HW(pll2),
+			      APB_SPARE8_REG,
+			      BIT(2), BIT(2), 0, 3, 1, 0);
+static CCU_GATE_FACTOR_DEFINE(pll2_d4, "pll2_d4", CCU_PARENT_HW(pll2),
+			      APB_SPARE8_REG,
+			      BIT(3), BIT(3), 0, 4, 1, 0);
+static CCU_GATE_FACTOR_DEFINE(pll2_d5, "pll2_d5", CCU_PARENT_HW(pll2),
+			      APB_SPARE8_REG,
+			      BIT(4), BIT(4), 0, 5, 1, 0);
+static CCU_GATE_FACTOR_DEFINE(pll2_d6, "pll2_d6", CCU_PARENT_HW(pll2),
+			      APB_SPARE8_REG,
+			      BIT(5), BIT(5), 0, 6, 1, 0);
+static CCU_GATE_FACTOR_DEFINE(pll2_d7, "pll2_d7", CCU_PARENT_HW(pll2),
+			      APB_SPARE8_REG,
+			      BIT(6), BIT(6), 0, 7, 1, 0);
+static CCU_GATE_FACTOR_DEFINE(pll2_d8, "pll2_d8", CCU_PARENT_HW(pll2),
+			      APB_SPARE8_REG,
+			      BIT(7), BIT(7), 0, 8, 1, 0);
+
+static CCU_GATE_FACTOR_DEFINE(pll3_d1, "pll3_d1", CCU_PARENT_HW(pll3),
+			      APB_SPARE11_REG,
+			      BIT(0), BIT(0), 0, 1, 1, 0);
+static CCU_GATE_FACTOR_DEFINE(pll3_d2, "pll3_d2", CCU_PARENT_HW(pll3),
+			      APB_SPARE11_REG,
+			      BIT(1), BIT(1), 0, 2, 1, 0);
+static CCU_GATE_FACTOR_DEFINE(pll3_d3, "pll3_d3", CCU_PARENT_HW(pll3),
+			      APB_SPARE11_REG,
+			      BIT(2), BIT(2), 0, 3, 1, 0);
+static CCU_GATE_FACTOR_DEFINE(pll3_d4, "pll3_d4", CCU_PARENT_HW(pll3),
+			      APB_SPARE11_REG,
+			      BIT(3), BIT(3), 0, 4, 1, 0);
+static CCU_GATE_FACTOR_DEFINE(pll3_d5, "pll3_d5", CCU_PARENT_HW(pll3),
+			      APB_SPARE11_REG,
+			      BIT(4), BIT(4), 0, 5, 1, 0);
+static CCU_GATE_FACTOR_DEFINE(pll3_d6, "pll3_d6", CCU_PARENT_HW(pll3),
+			      APB_SPARE11_REG,
+			      BIT(5), BIT(5), 0, 6, 1, 0);
+static CCU_GATE_FACTOR_DEFINE(pll3_d7, "pll3_d7", CCU_PARENT_HW(pll3),
+			      APB_SPARE11_REG,
+			      BIT(6), BIT(6), 0, 7, 1, 0);
+static CCU_GATE_FACTOR_DEFINE(pll3_d8, "pll3_d8", CCU_PARENT_HW(pll3),
+			      APB_SPARE11_REG,
+			      BIT(7), BIT(7), 0, 8, 1, 0);
+
+static CCU_FACTOR_DEFINE(pll3_20, "pll3_20", CCU_PARENT_HW(pll3_d8), 20, 1);
+static CCU_FACTOR_DEFINE(pll3_40, "pll3_40", CCU_PARENT_HW(pll3_d8), 10, 1);
+static CCU_FACTOR_DEFINE(pll3_80, "pll3_80", CCU_PARENT_HW(pll3_d8), 5, 1);
+
+/*	APBS clocks end		*/
+
+/*	MPMU clocks start	*/
+static CCU_GATE_DEFINE(pll1_d8_307p2, "pll1_d8_307p2", CCU_PARENT_HW(pll1_d8),
+		       MPMU_ACGR,
+		       BIT(13), BIT(13), 0, 0);
+static CCU_FACTOR_DEFINE(pll1_d32_76p8, "pll1_d32_76p8", CCU_PARENT_HW(pll1_d8_307p2),
+			 4, 1);
+static CCU_FACTOR_DEFINE(pll1_d40_61p44, "pll1_d40_61p44", CCU_PARENT_HW(pll1_d8_307p2),
+			 5, 1);
+static CCU_FACTOR_DEFINE(pll1_d16_153p6, "pll1_d16_153p6", CCU_PARENT_HW(pll1_d8),
+			 2, 1);
+static CCU_GATE_FACTOR_DEFINE(pll1_d24_102p4, "pll1_d24_102p4", CCU_PARENT_HW(pll1_d8),
+			      MPMU_ACGR,
+			      BIT(12), BIT(12), 0, 3, 1, 0);
+static CCU_GATE_FACTOR_DEFINE(pll1_d48_51p2, "pll1_d48_51p2", CCU_PARENT_HW(pll1_d8),
+			      MPMU_ACGR,
+			      BIT(7), BIT(7), 0, 6, 1, 0);
+static CCU_GATE_FACTOR_DEFINE(pll1_d48_51p2_ap, "pll1_d48_51p2_ap", CCU_PARENT_HW(pll1_d8),
+			      MPMU_ACGR,
+			      BIT(11), BIT(11), 0, 6, 1, 0);
+static CCU_GATE_FACTOR_DEFINE(pll1_m3d128_57p6, "pll1_m3d128_57p6", CCU_PARENT_HW(pll1_d8),
+			      MPMU_ACGR,
+			      BIT(8), BIT(8), 0, 16, 3, 0);
+static CCU_GATE_FACTOR_DEFINE(pll1_d96_25p6, "pll1_d96_25p6", CCU_PARENT_HW(pll1_d8),
+			      MPMU_ACGR,
+			      BIT(4), BIT(4), 0, 12, 1, 0);
+static CCU_GATE_FACTOR_DEFINE(pll1_d192_12p8, "pll1_d192_12p8", CCU_PARENT_HW(pll1_d8),
+			      MPMU_ACGR,
+			      BIT(3), BIT(3), 0, 24, 1, 0);
+static CCU_GATE_FACTOR_DEFINE(pll1_d192_12p8_wdt, "pll1_d192_12p8_wdt", CCU_PARENT_HW(pll1_d8),
+			      MPMU_ACGR,
+			      BIT(19), BIT(19), 0x0, 24, 1, 0);
+static CCU_GATE_FACTOR_DEFINE(pll1_d384_6p4, "pll1_d384_6p4", CCU_PARENT_HW(pll1_d8),
+			      MPMU_ACGR,
+			      BIT(2), BIT(2), 0, 48, 1, 0);
+static CCU_FACTOR_DEFINE(pll1_d768_3p2, "pll1_d768_3p2", CCU_PARENT_HW(pll1_d384_6p4),
+			 2, 1);
+static CCU_FACTOR_DEFINE(pll1_d1536_1p6, "pll1_d1536_1p6", CCU_PARENT_HW(pll1_d384_6p4),
+			 4, 1);
+static CCU_FACTOR_DEFINE(pll1_d3072_0p8, "pll1_d3072_0p8", CCU_PARENT_HW(pll1_d384_6p4),
+			 8, 1);
+
+static CCU_FACTOR_DEFINE(pll1_d7_351p08, "pll1_d7_351p08", CCU_PARENT_HW(pll1_d7),
+			 1, 1);
+
+static CCU_GATE_DEFINE(pll1_d6_409p6, "pll1_d6_409p6", CCU_PARENT_HW(pll1_d6),
+		       MPMU_ACGR,
+		       BIT(0), BIT(0), 0, 0);
+static CCU_GATE_FACTOR_DEFINE(pll1_d12_204p8, "pll1_d12_204p8", CCU_PARENT_HW(pll1_d6),
+			      MPMU_ACGR,
+			      BIT(5), BIT(5), 0, 2, 1, 0);
+
+static CCU_GATE_DEFINE(pll1_d5_491p52, "pll1_d5_491p52", CCU_PARENT_HW(pll1_d5),
+		       MPMU_ACGR,
+		       BIT(21), BIT(21), 0, 0);
+static CCU_GATE_FACTOR_DEFINE(pll1_d10_245p76, "pll1_d10_245p76", CCU_PARENT_HW(pll1_d5),
+			      MPMU_ACGR,
+			      BIT(18), BIT(18), 0, 2, 1, 0);
+
+static CCU_GATE_DEFINE(pll1_d4_614p4, "pll1_d4_614p4", CCU_PARENT_HW(pll1_d4),
+		       MPMU_ACGR,
+		       BIT(15), BIT(15), 0, 0);
+static CCU_GATE_FACTOR_DEFINE(pll1_d52_47p26, "pll1_d52_47p26", CCU_PARENT_HW(pll1_d4),
+			      MPMU_ACGR,
+			      BIT(10), BIT(10), 0, 13, 1, 0);
+static CCU_GATE_FACTOR_DEFINE(pll1_d78_31p5, "pll1_d78_31p5", CCU_PARENT_HW(pll1_d4),
+			      MPMU_ACGR,
+			      BIT(6), BIT(6), 0, 39, 2, 0);
+
+static CCU_GATE_DEFINE(pll1_d3_819p2, "pll1_d3_819p2", CCU_PARENT_HW(pll1_d3),
+		       MPMU_ACGR,
+		       BIT(14), BIT(14), 0, 0);
+
+static CCU_GATE_DEFINE(pll1_d2_1228p8, "pll1_d2_1228p8", CCU_PARENT_HW(pll1_d2),
+		       MPMU_ACGR,
+		       BIT(16), BIT(16), 0, 0);
+
+static struct ccu_ddn_info uart_ddn_mask_info = {
+	.factor		= 2,
+	.num_mask	= 0x1fff,
+	.den_mask	= 0x1fff,
+	.num_shift	= 16,
+	.den_shift	= 0,
+};
+static struct ccu_ddn_tbl slow_uart1_tbl[] = {
+	{ .num = 125, .den = 24 },
+};
+static struct ccu_ddn_tbl slow_uart2_tbl[] = {
+	{ .num = 6144, .den = 960 },
+};
+static CCU_GATE_DEFINE(slow_uart, "slow_uart", CCU_PARENT_NAME(osc_32k),
+		       MPMU_ACGR,
+		       BIT(1), BIT(1), 0, CLK_IGNORE_UNUSED);
+static CCU_DDN_DEFINE(slow_uart1_14p74, "slow_uart1_14p74", pll1_d16_153p6,
+		      &uart_ddn_mask_info, slow_uart1_tbl,
+		      MPMU_SUCCR, 0);
+static CCU_DDN_DEFINE(slow_uart2_48, "slow_uart2_48", pll1_d4_614p4,
+		      &uart_ddn_mask_info, slow_uart2_tbl,
+		      MPMU_SUCCR_1, 0);
+
+static CCU_GATE_DEFINE(wdt_clk, "wdt_clk", CCU_PARENT_HW(pll1_d96_25p6),
+		       MPMU_WDTPCR,
+		       BIT(1), BIT(1), 0x0,
+		       0);
+
+static CCU_GATE_DEFINE(ripc_clk, "ripc_clk", CCU_PARENT_NAME(vctcxo_24m),
+		       MPMU_RIPCCR,
+		       0x3, 0x3, 0x0,
+		       0);
+
+static CCU_GATE_FACTOR_DEFINE(i2s_sysclk, "i2s_sysclk", CCU_PARENT_HW(pll1_d16_153p6),
+			      MPMU_ISCCR,
+			      BIT(31), BIT(31), 0x0, 50, 1,
+			      0);
+static CCU_GATE_FACTOR_DEFINE(i2s_bclk, "i2s_bclk", CCU_PARENT_HW(i2s_sysclk),
+			      MPMU_ISCCR,
+			      BIT(29), BIT(29), 0x0, 1, 1,
+			      0);
+
+static const struct clk_parent_data apb_parents[] = {
+	CCU_PARENT_HW(pll1_d96_25p6),
+	CCU_PARENT_HW(pll1_d48_51p2),
+	CCU_PARENT_HW(pll1_d96_25p6),
+	CCU_PARENT_HW(pll1_d24_102p4),
+};
+static CCU_MUX_DEFINE(apb_clk, "apb_clk", apb_parents,
+		      MPMU_APBCSCR,
+		      0, 2,
+		      0);
+
+static CCU_GATE_DEFINE(wdt_bus_clk, "wdt_bus_clk", CCU_PARENT_HW(apb_clk),
+		       MPMU_WDTPCR,
+		       BIT(2), BIT(2), 0x0,
+		       0);
+/*	MPMU clocks end		*/
+
+/*	APBC clocks start	*/
+static const struct clk_parent_data uart_clk_parents[] = {
+	CCU_PARENT_HW(pll1_m3d128_57p6),
+	CCU_PARENT_HW(slow_uart1_14p74),
+	CCU_PARENT_HW(slow_uart2_48),
+};
+static CCU_MUX_GATE_DEFINE(uart0_clk, "uart0_clk", uart_clk_parents,
+			   APBC_UART1_CLK_RST,
+			   4, 3, BIT(1), BIT(1), 0x0,
+			   CLK_IS_CRITICAL);
+static CCU_MUX_GATE_DEFINE(uart2_clk, "uart2_clk", uart_clk_parents,
+			   APBC_UART2_CLK_RST,
+			   4, 3, BIT(1), BIT(1), 0x0,
+			   0);
+static CCU_MUX_GATE_DEFINE(uart3_clk, "uart3_clk", uart_clk_parents,
+			   APBC_UART3_CLK_RST,
+			   4, 3, BIT(1), BIT(1), 0x0,
+			   0);
+static CCU_MUX_GATE_DEFINE(uart4_clk, "uart4_clk", uart_clk_parents,
+			   APBC_UART4_CLK_RST,
+			   4, 3, BIT(1), BIT(1), 0x0,
+			   0);
+static CCU_MUX_GATE_DEFINE(uart5_clk, "uart5_clk", uart_clk_parents,
+			   APBC_UART5_CLK_RST,
+			   4, 3, BIT(1), BIT(1), 0x0,
+			   0);
+static CCU_MUX_GATE_DEFINE(uart6_clk, "uart6_clk", uart_clk_parents,
+			   APBC_UART6_CLK_RST,
+			   4, 3, BIT(1), BIT(1), 0x0,
+			   0);
+static CCU_MUX_GATE_DEFINE(uart7_clk, "uart7_clk", uart_clk_parents,
+			   APBC_UART7_CLK_RST,
+			   4, 3, BIT(1), BIT(1), 0x0,
+			   0);
+static CCU_MUX_GATE_DEFINE(uart8_clk, "uart8_clk", uart_clk_parents,
+			   APBC_UART8_CLK_RST,
+			   4, 3, BIT(1), BIT(1), 0x0,
+			   0);
+static CCU_MUX_GATE_DEFINE(uart9_clk, "uart9_clk", uart_clk_parents,
+			   APBC_UART9_CLK_RST,
+			   4, 3, BIT(1), BIT(1), 0x0,
+			   0);
+
+static CCU_GATE_DEFINE(gpio_clk, "gpio_clk", CCU_PARENT_NAME(vctcxo_24m),
+		       APBC_GPIO_CLK_RST,
+		       BIT(1), BIT(1), 0x0,
+		       0);
+
+static const struct clk_parent_data pwm_parents[] = {
+	CCU_PARENT_HW(pll1_d192_12p8),
+	CCU_PARENT_NAME(osc_32k),
+};
+static CCU_MUX_GATE_DEFINE(pwm0_clk, "pwm0_clk", pwm_parents,
+			   APBC_PWM0_CLK_RST,
+			   4, 3, BIT(1), BIT(1), 0x0,
+			   0);
+static CCU_MUX_GATE_DEFINE(pwm1_clk, "pwm1_clk", pwm_parents,
+			   APBC_PWM1_CLK_RST,
+			   4, 3, BIT(1), BIT(1), 0x0,
+			   0);
+static CCU_MUX_GATE_DEFINE(pwm2_clk, "pwm2_clk", pwm_parents,
+			   APBC_PWM2_CLK_RST,
+			   4, 3, BIT(1), BIT(1), 0x0,
+			   0);
+static CCU_MUX_GATE_DEFINE(pwm3_clk, "pwm3_clk", pwm_parents,
+			   APBC_PWM3_CLK_RST,
+			   4, 3, BIT(1), BIT(1), 0x0,
+			   0);
+static CCU_MUX_GATE_DEFINE(pwm4_clk, "pwm4_clk", pwm_parents,
+			   APBC_PWM4_CLK_RST,
+			   4, 3, BIT(1), BIT(1), 0x0,
+			   0);
+static CCU_MUX_GATE_DEFINE(pwm5_clk, "pwm5_clk", pwm_parents,
+			   APBC_PWM5_CLK_RST,
+			   4, 3, BIT(1), BIT(1), 0x0,
+			   0);
+static CCU_MUX_GATE_DEFINE(pwm6_clk, "pwm6_clk", pwm_parents,
+			   APBC_PWM6_CLK_RST,
+			   4, 3, BIT(1), BIT(1), 0x0,
+			   0);
+static CCU_MUX_GATE_DEFINE(pwm7_clk, "pwm7_clk", pwm_parents,
+			   APBC_PWM7_CLK_RST,
+			   4, 3, BIT(1), BIT(1), 0x0,
+			   0);
+static CCU_MUX_GATE_DEFINE(pwm8_clk, "pwm8_clk", pwm_parents,
+			   APBC_PWM8_CLK_RST,
+			   4, 3, BIT(1), BIT(1), 0x0,
+			   0);
+static CCU_MUX_GATE_DEFINE(pwm9_clk, "pwm9_clk", pwm_parents,
+			   APBC_PWM9_CLK_RST,
+			   4, 3, BIT(1), BIT(1), 0x0,
+			   0);
+static CCU_MUX_GATE_DEFINE(pwm10_clk, "pwm10_clk", pwm_parents,
+			   APBC_PWM10_CLK_RST,
+			   4, 3, BIT(1), BIT(1), 0x0,
+			   0);
+static CCU_MUX_GATE_DEFINE(pwm11_clk, "pwm11_clk", pwm_parents,
+			   APBC_PWM11_CLK_RST,
+			   4, 3, BIT(1), BIT(1), 0x0,
+			   0);
+static CCU_MUX_GATE_DEFINE(pwm12_clk, "pwm12_clk", pwm_parents,
+			   APBC_PWM12_CLK_RST,
+			   4, 3, BIT(1), BIT(1), 0x0,
+			   0);
+static CCU_MUX_GATE_DEFINE(pwm13_clk, "pwm13_clk", pwm_parents,
+			   APBC_PWM13_CLK_RST,
+			   4, 3, BIT(1), BIT(1), 0x0,
+			   0);
+static CCU_MUX_GATE_DEFINE(pwm14_clk, "pwm14_clk", pwm_parents,
+			   APBC_PWM14_CLK_RST,
+			   4, 3, BIT(1), BIT(1), 0x0,
+			   0);
+static CCU_MUX_GATE_DEFINE(pwm15_clk, "pwm15_clk", pwm_parents,
+			   APBC_PWM15_CLK_RST,
+			   4, 3, BIT(1), BIT(1), 0x0,
+			   0);
+static CCU_MUX_GATE_DEFINE(pwm16_clk, "pwm16_clk", pwm_parents,
+			   APBC_PWM16_CLK_RST,
+			   4, 3, BIT(1), BIT(1), 0x0,
+			   0);
+static CCU_MUX_GATE_DEFINE(pwm17_clk, "pwm17_clk", pwm_parents,
+			   APBC_PWM17_CLK_RST,
+			   4, 3, BIT(1), BIT(1), 0x0,
+			   0);
+static CCU_MUX_GATE_DEFINE(pwm18_clk, "pwm18_clk", pwm_parents,
+			   APBC_PWM18_CLK_RST,
+			   4, 3, BIT(1), BIT(1), 0x0,
+			   0);
+static CCU_MUX_GATE_DEFINE(pwm19_clk, "pwm19_clk", pwm_parents,
+			   APBC_PWM19_CLK_RST,
+			   4, 3, BIT(1), BIT(1), 0x0,
+			   0);
+
+static const struct clk_parent_data ssp_parents[] = {
+	CCU_PARENT_HW(pll1_d384_6p4),
+	CCU_PARENT_HW(pll1_d192_12p8),
+	CCU_PARENT_HW(pll1_d96_25p6),
+	CCU_PARENT_HW(pll1_d48_51p2),
+	CCU_PARENT_HW(pll1_d768_3p2),
+	CCU_PARENT_HW(pll1_d1536_1p6),
+	CCU_PARENT_HW(pll1_d3072_0p8),
+};
+static CCU_MUX_GATE_DEFINE(ssp3_clk, "ssp3_clk", ssp_parents,
+			   APBC_SSP3_CLK_RST,
+			   4, 3, BIT(1), BIT(1), 0x0,
+			   0);
+
+static CCU_GATE_DEFINE(rtc_clk, "rtc_clk", CCU_PARENT_NAME(osc_32k),
+		       APBC_RTC_CLK_RST,
+		       0x82, 0x82, 0x0,
+		       0);
+
+static const struct clk_parent_data twsi_parents[] = {
+	CCU_PARENT_HW(pll1_d78_31p5),
+	CCU_PARENT_HW(pll1_d48_51p2),
+	CCU_PARENT_HW(pll1_d40_61p44),
+};
+static CCU_MUX_GATE_DEFINE(twsi0_clk, "twsi0_clk", twsi_parents,
+			   APBC_TWSI0_CLK_RST,
+			   4, 3, BIT(1), BIT(1), 0x0,
+			   0);
+static CCU_MUX_GATE_DEFINE(twsi1_clk, "twsi1_clk", twsi_parents,
+			   APBC_TWSI1_CLK_RST,
+			   4, 3, BIT(1), BIT(1), 0x0,
+			   0);
+static CCU_MUX_GATE_DEFINE(twsi2_clk, "twsi2_clk", twsi_parents,
+			   APBC_TWSI2_CLK_RST,
+			   4, 3, BIT(1), BIT(1), 0x0,
+			   0);
+static CCU_MUX_GATE_DEFINE(twsi4_clk, "twsi4_clk", twsi_parents,
+			   APBC_TWSI4_CLK_RST,
+			   4, 3, BIT(1), BIT(1), 0x0,
+			   0);
+static CCU_MUX_GATE_DEFINE(twsi5_clk, "twsi5_clk", twsi_parents,
+			   APBC_TWSI5_CLK_RST,
+			   4, 3, BIT(1), BIT(1), 0x0,
+			   0);
+static CCU_MUX_GATE_DEFINE(twsi6_clk, "twsi6_clk", twsi_parents,
+			   APBC_TWSI6_CLK_RST,
+			   4, 3, BIT(1), BIT(1), 0x0,
+			   0);
+static CCU_MUX_GATE_DEFINE(twsi7_clk, "twsi7_clk", twsi_parents,
+			   APBC_TWSI7_CLK_RST,
+			   4, 3, BIT(1), BIT(1), 0x0,
+			   0);
+static CCU_MUX_GATE_DEFINE(twsi8_clk, "twsi8_clk", twsi_parents,
+			   APBC_TWSI8_CLK_RST,
+			   4, 3, BIT(1), BIT(1), 0x0,
+			   0);
+
+static const struct clk_parent_data timer_parents[] = {
+	CCU_PARENT_HW(pll1_d192_12p8),
+	CCU_PARENT_NAME(osc_32k),
+	CCU_PARENT_HW(pll1_d384_6p4),
+	CCU_PARENT_NAME(vctcxo_3m),
+	CCU_PARENT_NAME(vctcxo_1m),
+};
+static CCU_MUX_GATE_DEFINE(timers1_clk, "timers1_clk", timer_parents,
+			   APBC_TIMERS1_CLK_RST,
+			   4, 3, 0x3, 0x3, 0x0,
+			   0);
+static CCU_MUX_GATE_DEFINE(timers2_clk, "timers2_clk", timer_parents,
+			   APBC_TIMERS2_CLK_RST,
+			   4, 3, 0x3, 0x3, 0x0,
+			   0);
+
+static CCU_GATE_DEFINE(aib_clk, "aib_clk", CCU_PARENT_NAME(vctcxo_24m),
+		       APBC_AIB_CLK_RST,
+		       BIT(1), BIT(1), 0x0,
+		       0);
+
+static CCU_GATE_DEFINE(onewire_clk, "onewire_clk", CCU_PARENT_NAME(vctcxo_24m),
+		       APBC_ONEWIRE_CLK_RST,
+		       BIT(1), BIT(1), 0x0,
+		       0);
+
+static const struct clk_parent_data sspa_parents[] = {
+	CCU_PARENT_HW(pll1_d384_6p4),
+	CCU_PARENT_HW(pll1_d192_12p8),
+	CCU_PARENT_HW(pll1_d96_25p6),
+	CCU_PARENT_HW(pll1_d48_51p2),
+	CCU_PARENT_HW(pll1_d768_3p2),
+	CCU_PARENT_HW(pll1_d1536_1p6),
+	CCU_PARENT_HW(pll1_d3072_0p8),
+	CCU_PARENT_HW(i2s_bclk),
+};
+static CCU_MUX_GATE_DEFINE(sspa0_clk, "sspa0_clk", sspa_parents,
+			   APBC_SSPA0_CLK_RST,
+			   4, 3, BIT(1), BIT(1), 0x0,
+			   0);
+static CCU_MUX_GATE_DEFINE(sspa1_clk, "sspa1_clk", sspa_parents,
+			   APBC_SSPA1_CLK_RST,
+			   4, 3, BIT(1), BIT(1), 0x0,
+			   0);
+static CCU_GATE_DEFINE(dro_clk, "dro_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_DRO_CLK_RST,
+		       BIT(1), BIT(1), 0x0,
+		       0);
+static CCU_GATE_DEFINE(ir_clk, "ir_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_IR_CLK_RST,
+		       BIT(1), BIT(1), 0x0,
+		       0);
+static CCU_GATE_DEFINE(tsen_clk, "tsen_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_TSEN_CLK_RST,
+		       BIT(1), BIT(1), 0x0,
+		       0);
+static CCU_GATE_DEFINE(ipc_ap2aud_clk, "ipc_ap2aud_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_IPC_AP2AUD_CLK_RST,
+		       BIT(1), BIT(1), 0x0,
+		       0);
+
+static const struct clk_parent_data can_parents[] = {
+	CCU_PARENT_HW(pll3_20),
+	CCU_PARENT_HW(pll3_40),
+	CCU_PARENT_HW(pll3_80),
+};
+static CCU_MUX_GATE_DEFINE(can0_clk, "can0_clk", can_parents,
+			   APBC_CAN0_CLK_RST,
+			   4, 3, BIT(1), BIT(1), 0x0,
+			   0);
+static CCU_GATE_DEFINE(can0_bus_clk, "can0_bus_clk", CCU_PARENT_NAME(vctcxo_24m),
+		       APBC_CAN0_CLK_RST,
+		       BIT(0), BIT(0), 0x0,
+		       0);
+
+static CCU_GATE_DEFINE(uart0_bus_clk, "uart0_bus_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_UART1_CLK_RST,
+		       BIT(0), BIT(0), 0x0,
+		       CLK_IS_CRITICAL);
+static CCU_GATE_DEFINE(uart2_bus_clk, "uart2_bus_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_UART2_CLK_RST,
+		       BIT(0), BIT(0), 0x0,
+		       0);
+static CCU_GATE_DEFINE(uart3_bus_clk, "uart3_bus_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_UART3_CLK_RST,
+		       BIT(0), BIT(0), 0x0,
+		       0);
+static CCU_GATE_DEFINE(uart4_bus_clk, "uart4_bus_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_UART4_CLK_RST,
+		       BIT(0), BIT(0), 0x0,
+		       0);
+static CCU_GATE_DEFINE(uart5_bus_clk, "uart5_bus_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_UART5_CLK_RST,
+		       BIT(0), BIT(0), 0x0,
+		       0);
+static CCU_GATE_DEFINE(uart6_bus_clk, "uart6_bus_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_UART6_CLK_RST,
+		       BIT(0), BIT(0), 0x0,
+		       0);
+static CCU_GATE_DEFINE(uart7_bus_clk, "uart7_bus_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_UART7_CLK_RST,
+		       BIT(0), BIT(0), 0x0,
+		       0);
+static CCU_GATE_DEFINE(uart8_bus_clk, "uart8_bus_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_UART8_CLK_RST,
+		       BIT(0), BIT(0), 0x0,
+		       0);
+static CCU_GATE_DEFINE(uart9_bus_clk, "uart9_bus_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_UART9_CLK_RST,
+		       BIT(0), BIT(0), 0x0,
+		       0);
+
+static CCU_GATE_DEFINE(gpio_bus_clk, "gpio_bus_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_GPIO_CLK_RST,
+		       BIT(0), BIT(0), 0x0,
+		       0);
+
+static CCU_GATE_DEFINE(pwm0_bus_clk, "pwm0_bus_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_PWM0_CLK_RST,
+		       BIT(0), BIT(0), 0x0,
+		       0);
+static CCU_GATE_DEFINE(pwm1_bus_clk, "pwm1_bus_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_PWM1_CLK_RST,
+		       BIT(0), BIT(0), 0x0,
+		       0);
+static CCU_GATE_DEFINE(pwm2_bus_clk, "pwm2_bus_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_PWM2_CLK_RST,
+		       BIT(0), BIT(0), 0x0,
+		       0);
+static CCU_GATE_DEFINE(pwm3_bus_clk, "pwm3_bus_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_PWM3_CLK_RST,
+		       BIT(0), BIT(0), 0x0,
+		       0);
+static CCU_GATE_DEFINE(pwm4_bus_clk, "pwm4_bus_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_PWM4_CLK_RST,
+		       BIT(0), BIT(0), 0x0,
+		       0);
+static CCU_GATE_DEFINE(pwm5_bus_clk, "pwm5_bus_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_PWM5_CLK_RST,
+		       BIT(0), BIT(0), 0x0,
+		       0);
+static CCU_GATE_DEFINE(pwm6_bus_clk, "pwm6_bus_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_PWM6_CLK_RST,
+		       BIT(0), BIT(0), 0x0,
+		       0);
+static CCU_GATE_DEFINE(pwm7_bus_clk, "pwm7_bus_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_PWM7_CLK_RST,
+		       BIT(0), BIT(0), 0x0,
+		       0);
+static CCU_GATE_DEFINE(pwm8_bus_clk, "pwm8_bus_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_PWM8_CLK_RST,
+		       BIT(0), BIT(0), 0x0,
+		       0);
+static CCU_GATE_DEFINE(pwm9_bus_clk, "pwm9_bus_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_PWM9_CLK_RST,
+		       BIT(0), BIT(0), 0x0,
+		       0);
+static CCU_GATE_DEFINE(pwm10_bus_clk, "pwm10_bus_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_PWM10_CLK_RST,
+		       BIT(0), BIT(0), 0x0,
+		       0);
+static CCU_GATE_DEFINE(pwm11_bus_clk, "pwm11_bus_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_PWM11_CLK_RST,
+		       BIT(0), BIT(0), 0x0,
+		       0);
+static CCU_GATE_DEFINE(pwm12_bus_clk, "pwm12_bus_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_PWM12_CLK_RST,
+		       BIT(0), BIT(0), 0x0,
+		       0);
+static CCU_GATE_DEFINE(pwm13_bus_clk, "pwm13_bus_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_PWM13_CLK_RST,
+		       BIT(0), BIT(0), 0x0,
+		       0);
+static CCU_GATE_DEFINE(pwm14_bus_clk, "pwm14_bus_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_PWM14_CLK_RST,
+		       BIT(0), BIT(0), 0x0,
+		       0);
+static CCU_GATE_DEFINE(pwm15_bus_clk, "pwm15_bus_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_PWM15_CLK_RST,
+		       BIT(0), BIT(0), 0x0,
+		       0);
+static CCU_GATE_DEFINE(pwm16_bus_clk, "pwm16_bus_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_PWM16_CLK_RST,
+		       BIT(0), BIT(0), 0x0,
+		       0);
+static CCU_GATE_DEFINE(pwm17_bus_clk, "pwm17_bus_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_PWM17_CLK_RST,
+		       BIT(0), BIT(0), 0x0,
+		       0);
+static CCU_GATE_DEFINE(pwm18_bus_clk, "pwm18_bus_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_PWM18_CLK_RST,
+		       BIT(0), BIT(0), 0x0,
+		       0);
+static CCU_GATE_DEFINE(pwm19_bus_clk, "pwm19_bus_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_PWM19_CLK_RST,
+		       BIT(0), BIT(0), 0x0,
+		       0);
+
+static CCU_GATE_DEFINE(ssp3_bus_clk, "ssp3_bus_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_SSP3_CLK_RST,
+		       BIT(0), BIT(0), 0x0,
+		       0);
+
+static CCU_GATE_DEFINE(rtc_bus_clk, "rtc_bus_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_RTC_CLK_RST,
+		       BIT(0), BIT(0), 0x0,
+		       0);
+
+static CCU_GATE_DEFINE(twsi0_bus_clk, "twsi0_bus_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_TWSI0_CLK_RST,
+		       BIT(0), BIT(0), 0x0,
+		       0);
+static CCU_GATE_DEFINE(twsi1_bus_clk, "twsi1_bus_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_TWSI1_CLK_RST,
+		       BIT(0), BIT(0), 0x0,
+		       0);
+static CCU_GATE_DEFINE(twsi2_bus_clk, "twsi2_bus_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_TWSI2_CLK_RST,
+		       BIT(0), BIT(0), 0x0,
+		       0);
+static CCU_GATE_DEFINE(twsi4_bus_clk, "twsi4_bus_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_TWSI4_CLK_RST,
+		       BIT(0), BIT(0), 0x0,
+		       0);
+static CCU_GATE_DEFINE(twsi5_bus_clk, "twsi5_bus_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_TWSI5_CLK_RST,
+		       BIT(0), BIT(0), 0x0,
+		       0);
+static CCU_GATE_DEFINE(twsi6_bus_clk, "twsi6_bus_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_TWSI6_CLK_RST,
+		       BIT(0), BIT(0), 0x0,
+		       0);
+static CCU_GATE_DEFINE(twsi7_bus_clk, "twsi7_bus_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_TWSI7_CLK_RST,
+		       BIT(0), BIT(0), 0x0,
+		       0);
+static CCU_GATE_DEFINE(twsi8_bus_clk, "twsi8_bus_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_TWSI8_CLK_RST,
+		       BIT(0), BIT(0), 0x0,
+		       0);
+
+static CCU_GATE_DEFINE(timers1_bus_clk, "timers1_bus_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_TIMERS1_CLK_RST,
+		       BIT(0), BIT(0), 0x0,
+		       0);
+static CCU_GATE_DEFINE(timers2_bus_clk, "timers2_bus_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_TIMERS2_CLK_RST,
+		       BIT(0), BIT(0), 0x0,
+		       0);
+
+static CCU_GATE_DEFINE(aib_bus_clk, "aib_bus_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_AIB_CLK_RST,
+		       BIT(0), BIT(0), 0x0,
+		       0);
+
+static CCU_GATE_DEFINE(onewire_bus_clk, "onewire_bus_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_ONEWIRE_CLK_RST,
+		       BIT(0), BIT(0), 0x0,
+		       0);
+
+static CCU_GATE_DEFINE(sspa0_bus_clk, "sspa0_bus_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_SSPA0_CLK_RST,
+		       BIT(0), BIT(0), 0x0,
+		       0);
+static CCU_GATE_DEFINE(sspa1_bus_clk, "sspa1_bus_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_SSPA1_CLK_RST,
+		       BIT(0), BIT(0), 0x0,
+		       0);
+
+static CCU_GATE_DEFINE(tsen_bus_clk, "tsen_bus_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_TSEN_CLK_RST,
+		       BIT(0), BIT(0), 0x0,
+		       0);
+
+static CCU_GATE_DEFINE(ipc_ap2aud_bus_clk, "ipc_ap2aud_bus_clk", CCU_PARENT_HW(apb_clk),
+		       APBC_IPC_AP2AUD_CLK_RST,
+		       BIT(0), BIT(0), 0x0,
+		       0);
+/*	APBC clocks end		*/
+
+/*	APMU clocks start	*/
+static const struct clk_parent_data pmua_aclk_parents[] = {
+	CCU_PARENT_HW(pll1_d10_245p76),
+	CCU_PARENT_HW(pll1_d8_307p2),
+};
+static CCU_DIV_FC_MUX_DEFINE(pmua_aclk, "pmua_aclk", pmua_aclk_parents,
+			     APMU_ACLK_CLK_CTRL,
+			     1, 2, BIT(4),
+			     0, 1,
+			     0);
+
+static const struct clk_parent_data cci550_clk_parents[] = {
+	CCU_PARENT_HW(pll1_d5_491p52),
+	CCU_PARENT_HW(pll1_d4_614p4),
+	CCU_PARENT_HW(pll1_d3_819p2),
+	CCU_PARENT_HW(pll2_d3),
+};
+static CCU_DIV_FC_MUX_DEFINE(cci550_clk, "cci550_clk", cci550_clk_parents,
+			     APMU_CCI550_CLK_CTRL,
+			     8, 3, BIT(12), 0, 2, CLK_IS_CRITICAL);
+
+static const struct clk_parent_data cpu_c0_hi_clk_parents[] = {
+	CCU_PARENT_HW(pll3_d2),
+	CCU_PARENT_HW(pll3_d1),
+};
+static CCU_MUX_DEFINE(cpu_c0_hi_clk, "cpu_c0_hi_clk", cpu_c0_hi_clk_parents,
+		      APMU_CPU_C0_CLK_CTRL,
+		      13, 1, 0);
+static const struct clk_parent_data cpu_c0_clk_parents[] = {
+	CCU_PARENT_HW(pll1_d4_614p4),
+	CCU_PARENT_HW(pll1_d3_819p2),
+	CCU_PARENT_HW(pll1_d6_409p6),
+	CCU_PARENT_HW(pll1_d5_491p52),
+	CCU_PARENT_HW(pll1_d2_1228p8),
+	CCU_PARENT_HW(pll3_d3),
+	CCU_PARENT_HW(pll2_d3),
+	CCU_PARENT_HW(cpu_c0_hi_clk),
+};
+static CCU_MUX_FC_DEFINE(cpu_c0_core_clk, "cpu_c0_core_clk", cpu_c0_clk_parents,
+			 APMU_CPU_C0_CLK_CTRL,
+			 BIT(12), 0, 3, CLK_IS_CRITICAL);
+static CCU_DIV_DEFINE(cpu_c0_ace_clk, "cpu_c0_ace_clk", CCU_PARENT_HW(cpu_c0_core_clk),
+		      APMU_CPU_C0_CLK_CTRL,
+		      6, 3, CLK_IS_CRITICAL);
+static CCU_DIV_DEFINE(cpu_c0_tcm_clk, "cpu_c0_tcm_clk", CCU_PARENT_HW(cpu_c0_core_clk),
+		      APMU_CPU_C0_CLK_CTRL, 9, 3, CLK_IS_CRITICAL);
+
+static const struct clk_parent_data cpu_c1_hi_clk_parents[] = {
+	CCU_PARENT_HW(pll3_d2),
+	CCU_PARENT_HW(pll3_d1),
+};
+static CCU_MUX_DEFINE(cpu_c1_hi_clk, "cpu_c1_hi_clk", cpu_c1_hi_clk_parents,
+		      APMU_CPU_C1_CLK_CTRL,
+		      13, 1, CLK_IS_CRITICAL);
+static const struct clk_parent_data cpu_c1_clk_parents[] = {
+	CCU_PARENT_HW(pll1_d4_614p4),
+	CCU_PARENT_HW(pll1_d3_819p2),
+	CCU_PARENT_HW(pll1_d6_409p6),
+	CCU_PARENT_HW(pll1_d5_491p52),
+	CCU_PARENT_HW(pll1_d2_1228p8),
+	CCU_PARENT_HW(pll3_d3),
+	CCU_PARENT_HW(pll2_d3),
+	CCU_PARENT_HW(cpu_c1_hi_clk),
+};
+static CCU_MUX_FC_DEFINE(cpu_c1_core_clk, "cpu_c1_core_clk", cpu_c1_clk_parents,
+			 APMU_CPU_C1_CLK_CTRL,
+			 BIT(12), 0, 3, CLK_IS_CRITICAL);
+static CCU_DIV_DEFINE(cpu_c1_ace_clk, "cpu_c1_ace_clk", CCU_PARENT_HW(cpu_c1_core_clk),
+		      APMU_CPU_C1_CLK_CTRL,
+		      6, 3, CLK_IS_CRITICAL);
+
+static const struct clk_parent_data jpg_parents[] = {
+	CCU_PARENT_HW(pll1_d4_614p4),
+	CCU_PARENT_HW(pll1_d6_409p6),
+	CCU_PARENT_HW(pll1_d5_491p52),
+	CCU_PARENT_HW(pll1_d3_819p2),
+	CCU_PARENT_HW(pll1_d2_1228p8),
+	CCU_PARENT_HW(pll2_d4),
+	CCU_PARENT_HW(pll2_d3),
+};
+static CCU_DIV_FC_MUX_GATE_DEFINE(jpg_clk, "jpg_clk", jpg_parents,
+				  APMU_JPG_CLK_RES_CTRL,
+				  5, 3, BIT(15),
+				  2, 3, BIT(1), BIT(1), 0x0,
+				  0);
+
+static const struct clk_parent_data ccic2phy_parents[] = {
+	CCU_PARENT_HW(pll1_d24_102p4),
+	CCU_PARENT_HW(pll1_d48_51p2_ap),
+};
+static CCU_MUX_GATE_DEFINE(ccic2phy_clk, "ccic2phy_clk", ccic2phy_parents,
+			   APMU_CSI_CCIC2_CLK_RES_CTRL,
+			   7, 1, BIT(5), BIT(5), 0x0,
+			   0);
+
+static const struct clk_parent_data ccic3phy_parents[] = {
+	CCU_PARENT_HW(pll1_d24_102p4),
+	CCU_PARENT_HW(pll1_d48_51p2_ap),
+};
+static CCU_MUX_GATE_DEFINE(ccic3phy_clk, "ccic3phy_clk", ccic3phy_parents,
+			   APMU_CSI_CCIC2_CLK_RES_CTRL,
+			   31, 1, BIT(30), BIT(30), 0x0,
+			   0);
+
+static const struct clk_parent_data csi_parents[] = {
+	CCU_PARENT_HW(pll1_d5_491p52),
+	CCU_PARENT_HW(pll1_d6_409p6),
+	CCU_PARENT_HW(pll1_d4_614p4),
+	CCU_PARENT_HW(pll1_d3_819p2),
+	CCU_PARENT_HW(pll2_d2),
+	CCU_PARENT_HW(pll2_d3),
+	CCU_PARENT_HW(pll2_d4),
+	CCU_PARENT_HW(pll1_d2_1228p8),
+};
+static CCU_DIV_FC_MUX_GATE_DEFINE(csi_clk, "csi_clk", csi_parents,
+				  APMU_CSI_CCIC2_CLK_RES_CTRL,
+				  20, 3, BIT(15),
+				  16, 3, BIT(4), BIT(4), 0x0,
+				  0);
+
+static const struct clk_parent_data camm_parents[] = {
+	CCU_PARENT_HW(pll1_d8_307p2),
+	CCU_PARENT_HW(pll2_d5),
+	CCU_PARENT_HW(pll1_d6_409p6),
+	CCU_PARENT_NAME(vctcxo_24m),
+};
+static CCU_DIV_MUX_GATE_DEFINE(camm0_clk, "camm0_clk", camm_parents,
+			       APMU_CSI_CCIC2_CLK_RES_CTRL,
+			       23, 4, 8, 2,
+			       BIT(28), BIT(28), 0x0,
+			       0);
+static CCU_DIV_MUX_GATE_DEFINE(camm1_clk, "camm1_clk", camm_parents,
+			       APMU_CSI_CCIC2_CLK_RES_CTRL,
+			       23, 4, 8, 2, BIT(6), BIT(6), 0x0,
+			       0);
+static CCU_DIV_MUX_GATE_DEFINE(camm2_clk, "camm2_clk", camm_parents,
+			       APMU_CSI_CCIC2_CLK_RES_CTRL,
+			       23, 4, 8, 2, BIT(3), BIT(3), 0x0,
+			       0);
+
+static const struct clk_parent_data isp_cpp_parents[] = {
+	CCU_PARENT_HW(pll1_d8_307p2),
+	CCU_PARENT_HW(pll1_d6_409p6),
+};
+static CCU_DIV_MUX_GATE_DEFINE(isp_cpp_clk, "isp_cpp_clk", isp_cpp_parents,
+			       APMU_ISP_CLK_RES_CTRL,
+			       24, 2, 26, 1, BIT(28), BIT(28), 0x0,
+			       0);
+static const struct clk_parent_data isp_bus_parents[] = {
+	CCU_PARENT_HW(pll1_d6_409p6),
+	CCU_PARENT_HW(pll1_d5_491p52),
+	CCU_PARENT_HW(pll1_d8_307p2),
+	CCU_PARENT_HW(pll1_d10_245p76),
+};
+static CCU_DIV_FC_MUX_GATE_DEFINE(isp_bus_clk, "isp_bus_clk", isp_bus_parents,
+				  APMU_ISP_CLK_RES_CTRL,
+				  18, 3, BIT(23),
+				  21, 2, BIT(17), BIT(17), 0x0,
+				  0);
+static const struct clk_parent_data isp_parents[] = {
+	CCU_PARENT_HW(pll1_d6_409p6),
+	CCU_PARENT_HW(pll1_d5_491p52),
+	CCU_PARENT_HW(pll1_d4_614p4),
+	CCU_PARENT_HW(pll1_d8_307p2),
+};
+static CCU_DIV_FC_MUX_GATE_DEFINE(isp_clk, "isp_clk", isp_parents,
+				  APMU_ISP_CLK_RES_CTRL,
+				  4, 3, BIT(7),
+				  8, 2, BIT(1), BIT(1), 0x0,
+				  0);
+
+static const struct clk_parent_data dpumclk_parents[] = {
+	CCU_PARENT_HW(pll1_d6_409p6),
+	CCU_PARENT_HW(pll1_d5_491p52),
+	CCU_PARENT_HW(pll1_d4_614p4),
+	CCU_PARENT_HW(pll1_d8_307p2),
+};
+static CCU_DIV2_FC_MUX_GATE_DEFINE(dpu_mclk, "dpu_mclk", dpumclk_parents,
+				   APMU_LCD_CLK_RES_CTRL1,
+				   APMU_LCD_CLK_RES_CTRL2,
+				   1, 4, BIT(29),
+				   5, 3, BIT(0), BIT(0), 0x0,
+				   0);
+
+static const struct clk_parent_data dpuesc_parents[] = {
+	CCU_PARENT_HW(pll1_d48_51p2_ap),
+	CCU_PARENT_HW(pll1_d52_47p26),
+	CCU_PARENT_HW(pll1_d96_25p6),
+	CCU_PARENT_HW(pll1_d32_76p8),
+};
+static CCU_MUX_GATE_DEFINE(dpu_esc_clk, "dpu_esc_clk", dpuesc_parents,
+			   APMU_LCD_CLK_RES_CTRL1,
+			   0, 2, BIT(2), BIT(2), 0x0,
+			   0);
+
+static const struct clk_parent_data dpubit_parents[] = {
+	CCU_PARENT_HW(pll1_d3_819p2),
+	CCU_PARENT_HW(pll2_d2),
+	CCU_PARENT_HW(pll2_d3),
+	CCU_PARENT_HW(pll1_d2_1228p8),
+	CCU_PARENT_HW(pll2_d4),
+	CCU_PARENT_HW(pll2_d5),
+	CCU_PARENT_HW(pll2_d8),
+	CCU_PARENT_HW(pll2_d8),
+};
+static CCU_DIV_FC_MUX_GATE_DEFINE(dpu_bit_clk, "dpu_bit_clk", dpubit_parents,
+				  APMU_LCD_CLK_RES_CTRL1,
+				  17, 3, BIT(31),
+				  20, 3, BIT(16), BIT(16), 0x0,
+				  0);
+
+static const struct clk_parent_data dpupx_parents[] = {
+	CCU_PARENT_HW(pll1_d6_409p6),
+	CCU_PARENT_HW(pll1_d5_491p52),
+	CCU_PARENT_HW(pll1_d4_614p4),
+	CCU_PARENT_HW(pll1_d8_307p2),
+	CCU_PARENT_HW(pll2_d7),
+	CCU_PARENT_HW(pll2_d8),
+};
+static CCU_DIV2_FC_MUX_GATE_DEFINE(dpu_pxclk, "dpu_pxclk", dpupx_parents,
+				  APMU_LCD_CLK_RES_CTRL1,
+				  APMU_LCD_CLK_RES_CTRL2,
+				  17, 4, BIT(30),
+				  21, 3, BIT(16), BIT(16), 0x0,
+				  0);
+
+static CCU_GATE_DEFINE(dpu_hclk, "dpu_hclk", CCU_PARENT_HW(pmua_aclk),
+		       APMU_LCD_CLK_RES_CTRL1,
+		       BIT(5), BIT(5), 0x0,
+		       0);
+
+static const struct clk_parent_data dpu_spi_parents[] = {
+	CCU_PARENT_HW(pll1_d8_307p2),
+	CCU_PARENT_HW(pll1_d6_409p6),
+	CCU_PARENT_HW(pll1_d10_245p76),
+	CCU_PARENT_HW(pll1_d11_223p4),
+	CCU_PARENT_HW(pll1_d13_189),
+	CCU_PARENT_HW(pll1_d23_106p8),
+	CCU_PARENT_HW(pll2_d3),
+	CCU_PARENT_HW(pll2_d5),
+};
+static CCU_DIV_FC_MUX_GATE_DEFINE(dpu_spi_clk, "dpu_spi_clk", dpu_spi_parents,
+				  APMU_LCD_SPI_CLK_RES_CTRL,
+				  8, 3, BIT(7),
+				  12, 3, BIT(1), BIT(1), 0x0,
+				  0);
+static CCU_GATE_DEFINE(dpu_spi_hbus_clk, "dpu_spi_hbus_clk", CCU_PARENT_HW(pmua_aclk),
+		       APMU_LCD_SPI_CLK_RES_CTRL,
+		       BIT(3), BIT(3), 0x0,
+		       0);
+static CCU_GATE_DEFINE(dpu_spi_bus_clk, "dpu_spi_bus_clk", CCU_PARENT_HW(pmua_aclk),
+		       APMU_LCD_SPI_CLK_RES_CTRL,
+		       BIT(5), BIT(5), 0x0,
+		       0);
+static CCU_GATE_DEFINE(dpu_spi_aclk, "dpu_spi_aclk", CCU_PARENT_HW(pmua_aclk),
+		       APMU_LCD_SPI_CLK_RES_CTRL,
+		       BIT(6), BIT(6), 0x0,
+		       0);
+
+static const struct clk_parent_data v2d_parents[] = {
+	CCU_PARENT_HW(pll1_d5_491p52),
+	CCU_PARENT_HW(pll1_d6_409p6),
+	CCU_PARENT_HW(pll1_d8_307p2),
+	CCU_PARENT_HW(pll1_d4_614p4),
+};
+static CCU_DIV_FC_MUX_GATE_DEFINE(v2d_clk, "v2d_clk", v2d_parents,
+				  APMU_LCD_CLK_RES_CTRL1,
+				  9, 3, BIT(28),
+				  12, 2, BIT(8), BIT(8), 0x0,
+				  0);
+
+static const struct clk_parent_data ccic_4x_parents[] = {
+	CCU_PARENT_HW(pll1_d5_491p52),
+	CCU_PARENT_HW(pll1_d6_409p6),
+	CCU_PARENT_HW(pll1_d4_614p4),
+	CCU_PARENT_HW(pll1_d3_819p2),
+	CCU_PARENT_HW(pll2_d2),
+	CCU_PARENT_HW(pll2_d3),
+	CCU_PARENT_HW(pll2_d4),
+	CCU_PARENT_HW(pll1_d2_1228p8),
+};
+static CCU_DIV_FC_MUX_GATE_DEFINE(ccic_4x_clk, "ccic_4x_clk", ccic_4x_parents,
+				  APMU_CCIC_CLK_RES_CTRL,
+				  18, 3, BIT(15),
+				  23, 2, BIT(4), BIT(4), 0x0,
+				  0);
+
+static const struct clk_parent_data ccic1phy_parents[] = {
+	CCU_PARENT_HW(pll1_d24_102p4),
+	CCU_PARENT_HW(pll1_d48_51p2_ap),
+};
+static CCU_MUX_GATE_DEFINE(ccic1phy_clk, "ccic1phy_clk", ccic1phy_parents,
+			   APMU_CCIC_CLK_RES_CTRL,
+			   7, 1, BIT(5), BIT(5), 0x0,
+			   0);
+
+static CCU_GATE_DEFINE(sdh_axi_aclk, "sdh_axi_aclk", CCU_PARENT_HW(pmua_aclk),
+		       APMU_SDH0_CLK_RES_CTRL,
+		       BIT(3), BIT(3), 0x0,
+		       0);
+static const struct clk_parent_data sdh01_parents[] = {
+	CCU_PARENT_HW(pll1_d6_409p6),
+	CCU_PARENT_HW(pll1_d4_614p4),
+	CCU_PARENT_HW(pll2_d8),
+	CCU_PARENT_HW(pll2_d5),
+	CCU_PARENT_HW(pll1_d11_223p4),
+	CCU_PARENT_HW(pll1_d13_189),
+	CCU_PARENT_HW(pll1_d23_106p8),
+};
+static CCU_DIV_FC_MUX_GATE_DEFINE(sdh0_clk, "sdh0_clk", sdh01_parents,
+				  APMU_SDH0_CLK_RES_CTRL,
+				  8, 3, BIT(11),
+				  5, 3, BIT(4), BIT(4), 0x0,
+				  0);
+static CCU_DIV_FC_MUX_GATE_DEFINE(sdh1_clk, "sdh1_clk", sdh01_parents,
+				  APMU_SDH1_CLK_RES_CTRL,
+				  8, 3, BIT(11),
+				  5, 3, BIT(4), BIT(4), 0x0,
+				  0);
+static const struct clk_parent_data sdh2_parents[] = {
+	CCU_PARENT_HW(pll1_d6_409p6),
+	CCU_PARENT_HW(pll1_d4_614p4),
+	CCU_PARENT_HW(pll2_d8),
+	CCU_PARENT_HW(pll1_d3_819p2),
+	CCU_PARENT_HW(pll1_d11_223p4),
+	CCU_PARENT_HW(pll1_d13_189),
+	CCU_PARENT_HW(pll1_d23_106p8),
+};
+static CCU_DIV_FC_MUX_GATE_DEFINE(sdh2_clk, "sdh2_clk", sdh2_parents,
+				  APMU_SDH2_CLK_RES_CTRL,
+				  8, 3, BIT(11),
+				  5, 3, BIT(4), BIT(4), 0x0,
+				  0);
+
+static CCU_GATE_DEFINE(usb_axi_clk, "usb_axi_clk", CCU_PARENT_HW(pmua_aclk),
+		       APMU_USB_CLK_RES_CTRL,
+		       BIT(1), BIT(1), 0x0,
+		       0);
+static CCU_GATE_DEFINE(usb_p1_aclk, "usb_p1_aclk", CCU_PARENT_HW(pmua_aclk),
+		       APMU_USB_CLK_RES_CTRL,
+		       BIT(5), BIT(5), 0x0,
+		       0);
+static CCU_GATE_DEFINE(usb30_clk, "usb30_clk", CCU_PARENT_HW(pmua_aclk),
+		       APMU_USB_CLK_RES_CTRL,
+		       BIT(8), BIT(8), 0x0,
+		       0);
+
+static const struct clk_parent_data qspi_parents[] = {
+	CCU_PARENT_HW(pll1_d6_409p6),
+	CCU_PARENT_HW(pll2_d8),
+	CCU_PARENT_HW(pll1_d8_307p2),
+	CCU_PARENT_HW(pll1_d10_245p76),
+	CCU_PARENT_HW(pll1_d11_223p4),
+	CCU_PARENT_HW(pll1_d23_106p8),
+	CCU_PARENT_HW(pll1_d5_491p52),
+	CCU_PARENT_HW(pll1_d13_189),
+};
+static CCU_DIV_MFC_MUX_GATE_DEFINE(qspi_clk, "qspi_clk", qspi_parents,
+				   APMU_QSPI_CLK_RES_CTRL,
+				   9, 3, BIT(12),
+				   6, 3, BIT(4), BIT(4), 0x0,
+				   0);
+static CCU_GATE_DEFINE(qspi_bus_clk, "qspi_bus_clk", CCU_PARENT_HW(pmua_aclk),
+		       APMU_QSPI_CLK_RES_CTRL,
+		       BIT(3), BIT(3), 0x0,
+		       0);
+static CCU_GATE_DEFINE(dma_clk, "dma_clk", CCU_PARENT_HW(pmua_aclk),
+		       APMU_DMA_CLK_RES_CTRL,
+		       BIT(3), BIT(3), 0x0,
+		       0);
+
+static const struct clk_parent_data aes_parents[] = {
+	CCU_PARENT_HW(pll1_d12_204p8),
+	CCU_PARENT_HW(pll1_d24_102p4),
+};
+static CCU_MUX_GATE_DEFINE(aes_clk, "aes_clk", aes_parents,
+			   APMU_AES_CLK_RES_CTRL,
+			   6, 1, BIT(5), BIT(5), 0x0,
+			   0);
+
+static const struct clk_parent_data vpu_parents[] = {
+	CCU_PARENT_HW(pll1_d4_614p4),
+	CCU_PARENT_HW(pll1_d5_491p52),
+	CCU_PARENT_HW(pll1_d3_819p2),
+	CCU_PARENT_HW(pll1_d6_409p6),
+	CCU_PARENT_HW(pll3_d6),
+	CCU_PARENT_HW(pll2_d3),
+	CCU_PARENT_HW(pll2_d4),
+	CCU_PARENT_HW(pll2_d5),
+};
+static CCU_DIV_FC_MUX_GATE_DEFINE(vpu_clk, "vpu_clk", vpu_parents,
+				  APMU_VPU_CLK_RES_CTRL,
+				  13, 3, BIT(21),
+				  10, 3,
+				  BIT(3), BIT(3), 0x0,
+				  0);
+
+static const struct clk_parent_data gpu_parents[] = {
+	CCU_PARENT_HW(pll1_d4_614p4),
+	CCU_PARENT_HW(pll1_d5_491p52),
+	CCU_PARENT_HW(pll1_d3_819p2),
+	CCU_PARENT_HW(pll1_d6_409p6),
+	CCU_PARENT_HW(pll3_d6),
+	CCU_PARENT_HW(pll2_d3),
+	CCU_PARENT_HW(pll2_d4),
+	CCU_PARENT_HW(pll2_d5),
+};
+static CCU_DIV_FC_MUX_GATE_DEFINE(gpu_clk, "gpu_clk", gpu_parents,
+				  APMU_GPU_CLK_RES_CTRL,
+				  12, 3, BIT(15),
+				  18, 3,
+				  BIT(4), BIT(4), 0x0,
+				  0);
+
+static const struct clk_parent_data emmc_parents[] = {
+	CCU_PARENT_HW(pll1_d6_409p6),
+	CCU_PARENT_HW(pll1_d4_614p4),
+	CCU_PARENT_HW(pll1_d52_47p26),
+	CCU_PARENT_HW(pll1_d3_819p2),
+};
+static CCU_DIV_FC_MUX_GATE_DEFINE(emmc_clk, "emmc_clk", emmc_parents,
+				  APMU_PMUA_EM_CLK_RES_CTRL,
+				  8, 3, BIT(11),
+				  6, 2,
+				  BIT(4), BIT(4), 0x0,
+				  0);
+static CCU_DIV_GATE_DEFINE(emmc_x_clk, "emmc_x_clk", CCU_PARENT_HW(pll1_d2_1228p8),
+			   APMU_PMUA_EM_CLK_RES_CTRL,
+			   12, 3, BIT(15), BIT(15), 0x0,
+			   0);
+
+static const struct clk_parent_data audio_parents[] = {
+	CCU_PARENT_HW(pll1_aud_245p7),
+	CCU_PARENT_HW(pll1_d8_307p2),
+	CCU_PARENT_HW(pll1_d6_409p6),
+};
+static CCU_DIV_FC_MUX_GATE_DEFINE(audio_clk, "audio_clk", audio_parents,
+				  APMU_AUDIO_CLK_RES_CTRL,
+				  4, 3, BIT(15),
+				  7, 3,
+				  BIT(12), BIT(12), 0x0,
+				  0);
+
+static const struct clk_parent_data hdmi_parents[] = {
+	CCU_PARENT_HW(pll1_d6_409p6),
+	CCU_PARENT_HW(pll1_d5_491p52),
+	CCU_PARENT_HW(pll1_d4_614p4),
+	CCU_PARENT_HW(pll1_d8_307p2),
+};
+static CCU_DIV_FC_MUX_GATE_DEFINE(hdmi_mclk, "hdmi_mclk", hdmi_parents,
+				  APMU_HDMI_CLK_RES_CTRL,
+				  1, 4, BIT(29),
+				  5, 3,
+				  BIT(0), BIT(0), 0x0,
+				  0);
+
+static CCU_GATE_DEFINE(pcie0_clk, "pcie0_clk", CCU_PARENT_HW(pmua_aclk),
+		       APMU_PCIE_CLK_RES_CTRL_0,
+		       0x7, 0x7, 0x0,
+		       0);
+static CCU_GATE_DEFINE(pcie1_clk, "pcie1_clk", CCU_PARENT_HW(pmua_aclk),
+		       APMU_PCIE_CLK_RES_CTRL_1,
+		       0x7, 0x7, 0x0,
+		       0);
+static CCU_GATE_DEFINE(pcie2_clk, "pcie2_clk", CCU_PARENT_HW(pmua_aclk),
+		       APMU_PCIE_CLK_RES_CTRL_2,
+		       0x7, 0x7, 0x0,
+		       0);
+
+static CCU_GATE_DEFINE(emac0_bus_clk, "emac0_bus_clk", CCU_PARENT_HW(pmua_aclk),
+		       APMU_EMAC0_CLK_RES_CTRL,
+		       BIT(0), BIT(0), 0x0,
+		       0);
+static CCU_GATE_DEFINE(emac0_ptp_clk, "emac0_ptp_clk", CCU_PARENT_HW(pll2_d6),
+		       APMU_EMAC0_CLK_RES_CTRL,
+		       BIT(15), BIT(15), 0x0,
+		       0);
+static CCU_GATE_DEFINE(emac1_bus_clk, "emac1_bus_clk", CCU_PARENT_HW(pmua_aclk),
+		       APMU_EMAC1_CLK_RES_CTRL,
+		       BIT(0), BIT(0), 0x0,
+		       0);
+static CCU_GATE_DEFINE(emac1_ptp_clk, "emac1_ptp_clk", CCU_PARENT_HW(pll2_d6),
+		       APMU_EMAC1_CLK_RES_CTRL,
+		       BIT(15), BIT(15), 0x0,
+		       0);
+
+static CCU_GATE_DEFINE(emmc_bus_clk, "emmc_bus_clk", CCU_PARENT_HW(pmua_aclk),
+		       APMU_PMUA_EM_CLK_RES_CTRL,
+		       BIT(3), BIT(3), 0,
+		       0);
+/*	APMU clocks end		*/
+
+static struct clk_hw_onecell_data k1_ccu_apbs_clks = {
+	.hws = {
+		[CLK_PLL1]		= &pll1.common.hw,
+		[CLK_PLL2]		= &pll2.common.hw,
+		[CLK_PLL3]		= &pll3.common.hw,
+		[CLK_PLL1_D2]		= &pll1_d2.common.hw,
+		[CLK_PLL1_D3]		= &pll1_d3.common.hw,
+		[CLK_PLL1_D4]		= &pll1_d4.common.hw,
+		[CLK_PLL1_D5]		= &pll1_d5.common.hw,
+		[CLK_PLL1_D6]		= &pll1_d6.common.hw,
+		[CLK_PLL1_D7]		= &pll1_d7.common.hw,
+		[CLK_PLL1_D8]		= &pll1_d8.common.hw,
+		[CLK_PLL1_D11]		= &pll1_d11_223p4.common.hw,
+		[CLK_PLL1_D13]		= &pll1_d13_189.common.hw,
+		[CLK_PLL1_D23]		= &pll1_d23_106p8.common.hw,
+		[CLK_PLL1_D64]		= &pll1_d64_38p4.common.hw,
+		[CLK_PLL1_D10_AUD]	= &pll1_aud_245p7.common.hw,
+		[CLK_PLL1_D100_AUD]	= &pll1_aud_24p5.common.hw,
+		[CLK_PLL2_D1]		= &pll2_d1.common.hw,
+		[CLK_PLL2_D2]		= &pll2_d2.common.hw,
+		[CLK_PLL2_D3]		= &pll2_d3.common.hw,
+		[CLK_PLL2_D3]		= &pll2_d4.common.hw,
+		[CLK_PLL2_D5]		= &pll2_d5.common.hw,
+		[CLK_PLL2_D6]		= &pll2_d6.common.hw,
+		[CLK_PLL2_D7]		= &pll2_d7.common.hw,
+		[CLK_PLL2_D8]		= &pll2_d8.common.hw,
+		[CLK_PLL3_D1]		= &pll3_d1.common.hw,
+		[CLK_PLL3_D2]		= &pll3_d2.common.hw,
+		[CLK_PLL3_D3]		= &pll3_d3.common.hw,
+		[CLK_PLL3_D4]		= &pll3_d4.common.hw,
+		[CLK_PLL3_D5]		= &pll3_d5.common.hw,
+		[CLK_PLL3_D6]		= &pll3_d6.common.hw,
+		[CLK_PLL3_D7]		= &pll3_d7.common.hw,
+		[CLK_PLL3_D8]		= &pll3_d8.common.hw,
+		[CLK_PLL3_80]		= &pll3_80.common.hw,
+		[CLK_PLL3_40]		= &pll3_40.common.hw,
+		[CLK_PLL3_20]		= &pll3_20.common.hw,
+
+	},
+	.num = CLK_APBS_NUM,
+};
+
+static struct clk_hw_onecell_data k1_ccu_mpmu_clks = {
+	.hws = {
+		[CLK_PLL1_307P2]	= &pll1_d8_307p2.common.hw,
+		[CLK_PLL1_76P8]		= &pll1_d32_76p8.common.hw,
+		[CLK_PLL1_61P44]	= &pll1_d40_61p44.common.hw,
+		[CLK_PLL1_153P6]	= &pll1_d16_153p6.common.hw,
+		[CLK_PLL1_102P4]	= &pll1_d24_102p4.common.hw,
+		[CLK_PLL1_51P2]		= &pll1_d48_51p2.common.hw,
+		[CLK_PLL1_51P2_AP]	= &pll1_d48_51p2_ap.common.hw,
+		[CLK_PLL1_57P6]		= &pll1_m3d128_57p6.common.hw,
+		[CLK_PLL1_25P6]		= &pll1_d96_25p6.common.hw,
+		[CLK_PLL1_12P8]		= &pll1_d192_12p8.common.hw,
+		[CLK_PLL1_12P8_WDT]	= &pll1_d192_12p8_wdt.common.hw,
+		[CLK_PLL1_6P4]		= &pll1_d384_6p4.common.hw,
+		[CLK_PLL1_3P2]		= &pll1_d768_3p2.common.hw,
+		[CLK_PLL1_1P6]		= &pll1_d1536_1p6.common.hw,
+		[CLK_PLL1_0P8]		= &pll1_d3072_0p8.common.hw,
+		[CLK_PLL1_351]		= &pll1_d7_351p08.common.hw,
+		[CLK_PLL1_409P6]	= &pll1_d6_409p6.common.hw,
+		[CLK_PLL1_204P8]	= &pll1_d12_204p8.common.hw,
+		[CLK_PLL1_491]		= &pll1_d5_491p52.common.hw,
+		[CLK_PLL1_245P76]	= &pll1_d10_245p76.common.hw,
+		[CLK_PLL1_614]		= &pll1_d4_614p4.common.hw,
+		[CLK_PLL1_47P26]	= &pll1_d52_47p26.common.hw,
+		[CLK_PLL1_31P5]		= &pll1_d78_31p5.common.hw,
+		[CLK_PLL1_819]		= &pll1_d3_819p2.common.hw,
+		[CLK_PLL1_1228]		= &pll1_d2_1228p8.common.hw,
+		[CLK_SLOW_UART]		= &slow_uart.common.hw,
+		[CLK_SLOW_UART1]	= &slow_uart1_14p74.common.hw,
+		[CLK_SLOW_UART2]	= &slow_uart2_48.common.hw,
+		[CLK_WDT]		= &wdt_clk.common.hw,
+		[CLK_RIPC]		= &ripc_clk.common.hw,
+		[CLK_I2S_SYSCLK]	= &i2s_sysclk.common.hw,
+		[CLK_I2S_BCLK]		= &i2s_bclk.common.hw,
+		[CLK_APB]		= &apb_clk.common.hw,
+		[CLK_WDT_BUS]		= &wdt_bus_clk.common.hw,
+	},
+	.num = CLK_MPMU_NUM,
+};
+
+static struct clk_hw_onecell_data k1_ccu_apbc_clks = {
+	.hws = {
+		[CLK_UART0]		= &uart0_clk.common.hw,
+		[CLK_UART2]		= &uart2_clk.common.hw,
+		[CLK_UART3]		= &uart3_clk.common.hw,
+		[CLK_UART4]		= &uart4_clk.common.hw,
+		[CLK_UART5]		= &uart5_clk.common.hw,
+		[CLK_UART6]		= &uart6_clk.common.hw,
+		[CLK_UART7]		= &uart7_clk.common.hw,
+		[CLK_UART8]		= &uart8_clk.common.hw,
+		[CLK_UART9]		= &uart9_clk.common.hw,
+		[CLK_GPIO]		= &gpio_clk.common.hw,
+		[CLK_PWM0]		= &pwm0_clk.common.hw,
+		[CLK_PWM1]		= &pwm1_clk.common.hw,
+		[CLK_PWM2]		= &pwm2_clk.common.hw,
+		[CLK_PWM3]		= &pwm3_clk.common.hw,
+		[CLK_PWM4]		= &pwm4_clk.common.hw,
+		[CLK_PWM5]		= &pwm5_clk.common.hw,
+		[CLK_PWM6]		= &pwm6_clk.common.hw,
+		[CLK_PWM7]		= &pwm7_clk.common.hw,
+		[CLK_PWM8]		= &pwm8_clk.common.hw,
+		[CLK_PWM9]		= &pwm9_clk.common.hw,
+		[CLK_PWM10]		= &pwm10_clk.common.hw,
+		[CLK_PWM11]		= &pwm11_clk.common.hw,
+		[CLK_PWM12]		= &pwm12_clk.common.hw,
+		[CLK_PWM13]		= &pwm13_clk.common.hw,
+		[CLK_PWM14]		= &pwm14_clk.common.hw,
+		[CLK_PWM15]		= &pwm15_clk.common.hw,
+		[CLK_PWM16]		= &pwm16_clk.common.hw,
+		[CLK_PWM17]		= &pwm17_clk.common.hw,
+		[CLK_PWM18]		= &pwm18_clk.common.hw,
+		[CLK_PWM19]		= &pwm19_clk.common.hw,
+		[CLK_SSP3]		= &ssp3_clk.common.hw,
+		[CLK_RTC]		= &rtc_clk.common.hw,
+		[CLK_TWSI0]		= &twsi0_clk.common.hw,
+		[CLK_TWSI1]		= &twsi1_clk.common.hw,
+		[CLK_TWSI2]		= &twsi2_clk.common.hw,
+		[CLK_TWSI4]		= &twsi4_clk.common.hw,
+		[CLK_TWSI5]		= &twsi5_clk.common.hw,
+		[CLK_TWSI6]		= &twsi6_clk.common.hw,
+		[CLK_TWSI7]		= &twsi7_clk.common.hw,
+		[CLK_TWSI8]		= &twsi8_clk.common.hw,
+		[CLK_TIMERS1]		= &timers1_clk.common.hw,
+		[CLK_TIMERS2]		= &timers2_clk.common.hw,
+		[CLK_AIB]		= &aib_clk.common.hw,
+		[CLK_ONEWIRE]		= &onewire_clk.common.hw,
+		[CLK_SSPA0]		= &sspa0_clk.common.hw,
+		[CLK_SSPA1]		= &sspa1_clk.common.hw,
+		[CLK_DRO]		= &dro_clk.common.hw,
+		[CLK_IR]		= &ir_clk.common.hw,
+		[CLK_TSEN]		= &tsen_clk.common.hw,
+		[CLK_IPC_AP2AUD]	= &ipc_ap2aud_clk.common.hw,
+		[CLK_CAN0]		= &can0_clk.common.hw,
+		[CLK_CAN0_BUS]		= &can0_bus_clk.common.hw,
+		[CLK_UART0_BUS]		= &uart0_bus_clk.common.hw,
+		[CLK_UART2_BUS]		= &uart2_bus_clk.common.hw,
+		[CLK_UART3_BUS]		= &uart3_bus_clk.common.hw,
+		[CLK_UART4_BUS]		= &uart4_bus_clk.common.hw,
+		[CLK_UART5_BUS]		= &uart5_bus_clk.common.hw,
+		[CLK_UART6_BUS]		= &uart6_bus_clk.common.hw,
+		[CLK_UART7_BUS]		= &uart7_bus_clk.common.hw,
+		[CLK_UART8_BUS]		= &uart8_bus_clk.common.hw,
+		[CLK_UART9_BUS]		= &uart9_bus_clk.common.hw,
+		[CLK_GPIO_BUS]		= &gpio_bus_clk.common.hw,
+		[CLK_PWM0_BUS]		= &pwm0_bus_clk.common.hw,
+		[CLK_PWM1_BUS]		= &pwm1_bus_clk.common.hw,
+		[CLK_PWM2_BUS]		= &pwm2_bus_clk.common.hw,
+		[CLK_PWM3_BUS]		= &pwm3_bus_clk.common.hw,
+		[CLK_PWM4_BUS]		= &pwm4_bus_clk.common.hw,
+		[CLK_PWM5_BUS]		= &pwm5_bus_clk.common.hw,
+		[CLK_PWM6_BUS]		= &pwm6_bus_clk.common.hw,
+		[CLK_PWM7_BUS]		= &pwm7_bus_clk.common.hw,
+		[CLK_PWM8_BUS]		= &pwm8_bus_clk.common.hw,
+		[CLK_PWM9_BUS]		= &pwm9_bus_clk.common.hw,
+		[CLK_PWM10_BUS]		= &pwm10_bus_clk.common.hw,
+		[CLK_PWM11_BUS]		= &pwm11_bus_clk.common.hw,
+		[CLK_PWM12_BUS]		= &pwm12_bus_clk.common.hw,
+		[CLK_PWM13_BUS]		= &pwm13_bus_clk.common.hw,
+		[CLK_PWM14_BUS]		= &pwm14_bus_clk.common.hw,
+		[CLK_PWM15_BUS]		= &pwm15_bus_clk.common.hw,
+		[CLK_PWM16_BUS]		= &pwm16_bus_clk.common.hw,
+		[CLK_PWM17_BUS]		= &pwm17_bus_clk.common.hw,
+		[CLK_PWM18_BUS]		= &pwm18_bus_clk.common.hw,
+		[CLK_PWM19_BUS]		= &pwm19_bus_clk.common.hw,
+		[CLK_SSP3_BUS]		= &ssp3_bus_clk.common.hw,
+		[CLK_RTC_BUS]		= &rtc_bus_clk.common.hw,
+		[CLK_TWSI0_BUS]		= &twsi0_bus_clk.common.hw,
+		[CLK_TWSI1_BUS]		= &twsi1_bus_clk.common.hw,
+		[CLK_TWSI2_BUS]		= &twsi2_bus_clk.common.hw,
+		[CLK_TWSI4_BUS]		= &twsi4_bus_clk.common.hw,
+		[CLK_TWSI5_BUS]		= &twsi5_bus_clk.common.hw,
+		[CLK_TWSI6_BUS]		= &twsi6_bus_clk.common.hw,
+		[CLK_TWSI7_BUS]		= &twsi7_bus_clk.common.hw,
+		[CLK_TWSI8_BUS]		= &twsi8_bus_clk.common.hw,
+		[CLK_TIMERS1_BUS]	= &timers1_bus_clk.common.hw,
+		[CLK_TIMERS2_BUS]	= &timers2_bus_clk.common.hw,
+		[CLK_AIB_BUS]		= &aib_bus_clk.common.hw,
+		[CLK_ONEWIRE_BUS]	= &onewire_bus_clk.common.hw,
+		[CLK_SSPA0_BUS]		= &sspa0_bus_clk.common.hw,
+		[CLK_SSPA1_BUS]		= &sspa1_bus_clk.common.hw,
+		[CLK_TSEN_BUS]		= &tsen_bus_clk.common.hw,
+		[CLK_IPC_AP2AUD_BUS]	= &ipc_ap2aud_bus_clk.common.hw,
+	},
+	.num = CLK_APBC_NUM,
+};
+
+static struct clk_hw_onecell_data k1_ccu_apmu_clks = {
+	.hws = {
+		[CLK_CCI550]		= &cci550_clk.common.hw,
+		[CLK_CPU_C0_HI]		= &cpu_c0_hi_clk.common.hw,
+		[CLK_CPU_C0_CORE]	= &cpu_c0_core_clk.common.hw,
+		[CLK_CPU_C0_ACE]	= &cpu_c0_ace_clk.common.hw,
+		[CLK_CPU_C0_TCM]	= &cpu_c0_tcm_clk.common.hw,
+		[CLK_CPU_C1_HI]		= &cpu_c1_hi_clk.common.hw,
+		[CLK_CPU_C1_CORE]	= &cpu_c1_core_clk.common.hw,
+		[CLK_CPU_C1_ACE]	= &cpu_c1_ace_clk.common.hw,
+		[CLK_CCIC_4X]		= &ccic_4x_clk.common.hw,
+		[CLK_CCIC1PHY]		= &ccic1phy_clk.common.hw,
+		[CLK_SDH_AXI]		= &sdh_axi_aclk.common.hw,
+		[CLK_SDH0]		= &sdh0_clk.common.hw,
+		[CLK_SDH1]		= &sdh1_clk.common.hw,
+		[CLK_SDH2]		= &sdh2_clk.common.hw,
+		[CLK_USB_P1]		= &usb_p1_aclk.common.hw,
+		[CLK_USB_AXI]		= &usb_axi_clk.common.hw,
+		[CLK_USB30]		= &usb30_clk.common.hw,
+		[CLK_QSPI]		= &qspi_clk.common.hw,
+		[CLK_QSPI_BUS]		= &qspi_bus_clk.common.hw,
+		[CLK_DMA]		= &dma_clk.common.hw,
+		[CLK_AES]		= &aes_clk.common.hw,
+		[CLK_VPU]		= &vpu_clk.common.hw,
+		[CLK_GPU]		= &gpu_clk.common.hw,
+		[CLK_EMMC]		= &emmc_clk.common.hw,
+		[CLK_EMMC_X]		= &emmc_x_clk.common.hw,
+		[CLK_AUDIO]		= &audio_clk.common.hw,
+		[CLK_HDMI]		= &hdmi_mclk.common.hw,
+		[CLK_PMUA_ACLK]		= &pmua_aclk.common.hw,
+		[CLK_PCIE0]		= &pcie0_clk.common.hw,
+		[CLK_PCIE1]		= &pcie1_clk.common.hw,
+		[CLK_PCIE2]		= &pcie2_clk.common.hw,
+		[CLK_EMAC0_BUS]		= &emac0_bus_clk.common.hw,
+		[CLK_EMAC0_PTP]		= &emac0_ptp_clk.common.hw,
+		[CLK_EMAC1_BUS]		= &emac1_bus_clk.common.hw,
+		[CLK_EMAC1_PTP]		= &emac1_ptp_clk.common.hw,
+		[CLK_JPG]		= &jpg_clk.common.hw,
+		[CLK_CCIC2PHY]		= &ccic2phy_clk.common.hw,
+		[CLK_CCIC3PHY]		= &ccic3phy_clk.common.hw,
+		[CLK_CSI]		= &csi_clk.common.hw,
+		[CLK_CAMM0]		= &camm0_clk.common.hw,
+		[CLK_CAMM1]		= &camm1_clk.common.hw,
+		[CLK_CAMM2]		= &camm2_clk.common.hw,
+		[CLK_ISP_CPP]		= &isp_cpp_clk.common.hw,
+		[CLK_ISP_BUS]		= &isp_bus_clk.common.hw,
+		[CLK_ISP]		= &isp_clk.common.hw,
+		[CLK_DPU_MCLK]		= &dpu_mclk.common.hw,
+		[CLK_DPU_ESC]		= &dpu_esc_clk.common.hw,
+		[CLK_DPU_BIT]		= &dpu_bit_clk.common.hw,
+		[CLK_DPU_PXCLK]		= &dpu_pxclk.common.hw,
+		[CLK_DPU_HCLK]		= &dpu_hclk.common.hw,
+		[CLK_DPU_SPI]		= &dpu_spi_clk.common.hw,
+		[CLK_DPU_SPI_HBUS]	= &dpu_spi_hbus_clk.common.hw,
+		[CLK_DPU_SPIBUS]	= &dpu_spi_bus_clk.common.hw,
+		[CLK_DPU_SPI_ACLK]	= &dpu_spi_aclk.common.hw,
+		[CLK_V2D]		= &v2d_clk.common.hw,
+		[CLK_EMMC_BUS]		= &emmc_bus_clk.common.hw,
+	},
+	.num = CLK_APMU_NUM
+};
+
+struct spacemit_ccu_data {
+	struct clk_hw_onecell_data *hw_clks;
+	bool need_pll_lock;
+};
+
+struct spacemit_ccu_priv {
+	const struct spacemit_ccu_data *data;
+	struct regmap *base;
+	struct regmap *lock_base;
+};
+
+static int spacemit_ccu_register(struct device *dev,
+				 struct spacemit_ccu_priv *priv)
+{
+	const struct spacemit_ccu_data *data = priv->data;
+	int i, ret;
+
+	for (i = 0; i < data->hw_clks->num; i++) {
+		struct clk_hw *hw = data->hw_clks->hws[i];
+		struct ccu_common *common;
+		const char *name;
+
+		if (!hw)
+			continue;
+
+		common = hw_to_ccu_common(hw);
+		name = hw->init->name;
+
+		common->base		= priv->base;
+		common->lock_base	= priv->lock_base;
+
+		ret = devm_clk_hw_register(dev, hw);
+		if (ret) {
+			dev_err(dev, "Cannot register clock %d - %s\n",
+				i, name);
+			return ret;
+		}
+	}
+
+	return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
+					   data->hw_clks);
+}
+
+static int k1_ccu_probe(struct platform_device *pdev)
+{
+	const struct spacemit_ccu_data *data;
+	struct regmap *base_map, *lock_map;
+	struct device *dev = &pdev->dev;
+	struct spacemit_ccu_priv *priv;
+	struct device_node *parent;
+	int ret;
+
+	data = of_device_get_match_data(dev);
+	if (WARN_ON(!data))
+		return -EINVAL;
+
+	parent   = of_get_parent(dev->of_node);
+	base_map = syscon_node_to_regmap(parent);
+	of_node_put(parent);
+
+	if (IS_ERR(base_map))
+		return dev_err_probe(dev, PTR_ERR(base_map),
+				     "failed to get regmap\n");
+
+	if (data->need_pll_lock) {
+		lock_map = syscon_regmap_lookup_by_phandle(dev->of_node,
+							   "spacemit,mpmu");
+		if (IS_ERR(lock_map))
+			return dev_err_probe(dev, PTR_ERR(lock_map),
+					     "failed to get lock regmap\n");
+	}
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->data	= data;
+	priv->base	= base_map;
+	priv->lock_base	= lock_map;
+
+	ret = spacemit_ccu_register(dev, priv);
+	if (ret)
+		return dev_err_probe(dev, ret, "failed to register clocks\n");
+
+	return 0;
+}
+
+static const struct spacemit_ccu_data k1_ccu_apbs_data = {
+	.need_pll_lock	= true,
+	.hw_clks	= &k1_ccu_apbs_clks,
+};
+
+static const struct spacemit_ccu_data k1_ccu_mpmu_data = {
+	.need_pll_lock	= false,
+	.hw_clks	= &k1_ccu_mpmu_clks,
+};
+
+static const struct spacemit_ccu_data k1_ccu_apbc_data = {
+	.need_pll_lock	= false,
+	.hw_clks	= &k1_ccu_apbc_clks,
+};
+
+static const struct spacemit_ccu_data k1_ccu_apmu_data = {
+	.need_pll_lock	= false,
+	.hw_clks	= &k1_ccu_apmu_clks,
+};
+
+static const struct of_device_id of_k1_ccu_match[] = {
+	{
+		.compatible	= "spacemit,k1-ccu-apbs",
+		.data		= &k1_ccu_apbs_data,
+	},
+	{
+		.compatible	= "spacemit,k1-ccu-mpmu",
+		.data		= &k1_ccu_mpmu_data,
+	},
+	{
+		.compatible	= "spacemit,k1-ccu-apbc",
+		.data		= &k1_ccu_apbc_data,
+	},
+	{
+		.compatible	= "spacemit,k1-ccu-apmu",
+		.data		= &k1_ccu_apmu_data,
+	},
+	{ }
+};
+MODULE_DEVICE_TABLE(of, of_k1_ccu_match);
+
+static struct platform_driver k1_ccu_driver = {
+	.driver = {
+		.name		= "spacemit,k1-ccu",
+		.of_match_table = of_k1_ccu_match,
+	},
+	.probe	= k1_ccu_probe,
+};
+module_platform_driver(k1_ccu_driver);
+
+MODULE_DESCRIPTION("Spacemit K1 CCU driver");
+MODULE_AUTHOR("Haylen Chu <heylenay@outlook.com>");
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/spacemit/ccu_common.h b/drivers/clk/spacemit/ccu_common.h
new file mode 100644
index 000000000000..9910fb69bc9e
--- /dev/null
+++ b/drivers/clk/spacemit/ccu_common.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2024 SpacemiT Technology Co. Ltd
+ * Copyright (c) 2024 Haylen Chu <heylenay@outlook.com>
+ */
+
+#ifndef _CCU_COMMON_H_
+#define _CCU_COMMON_H_
+
+#include <linux/regmap.h>
+
+enum ccu_div_type {
+	CLK_DIV_TYPE_1REG_NOFC_V1 = 0,
+	CLK_DIV_TYPE_1REG_FC_V2,
+	CLK_DIV_TYPE_2REG_NOFC_V3,
+	CLK_DIV_TYPE_2REG_FC_V4,
+	CLK_DIV_TYPE_1REG_FC_DIV_V5,
+	CLK_DIV_TYPE_1REG_FC_MUX_V6,
+};
+
+struct ccu_common {
+	struct regmap *base;
+	struct regmap *lock_base;
+
+	enum ccu_div_type reg_type;
+
+	union {
+		struct {
+			u32 reg_ctrl;
+			u32 reg_sel;
+			u32 reg_xtc;
+			u32 fc;
+		};
+		struct {
+			u32 reg_swcr1;
+			u32 reg_swcr2;
+			u32 reg_swcr3;
+		};
+	};
+
+	unsigned long flags;
+	const char *name;
+	const char * const *parent_names;
+	int num_parents;
+
+	struct clk_hw hw;
+};
+
+static inline struct ccu_common *hw_to_ccu_common(struct clk_hw *hw)
+{
+	return container_of(hw, struct ccu_common, hw);
+}
+
+#define ccu_read(reg, c, val)	regmap_read((c)->base, (c)->reg_##reg, val)
+#define ccu_write(reg, c, val)	regmap_write((c)->base, (c)->reg_##reg, val)
+#define ccu_update(reg, c, mask, val) \
+	regmap_update_bits((c)->base, (c)->reg_##reg, mask, val)
+#define ccu_poll(reg, c, tmp, cond, sleep, timeout) \
+	regmap_read_poll_timeout_atomic((c)->base, (c)->reg_##reg,	\
+					tmp, cond, sleep, timeout)
+
+#endif /* _CCU_COMMON_H_ */
diff --git a/drivers/clk/spacemit/ccu_ddn.c b/drivers/clk/spacemit/ccu_ddn.c
new file mode 100644
index 000000000000..7a68652676ce
--- /dev/null
+++ b/drivers/clk/spacemit/ccu_ddn.c
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Spacemit clock type ddn
+ *
+ * Copyright (c) 2024 SpacemiT Technology Co. Ltd
+ * Copyright (c) 2024 Haylen Chu <heylenay@outlook.com>
+ */
+
+#include <linux/clk-provider.h>
+
+#include "ccu_ddn.h"
+
+/*
+ * It is M/N clock
+ *
+ * Fout from synthesizer can be given from two equations:
+ * numerator/denominator = Fin / (Fout * factor)
+ */
+static void ccu_ddn_disable(struct clk_hw *hw)
+{
+	struct ccu_ddn *ddn = hw_to_ccu_ddn(hw);
+	struct ccu_common *common = &ddn->common;
+
+	if (!ddn->gate)
+		return;
+
+	ccu_update(sel, common, ddn->gate, 0);
+}
+
+static int ccu_ddn_enable(struct clk_hw *hw)
+{
+	struct ccu_ddn *ddn = hw_to_ccu_ddn(hw);
+	struct ccu_common *common = &ddn->common;
+
+	if (!ddn->gate)
+		return 0;
+
+	ccu_update(sel, common, ddn->gate, ddn->gate);
+
+	return 0;
+}
+
+static int ccu_ddn_is_enabled(struct clk_hw *hw)
+{
+	struct ccu_ddn *ddn = hw_to_ccu_ddn(hw);
+	struct ccu_common *common = &ddn->common;
+	u32 tmp;
+
+	if (!ddn->gate)
+		return 1;
+
+	ccu_read(sel, common, &tmp);
+
+	return tmp & ddn->gate;
+}
+
+static long clk_ddn_round_rate(struct clk_hw *hw, unsigned long drate,
+			       unsigned long *prate)
+{
+	struct ccu_ddn *ddn = hw_to_ccu_ddn(hw);
+	struct ccu_ddn_config *params = &ddn->ddn;
+	unsigned long rate = 0, prev_rate;
+	unsigned long result;
+	int i;
+
+	for (i = 0; i < params->tbl_size; i++) {
+		prev_rate = rate;
+		rate = (((*prate / 10000) * params->tbl[i].den) /
+			(params->tbl[i].num * params->info->factor)) * 10000;
+		if (rate > drate)
+			break;
+	}
+
+	if ((i == 0) || (i == params->tbl_size)) {
+		result = rate;
+	} else {
+		if ((drate - prev_rate) > (rate - drate))
+			result = rate;
+		else
+			result = prev_rate;
+	}
+
+	return result;
+}
+
+static unsigned long clk_ddn_recalc_rate(struct clk_hw *hw,
+		unsigned long parent_rate)
+{
+	struct ccu_ddn *ddn = hw_to_ccu_ddn(hw);
+	struct ccu_ddn_config *params = &ddn->ddn;
+	unsigned int val, num, den;
+	unsigned long rate;
+
+	ccu_read(ctrl, &ddn->common, &val);
+
+	num = (val >> params->info->num_shift) & params->info->num_mask;
+	den = (val >> params->info->den_shift) & params->info->den_mask;
+
+	if (!den)
+		return 0;
+
+	rate = ((parent_rate / 10000)  * den) / (num * params->info->factor);
+	rate *= 10000;
+
+	return rate;
+}
+
+/* Configures new clock rate*/
+static int clk_ddn_set_rate(struct clk_hw *hw, unsigned long drate,
+			    unsigned long prate)
+{
+	struct ccu_ddn *ddn = hw_to_ccu_ddn(hw);
+	struct ccu_ddn_config *params = &ddn->ddn;
+	struct ccu_ddn_info *info = params->info;
+	unsigned long prev_rate, rate = 0;
+	int i;
+
+	for (i = 0; i < params->tbl_size; i++) {
+		prev_rate = rate;
+		rate = ((prate / 10000) * params->tbl[i].den) /
+		       (params->tbl[i].num * info->factor);
+		rate *= 10000;
+
+		if (rate > drate)
+			break;
+	}
+
+	if (i > 0)
+		i--;
+
+	ccu_update(ctrl, &ddn->common,
+		   info->num_mask | info->den_mask,
+		   (params->tbl[i].num << info->num_shift) |
+		   (params->tbl[i].den << info->den_shift));
+
+	return 0;
+}
+
+const struct clk_ops spacemit_ccu_ddn_ops = {
+	.disable	= ccu_ddn_disable,
+	.enable		= ccu_ddn_enable,
+	.is_enabled	= ccu_ddn_is_enabled,
+	.recalc_rate	= clk_ddn_recalc_rate,
+	.round_rate	= clk_ddn_round_rate,
+	.set_rate	= clk_ddn_set_rate,
+};
diff --git a/drivers/clk/spacemit/ccu_ddn.h b/drivers/clk/spacemit/ccu_ddn.h
new file mode 100644
index 000000000000..4d369f41404c
--- /dev/null
+++ b/drivers/clk/spacemit/ccu_ddn.h
@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2024 SpacemiT Technology Co. Ltd
+ * Copyright (c) 2024 Haylen Chu <heylenayy@outlook.com>
+ */
+
+#ifndef _CCU_DDN_H_
+#define _CCU_DDN_H_
+
+#include <linux/clk-provider.h>
+
+#include "ccu_common.h"
+
+struct ccu_ddn_tbl {
+	unsigned int num;
+	unsigned int den;
+};
+
+struct ccu_ddn_info {
+	unsigned int factor;
+	unsigned int num_mask;
+	unsigned int den_mask;
+	unsigned int num_shift;
+	unsigned int den_shift;
+};
+
+struct ccu_ddn_config {
+	struct ccu_ddn_info *info;
+	struct ccu_ddn_tbl *tbl;
+	u32 tbl_size;
+};
+
+struct ccu_ddn {
+	struct ccu_ddn_config  ddn;
+	struct ccu_common	common;
+	u32 gate;
+};
+
+#define CCU_DDN_CONFIG(_info, _table)					\
+	{								\
+		.info		= (struct ccu_ddn_info *)_info,		\
+		.tbl		= (struct ccu_ddn_tbl *)&_table,	\
+		.tbl_size	= ARRAY_SIZE(_table),			\
+	}
+
+#define CCU_DDN_INIT(_name, _parent, _flags) \
+	CLK_HW_INIT_HW(_name, &_parent.common.hw,			\
+		       &spacemit_ccu_ddn_ops, _flags)
+
+#define CCU_DDN_DEFINE(_struct, _name, _parent, _info, _table,		\
+		       _reg_ctrl, _flags)				\
+	struct ccu_ddn _struct = {					\
+		.ddn	= CCU_DDN_CONFIG(_info, _table),		\
+		.common = {						\
+			.reg_ctrl = _reg_ctrl,				\
+			.hw.init  = CCU_DDN_INIT(_name, _parent,	\
+						 _flags),		\
+		}							\
+	}
+
+#define CCU_DDN_GATE_DEFINE(_struct, _name, _parent, _info, _table,	\
+			    _reg_ddn, _reg_gate, _gate_mask, _flags)	\
+	struct ccu_ddn _struct = {					\
+		.ddn	= CCU_DDN_CONFIG(_info, _table),		\
+		.common = {						\
+			.reg_ctrl	= _reg_ddn,			\
+			.reg_sel	= _reg_gate,			\
+			.hw.init = CLK_HW_INIT(_name, _parent,		\
+					       &spacemit_ccu_ddn_ops,	\
+					       _flags),			\
+		}							\
+		.gate	= _gate_mask,					\
+	}
+
+
+static inline struct ccu_ddn *hw_to_ccu_ddn(struct clk_hw *hw)
+{
+	struct ccu_common *common = hw_to_ccu_common(hw);
+
+	return container_of(common, struct ccu_ddn, common);
+}
+
+extern const struct clk_ops spacemit_ccu_ddn_ops;
+
+#endif
diff --git a/drivers/clk/spacemit/ccu_mix.c b/drivers/clk/spacemit/ccu_mix.c
new file mode 100644
index 000000000000..de343405fcc7
--- /dev/null
+++ b/drivers/clk/spacemit/ccu_mix.c
@@ -0,0 +1,296 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Spacemit clock type mix(div/mux/gate/factor)
+ *
+ * Copyright (c) 2024 SpacemiT Technology Co. Ltd
+ * Copyright (c) 2024 Haylen Chu <heylenay@outlook.com>
+ */
+
+#include <linux/clk-provider.h>
+
+#include "ccu_mix.h"
+
+#define MIX_TIMEOUT	10000
+
+#define mix_hwparam_in_sel(c) \
+	((c)->reg_type == CLK_DIV_TYPE_2REG_NOFC_V3 || \
+	 (c)->reg_type == CLK_DIV_TYPE_2REG_FC_V4)
+
+static void ccu_mix_disable(struct clk_hw *hw)
+{
+	struct ccu_mix *mix = hw_to_ccu_mix(hw);
+	struct ccu_common *common = &mix->common;
+	struct ccu_gate_config *gate = mix->gate;
+
+	if (!gate)
+		return;
+
+	if (mix_hwparam_in_sel(common))
+		ccu_update(sel, common, gate->gate_mask, gate->val_disable);
+	else
+		ccu_update(ctrl, common, gate->gate_mask, gate->val_disable);
+}
+
+static int ccu_mix_enable(struct clk_hw *hw)
+{
+	struct ccu_mix *mix = hw_to_ccu_mix(hw);
+	struct ccu_common *common = &mix->common;
+	struct ccu_gate_config *gate = mix->gate;
+	u32 val_enable, mask;
+	u32 tmp;
+
+	if (!gate)
+		return 0;
+
+	val_enable	= gate->val_enable;
+	mask		= gate->gate_mask;
+
+	if (mix_hwparam_in_sel(common))
+		ccu_update(sel, common, mask, val_enable);
+	else
+		ccu_update(ctrl, common, mask, val_enable);
+
+	if (common->reg_type == CLK_DIV_TYPE_2REG_NOFC_V3 ||
+	    common->reg_type == CLK_DIV_TYPE_2REG_FC_V4)
+		return ccu_poll(sel, common, tmp, (tmp & mask) == val_enable,
+				10, MIX_TIMEOUT);
+	else
+		return ccu_poll(ctrl, common, tmp, (tmp & mask) == val_enable,
+				10, MIX_TIMEOUT);
+}
+
+static int ccu_mix_is_enabled(struct clk_hw *hw)
+{
+	struct ccu_mix *mix = hw_to_ccu_mix(hw);
+	struct ccu_common *common = &mix->common;
+	struct ccu_gate_config *gate = mix->gate;
+	u32 tmp;
+
+	if (!gate)
+		return 1;
+
+	if (mix_hwparam_in_sel(common))
+		ccu_read(sel, common, &tmp);
+	else
+		ccu_read(ctrl, common, &tmp);
+
+	return (tmp & gate->gate_mask) == gate->val_enable;
+}
+
+static unsigned long ccu_mix_recalc_rate(struct clk_hw *hw,
+					unsigned long parent_rate)
+{
+	struct ccu_mix *mix = hw_to_ccu_mix(hw);
+	struct ccu_common *common = &mix->common;
+	struct ccu_div_config *div = mix->div;
+	unsigned long val;
+	u32 reg;
+
+	if (!div) {
+		if (mix->factor)
+			return parent_rate * mix->factor->mul / mix->factor->div;
+
+		return parent_rate;
+	}
+
+	if (mix_hwparam_in_sel(common))
+		ccu_read(sel, common, &reg);
+	else
+		ccu_read(ctrl, common, &reg);
+
+	val = reg >> div->shift;
+	val &= (1 << div->width) - 1;
+
+	val = divider_recalc_rate(hw, parent_rate, val, div->table,
+				  div->flags, div->width);
+
+	return val;
+}
+
+
+static int ccu_mix_trigger_fc(struct clk_hw *hw)
+{
+	struct ccu_mix *mix = hw_to_ccu_mix(hw);
+	struct ccu_common *common = &mix->common;
+	unsigned int val = 0;
+	int ret = 0;
+
+	if (common->reg_type == CLK_DIV_TYPE_1REG_FC_V2 ||
+	    common->reg_type == CLK_DIV_TYPE_2REG_FC_V4 ||
+	    common->reg_type == CLK_DIV_TYPE_1REG_FC_DIV_V5 ||
+	    common->reg_type == CLK_DIV_TYPE_1REG_FC_MUX_V6) {
+		ccu_update(ctrl, common, common->fc, common->fc);
+
+		ret = ccu_poll(ctrl, common, val, !(val & common->fc),
+			       5, MIX_TIMEOUT);
+	}
+
+	return ret;
+}
+
+static int ccu_mix_determine_rate(struct clk_hw *hw,
+				  struct clk_rate_request *req)
+{
+	return 0;
+}
+
+static unsigned long
+ccu_mix_calc_best_rate(struct clk_hw *hw, unsigned long rate, u32 *mux_val,
+		       u32 *div_val)
+{
+	struct ccu_mix *mix = hw_to_ccu_mix(hw);
+	struct ccu_common *common = &mix->common;
+	struct ccu_div_config *div = mix->div ? mix->div : NULL;
+	struct clk_hw *parent;
+	unsigned long parent_rate = 0, best_rate = 0;
+	u32 i, j, div_max;
+
+	for (i = 0; i < common->num_parents; i++) {
+		parent = clk_hw_get_parent_by_index(hw, i);
+		if (!parent)
+			continue;
+
+		parent_rate = clk_hw_get_rate(parent);
+
+		if (div)
+			div_max = 1 << div->width;
+		else
+			div_max = 1;
+
+		for (j = 1; j <= div_max; j++) {
+			if (abs(parent_rate/j - rate) < abs(best_rate - rate)) {
+				best_rate = DIV_ROUND_UP_ULL(parent_rate, j);
+				*mux_val = i;
+				*div_val = j - 1;
+			}
+		}
+	}
+
+	return best_rate;
+}
+
+static int ccu_mix_set_rate(struct clk_hw *hw, unsigned long rate,
+			   unsigned long parent_rate)
+{
+	struct ccu_mix *mix = hw_to_ccu_mix(hw);
+	struct ccu_common *common = &mix->common;
+	struct ccu_div_config *div = mix->div;
+	struct ccu_mux_config *mux = mix->mux;
+	u32 cur_mux, cur_div, mux_val = 0, div_val = 0;
+	unsigned long best_rate = 0;
+	int ret = 0, tmp = 0;
+
+	if (!div && !mux)
+		return 0;
+
+	best_rate = ccu_mix_calc_best_rate(hw, rate, &mux_val, &div_val);
+
+	if (mix_hwparam_in_sel(common))
+		ccu_read(sel, common, &tmp);
+	else
+		ccu_read(ctrl, common, &tmp);
+
+	if (mux) {
+		cur_mux = tmp >> mux->shift;
+		cur_mux &= (1 << mux->width) - 1;
+
+		if (cur_mux != mux_val)
+			clk_hw_set_parent(hw, clk_hw_get_parent_by_index(hw, mux_val));
+	}
+
+	if (div) {
+		cur_div = tmp >> div->shift;
+		cur_div &= (1 << div->width) - 1;
+
+		if (cur_div == div_val)
+			return 0;
+	} else {
+		return 0;
+	}
+
+	tmp = GENMASK(div->width + div->shift - 1, div->shift);
+
+	if (mix_hwparam_in_sel(common))
+		ccu_update(sel, common, tmp, div_val << div->shift);
+	else
+		ccu_update(ctrl, common, tmp, div_val << div->shift);
+
+	if (common->reg_type == CLK_DIV_TYPE_1REG_FC_V2 ||
+	    common->reg_type == CLK_DIV_TYPE_2REG_FC_V4 ||
+	    common->reg_type == CLK_DIV_TYPE_1REG_FC_DIV_V5)
+		ret = ccu_mix_trigger_fc(hw);
+
+	return ret;
+}
+
+static u8 ccu_mix_get_parent(struct clk_hw *hw)
+{
+	struct ccu_mix *mix = hw_to_ccu_mix(hw);
+	struct ccu_common *common = &mix->common;
+	struct ccu_mux_config *mux = mix->mux;
+	u32 reg;
+	u8 parent;
+
+	if (!mux)
+		return 0;
+
+	if (mix_hwparam_in_sel(common))
+		ccu_read(sel, common, &reg);
+	else
+		ccu_read(ctrl, common, &reg);
+
+	parent = reg >> mux->shift;
+	parent &= (1 << mux->width) - 1;
+
+	if (mux->table) {
+		int num_parents = clk_hw_get_num_parents(&common->hw);
+		int i;
+
+		for (i = 0; i < num_parents; i++)
+			if (mux->table[i] == parent)
+				return i;
+	}
+
+	return parent;
+}
+
+static int ccu_mix_set_parent(struct clk_hw *hw, u8 index)
+{
+	struct ccu_mix *mix = hw_to_ccu_mix(hw);
+	struct ccu_common *common = &mix->common;
+	struct ccu_mux_config *mux = mix->mux;
+	int ret = 0;
+	u32 mask;
+
+	if (!mux)
+		return 0;
+
+	if (mux->table)
+		index = mux->table[index];
+
+	mask = GENMASK(mux->width + mux->shift - 1, mux->shift);
+
+	if (mix_hwparam_in_sel(common))
+		ccu_update(sel, common, mask, index << mux->shift);
+	else
+		ccu_update(ctrl, common, mask, index << mux->shift);
+
+	if (common->reg_type == CLK_DIV_TYPE_1REG_FC_V2 ||
+	    common->reg_type == CLK_DIV_TYPE_2REG_FC_V4 ||
+	    common->reg_type == CLK_DIV_TYPE_1REG_FC_MUX_V6)
+		ret = ccu_mix_trigger_fc(hw);
+
+	return ret;
+}
+
+const struct clk_ops spacemit_ccu_mix_ops = {
+	.disable	 = ccu_mix_disable,
+	.enable		 = ccu_mix_enable,
+	.is_enabled	 = ccu_mix_is_enabled,
+	.get_parent	 = ccu_mix_get_parent,
+	.set_parent	 = ccu_mix_set_parent,
+	.determine_rate  = ccu_mix_determine_rate,
+	.recalc_rate	 = ccu_mix_recalc_rate,
+	.set_rate	 = ccu_mix_set_rate,
+};
+
diff --git a/drivers/clk/spacemit/ccu_mix.h b/drivers/clk/spacemit/ccu_mix.h
new file mode 100644
index 000000000000..c7d91e1c03fd
--- /dev/null
+++ b/drivers/clk/spacemit/ccu_mix.h
@@ -0,0 +1,336 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2024 SpacemiT Technology Co. Ltd
+ * Copyright (c) 2024 Haylen Chu <heylenay@outlook.com>
+ */
+
+#ifndef _CCU_MIX_H_
+#define _CCU_MIX_H_
+
+#include <linux/clk-provider.h>
+
+#include "ccu_common.h"
+
+struct ccu_gate_config {
+	u32 gate_mask;
+	u32 val_enable;
+	u32 val_disable;
+	u32 flags;
+};
+
+struct ccu_factor_config {
+	u32 div;
+	u32 mul;
+};
+
+struct ccu_mux_config {
+	const u8 *table;
+	u32 flags;
+	u8 shift;
+	u8 width;
+};
+
+struct ccu_div_config {
+	struct clk_div_table *table;
+	u32 max;
+	u32 offset;
+	u32 flags;
+	u8 shift;
+	u8 width;
+};
+
+struct ccu_mix {
+	struct ccu_factor_config *factor;
+	struct ccu_gate_config *gate;
+	struct ccu_div_config *div;
+	struct ccu_mux_config *mux;
+	struct ccu_common common;
+};
+
+#define CCU_GATE_INIT(_gate_mask, _val_enable, _val_disable, _flags)		\
+	(&(struct ccu_gate_config) {						\
+		.gate_mask   = _gate_mask,					\
+		.val_enable  = _val_enable,					\
+		.val_disable = _val_disable,					\
+		.flags	     = _flags,						\
+	})
+
+#define CCU_FACTOR_INIT(_div, _mul)					\
+	(&(struct ccu_factor_config) {					\
+		.div = _div,						\
+		.mul = _mul,						\
+	})
+
+
+#define CCU_MUX_INIT(_shift, _width, _table, _flags)			\
+	(&(struct ccu_mux_config) {					\
+		.shift	= _shift,					\
+		.width	= _width,					\
+		.table	= _table,					\
+		.flags	= _flags,					\
+	})
+
+#define CCU_DIV_INIT(_shift, _width, _table, _flags)			\
+	(&(struct ccu_div_config) {					\
+		.shift	= _shift,					\
+		.width	= _width,					\
+		.flags	= _flags,					\
+		.table	= _table,					\
+	})
+
+#define CCU_PARENT_HW(_parent)		{ .hw = &_parent.common.hw }
+#define CCU_PARENT_NAME(_name)		{ .fw_name = #_name }
+
+#define CCU_MIX_INITHW(_name, _parent, _flags)				\
+	(&(struct clk_init_data) {					\
+		.flags		= _flags,				\
+		.name		= _name,				\
+		.parent_data	= (const struct clk_parent_data[])	\
+					{ _parent },			\
+		.num_parents	= 1,					\
+		.ops		= &spacemit_ccu_mix_ops,		\
+	})
+
+#define CCU_MIX_INITHW_PARENTS(_name, _parents, _flags)			\
+	CLK_HW_INIT_PARENTS_DATA(_name, _parents,			\
+				 &spacemit_ccu_mix_ops, _flags)
+
+#define CCU_GATE_DEFINE(_struct, _name, _parent, _reg, _gate_mask,	\
+			 _val_enable, _val_disable, _flags)		\
+struct ccu_mix _struct = {						\
+	.gate	= CCU_GATE_INIT(_gate_mask, _val_enable,		\
+				_val_disable, 0),			\
+	.common	= {							\
+		.reg_ctrl	= _reg,					\
+		.name		= _name,				\
+		.num_parents	= 1,					\
+		.hw.init	= CCU_MIX_INITHW(_name, _parent,	\
+						 _flags),		\
+	}								\
+}
+
+#define CCU_FACTOR_DEFINE(_struct, _name, _parent, _div, _mul)		\
+struct ccu_mix _struct = {						\
+	.factor	= CCU_FACTOR_INIT(_div, _mul),				\
+	.common = {							\
+		.name		= _name,				\
+		.num_parents	= 1,					\
+		.hw.init	= CCU_MIX_INITHW(_name, _parent, 0),	\
+	}								\
+}
+
+#define CCU_MUX_DEFINE(_struct, _name, _parents, _reg, _shift, _width,	\
+		       _flags)						\
+struct ccu_mix _struct = {						\
+	.mux	= CCU_MUX_INIT(_shift, _width, NULL, 0),		\
+	.common = {							\
+		.reg_ctrl	= _reg,					\
+		.name		= _name,				\
+		.num_parents	= ARRAY_SIZE(_parents),			\
+		.hw.init = CCU_MIX_INITHW_PARENTS(_name, _parents,	\
+						  _flags),		\
+	}								\
+}
+
+#define CCU_DIV_DEFINE(_struct, _name, _parent, _reg, _shift, _width,	\
+		       _flags)						\
+struct ccu_mix _struct = {						\
+	.div	= CCU_DIV_INIT(_shift, _width, NULL, 0),		\
+	.common = {							\
+		.reg_ctrl	= _reg,					\
+		.name		= _name,				\
+		.num_parents	= 1,					\
+		.hw.init = CCU_MIX_INITHW(_name, _parent, _flags)	\
+	}								\
+}
+
+#define CCU_GATE_FACTOR_DEFINE(_struct, _name, _parent, _reg,		\
+			       _gate_mask, _val_enable, _val_disable,	\
+			       _div, _mul, _flags)			\
+struct ccu_mix _struct = {						\
+	.gate	= CCU_GATE_INIT(_gate_mask, _val_enable,		\
+				_val_disable, 0),			\
+	.factor	= CCU_FACTOR_INIT(_div, _mul),				\
+	.common = {							\
+		.reg_ctrl	= _reg,					\
+		.name		= _name,				\
+		.num_parents	= 1,					\
+		.hw.init = CCU_MIX_INITHW(_name, _parent, _flags)	\
+	}								\
+}
+
+
+#define CCU_MUX_GATE_DEFINE(_struct, _name, _parents, _reg, _shift,	\
+			    _width, _gate_mask, _val_enable,		\
+			    _val_disable, _flags)			\
+struct ccu_mix _struct = {						\
+	.gate	= CCU_GATE_INIT(_gate_mask, _val_enable,		\
+				_val_disable, 0),			\
+	.mux	= CCU_MUX_INIT(_shift, _width, NULL, 0),		\
+	.common = {							\
+		.reg_ctrl	= _reg,					\
+		.name		= _name,				\
+		.num_parents	= ARRAY_SIZE(_parents),			\
+		.hw.init = CCU_MIX_INITHW_PARENTS(_name, _parents,	\
+						  _flags),		\
+	}								\
+}
+
+#define CCU_DIV_GATE_DEFINE(_struct, _name, _parent, _reg, _shift,	\
+			    _width, _gate_mask, _val_enable,		\
+			    _val_disable, _flags)			\
+struct ccu_mix _struct = {						\
+	.gate	= CCU_GATE_INIT(_gate_mask, _val_enable,		\
+				_val_disable, 0),			\
+	.div	= CCU_DIV_INIT(_shift, _width, NULL, 0),		\
+	.common = {							\
+		.reg_ctrl	= _reg,					\
+		.name		= _name,				\
+		.num_parents	= 1,					\
+		.hw.init	= CCU_MIX_INITHW(_name, _parent,	\
+						 _flags),		\
+	}								\
+}
+
+
+#define CCU_DIV_MUX_GATE_DEFINE(_struct, _name, _parents,  _reg_ctrl,	\
+				_mshift, _mwidth, _muxshift, _muxwidth,	\
+				_gate_mask, _val_enable, _val_disable,	\
+				_flags)					\
+struct ccu_mix _struct = {						\
+	.gate	= CCU_GATE_INIT(_gate_mask, _val_enable,		\
+				_val_disable, 0),			\
+	.div	= CCU_DIV_INIT(_mshift, _mwidth, NULL, 0),		\
+	.mux	= CCU_MUX_INIT(_muxshift, _muxwidth, NULL, 0),		\
+	.common	= {							\
+		.reg_ctrl	= _reg_ctrl,				\
+		.name		= _name,				\
+		.num_parents	= ARRAY_SIZE(_parents),			\
+		.hw.init = CCU_MIX_INITHW_PARENTS(_name, _parents,	\
+						  _flags),		\
+	},								\
+}
+
+#define CCU_DIV2_FC_MUX_GATE_DEFINE(_struct, _name, _parents,		\
+				    _reg_ctrl, _reg_sel, _mshift,	\
+				    _mwidth, _fc, _muxshift, _muxwidth,	\
+				    _gate_mask, _val_enable,		\
+				    _val_disable, _flags)		\
+struct ccu_mix _struct = {						\
+	.gate	= CCU_GATE_INIT(_gate_mask, _val_enable,		\
+				_val_disable, 0),			\
+	.div	= CCU_DIV_INIT(_mshift, _mwidth, NULL, 0),		\
+	.mux	= CCU_MUX_INIT(_muxshift, _muxwidth, NULL, 0),		\
+	.common = {							\
+	    .reg_type = CLK_DIV_TYPE_2REG_FC_V4,			\
+		.reg_ctrl	= _reg_ctrl,				\
+		.reg_sel	= _reg_sel,				\
+		.fc		= _fc,					\
+		.name		= _name,				\
+		.num_parents	= ARRAY_SIZE(_parents),			\
+		.hw.init = CCU_MIX_INITHW_PARENTS(_name, _parents,	\
+						  _flags),		\
+	},								\
+}
+
+
+#define CCU_DIV_FC_MUX_GATE_DEFINE(_struct, _name, _parents, _reg_ctrl,	\
+				   _mshift, _mwidth, _fc, _muxshift,	\
+				   _muxwidth, _gate_mask, _val_enable,	\
+				   _val_disable, _flags)		\
+struct ccu_mix _struct = {						\
+	.gate	= CCU_GATE_INIT(_gate_mask, _val_enable,		\
+				_val_disable, 0),			\
+	.div	= CCU_DIV_INIT(_mshift, _mwidth, NULL, 0),		\
+	.mux	= CCU_MUX_INIT(_muxshift, _muxwidth, NULL, 0),		\
+	.common = {							\
+		.reg_type	= CLK_DIV_TYPE_1REG_FC_V2,		\
+		.reg_ctrl	= _reg_ctrl,				\
+		.fc		= _fc,					\
+		.name		= _name,				\
+		.num_parents	= ARRAY_SIZE(_parents),			\
+		.hw.init = CCU_MIX_INITHW_PARENTS(_name, _parents,	\
+						  _flags),		\
+	},								\
+}
+
+#define CCU_DIV_MFC_MUX_GATE_DEFINE(_struct, _name, _parents,		\
+				    _reg_ctrl, _mshift, _mwidth, _fc,	\
+				    _muxshift, _muxwidth, _gate_mask,	\
+				    _val_enable, _val_disable, _flags)	\
+struct ccu_mix _struct = {						\
+	.gate	= CCU_GATE_INIT(_gate_mask, _val_enable,		\
+				_val_disable, 0),			\
+	.div	= CCU_DIV_INIT(_mshift, _mwidth, NULL, 0),		\
+	.mux	= CCU_MUX_INIT(_muxshift, _muxwidth, NULL, 0),		\
+	.common = {							\
+		.reg_type = CLK_DIV_TYPE_1REG_FC_MUX_V6,		\
+		.reg_ctrl	= _reg_ctrl,				\
+		.fc		= _fc,					\
+		.name		= _name,				\
+		.num_parents	= ARRAY_SIZE(_parents),			\
+		.hw.init = CCU_MIX_INITHW_PARENTS(_name, _parents,	\
+						  _flags),		\
+	},								\
+}
+
+#define CCU_DIV_FC_WITH_GATE_DEFINE(_struct, _name, _parent, _reg_ctrl,	\
+				    _mshift, _mwidth, _fc, _gate_mask,	\
+				    _val_enable, _val_disable, _flags)	\
+struct ccu_mix _struct = {						\
+	.gate	= CCU_GATE_INIT(_gate_mask, _val_enable,		\
+				_val_disable, 0),			\
+	.div	= CCU_DIV_INIT(_mshift, _mwidth, NULL, 0),		\
+	.common = {							\
+		.reg_type = CLK_DIV_TYPE_1REG_FC_V2,			\
+		.reg_ctrl	= _reg_ctrl,				\
+		.fc		= _fc,					\
+		.name		= _name,				\
+		.num_parents	= 1,					\
+		.hw.init	= CCU_MIXINITHW(_name, _parent,		\
+						_flags),		\
+	},								\
+}
+
+#define CCU_DIV_FC_MUX_DEFINE(_struct, _name, _parents, _reg_ctrl,	\
+			      _mshift, _mwidth, _fc, _muxshift,		\
+			      _muxwidth, _flags)			\
+struct ccu_mix _struct = {						\
+	.div	= CCU_DIV_INIT(_mshift, _mwidth, NULL, 0),		\
+	.mux	= CCU_MUX_INIT(_muxshift, _muxwidth, NULL, 0),		\
+	.common = {							\
+		.reg_type	= CLK_DIV_TYPE_1REG_FC_V2,		\
+		.reg_ctrl	= _reg_ctrl,				\
+		.fc		= _fc,					\
+		.name		= _name,				\
+		.num_parents	= ARRAY_SIZE(_parents),			\
+		.hw.init = CCU_MIX_INITHW_PARENTS(_name, _parents,	\
+						  _flags),		\
+	},								\
+}
+
+#define CCU_MUX_FC_DEFINE(_struct, _name, _parents, _reg_ctrl, _fc,	\
+			  _muxshift, _muxwidth, _flags)			\
+struct ccu_mix _struct = {						\
+	.mux	= CCU_MUX_INIT(_muxshift, _muxwidth, NULL, 0),		\
+	.common = {							\
+		.reg_type	= CLK_DIV_TYPE_1REG_FC_V2,		\
+		.reg_ctrl	= _reg_ctrl,				\
+		.fc		= _fc,					\
+		.name		= _name,				\
+		.num_parents	= ARRAY_SIZE(_parents),			\
+		.hw.init = CCU_MIX_INITHW_PARENTS(_name, _parents,	\
+						  _flags)		\
+	},								\
+}
+
+static inline struct ccu_mix *hw_to_ccu_mix(struct clk_hw *hw)
+{
+	struct ccu_common *common = hw_to_ccu_common(hw);
+
+	return container_of(common, struct ccu_mix, common);
+}
+
+extern const struct clk_ops spacemit_ccu_mix_ops;
+
+#endif /* _CCU_DIV_H_ */
diff --git a/drivers/clk/spacemit/ccu_pll.c b/drivers/clk/spacemit/ccu_pll.c
new file mode 100644
index 000000000000..cf6e547f073b
--- /dev/null
+++ b/drivers/clk/spacemit/ccu_pll.c
@@ -0,0 +1,198 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Spacemit clock type pll
+ *
+ * Copyright (c) 2024 SpacemiT Technology Co. Ltd
+ * Copyright (c) 2024 Haylen Chu <heylenay@outlook.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/regmap.h>
+
+#include "ccu_common.h"
+#include "ccu_pll.h"
+
+#define PLL_MIN_FREQ	600000000
+#define PLL_MAX_FREQ	3400000000
+#define PLL_DELAY_TIME	3000
+
+#define PLL_SWCR1_REG5_OFF	0
+#define PLL_SWCR1_REG5_MASK	GENMASK(7, 0)
+#define PLL_SWCR1_REG6_OFF	8
+#define PLL_SWCR1_REG6_MASK	GENMASK(15, 8)
+#define PLL_SWCR1_REG7_OFF	16
+#define PLL_SWCR1_REG7_MASK	GENMASK(23, 16)
+#define PLL_SWCR1_REG8_OFF	24
+#define PLL_SWCR1_REG8_MASK	GENMASK(31, 24)
+
+#define PLL_SWCR2_DIVn_EN(n)	BIT(n + 1)
+#define PLL_SWCR2_ATEST_EN	BIT(12)
+#define PLL_SWCR2_CKTEST_EN	BIT(13)
+#define PLL_SWCR2_DTEST_EN	BIT(14)
+
+#define PLL_SWCR3_DIV_FRC_OFF	0
+#define PLL_SWCR3_DIV_FRC_MASK	GENMASK(23, 0)
+#define PLL_SWCR3_DIV_INT_OFF	24
+#define PLL_SWCR3_DIV_INT_MASK	GENMASK(30, 24)
+#define PLL_SWCR3_EN		BIT(31)
+
+static int ccu_pll_is_enabled(struct clk_hw *hw)
+{
+	struct ccu_pll *p = hw_to_ccu_pll(hw);
+	u32 tmp;
+
+	ccu_read(swcr3, &p->common, &tmp);
+
+	return tmp & PLL_SWCR3_EN;
+}
+
+/* frequency unit Mhz, return pll vco freq */
+static unsigned long __get_vco_freq(struct clk_hw *hw)
+{
+	unsigned int reg5, reg6, reg7, reg8, size, i;
+	unsigned int div_int, div_frc;
+	struct ccu_pll_rate_tbl *freq_pll_regs_table;
+	struct ccu_pll *p = hw_to_ccu_pll(hw);
+	struct ccu_common *common = &p->common;
+	u32 tmp;
+
+	ccu_read(swcr1, common, &tmp);
+	reg5 = (tmp & PLL_SWCR1_REG5_MASK) >> PLL_SWCR1_REG5_OFF;
+	reg6 = (tmp & PLL_SWCR1_REG6_MASK) >> PLL_SWCR1_REG6_OFF;
+	reg7 = (tmp & PLL_SWCR1_REG7_MASK) >> PLL_SWCR1_REG7_OFF;
+	reg8 = (tmp & PLL_SWCR1_REG8_MASK) >> PLL_SWCR1_REG8_OFF;
+
+	ccu_read(swcr3, common, &tmp);
+	div_int = (tmp & PLL_SWCR3_DIV_INT_MASK) >> PLL_SWCR3_DIV_INT_OFF;
+	div_frc = (tmp & PLL_SWCR3_DIV_FRC_MASK) >> PLL_SWCR3_DIV_FRC_OFF;
+
+	freq_pll_regs_table = p->pll.rate_tbl;
+	size = p->pll.tbl_size;
+
+	for (i = 0; i < size; i++)
+		if ((freq_pll_regs_table[i].reg5 == reg5) &&
+		    (freq_pll_regs_table[i].reg6 == reg6) &&
+		    (freq_pll_regs_table[i].reg7 == reg7) &&
+		    (freq_pll_regs_table[i].reg8 == reg8) &&
+		    (freq_pll_regs_table[i].div_int == div_int) &&
+		    (freq_pll_regs_table[i].div_frac == div_frc))
+			return freq_pll_regs_table[i].rate;
+
+	WARN_ON_ONCE(1);
+
+	return 0;
+}
+
+static int ccu_pll_enable(struct clk_hw *hw)
+{
+	struct ccu_pll *p = hw_to_ccu_pll(hw);
+	struct ccu_common *common = &p->common;
+	unsigned int tmp;
+	int ret;
+
+	if (ccu_pll_is_enabled(hw))
+		return 0;
+
+	ccu_update(swcr3, common, PLL_SWCR3_EN, PLL_SWCR3_EN);
+
+	/* check lock status */
+	ret = regmap_read_poll_timeout_atomic(common->lock_base,
+					      p->pll.reg_lock,
+					      tmp,
+					      tmp & p->pll.lock_enable_bit,
+					      5, PLL_DELAY_TIME);
+
+	return ret;
+}
+
+static void ccu_pll_disable(struct clk_hw *hw)
+{
+	struct ccu_pll *p = hw_to_ccu_pll(hw);
+	struct ccu_common *common = &p->common;
+
+	ccu_update(swcr3, common, PLL_SWCR3_EN, 0);
+}
+
+/*
+ * pll rate change requires sequence:
+ * clock off -> change rate setting -> clock on
+ * This function doesn't really change rate, but cache the config
+ */
+static int ccu_pll_set_rate(struct clk_hw *hw, unsigned long rate,
+			       unsigned long parent_rate)
+{
+	struct ccu_pll *p = hw_to_ccu_pll(hw);
+	struct ccu_common *common = &p->common;
+	struct ccu_pll_config *params = &p->pll;
+	struct ccu_pll_rate_tbl *entry;
+	unsigned long old_rate;
+	bool found = false;
+	u32 mask, val;
+	int i;
+
+	if (ccu_pll_is_enabled(hw)) {
+		pr_err("%s %s is enabled, ignore the setrate!\n",
+		       __func__, __clk_get_name(hw->clk));
+		return 0;
+	}
+
+	old_rate = __get_vco_freq(hw);
+
+	for (i = 0; i < params->tbl_size; i++) {
+		if (rate == params->rate_tbl[i].rate) {
+			found = true;
+			entry = &params->rate_tbl[i];
+			break;
+		}
+	}
+	WARN_ON_ONCE(!found);
+
+	mask = PLL_SWCR1_REG5_MASK | PLL_SWCR1_REG6_MASK;
+	mask |= PLL_SWCR1_REG7_MASK | PLL_SWCR1_REG8_MASK;
+	val |= entry->reg5 << PLL_SWCR1_REG5_OFF;
+	val |= entry->reg6 << PLL_SWCR1_REG6_OFF;
+	val |= entry->reg7 << PLL_SWCR1_REG7_OFF;
+	val |= entry->reg8 << PLL_SWCR1_REG8_OFF;
+	ccu_update(swcr1, common, mask, val);
+
+	mask = PLL_SWCR3_DIV_INT_MASK | PLL_SWCR3_DIV_FRC_MASK;
+	val = entry->div_int << PLL_SWCR3_DIV_INT_OFF;
+	val |= entry->div_frac << PLL_SWCR3_DIV_FRC_OFF;
+	ccu_update(swcr3, common, mask, val);
+
+	return 0;
+}
+
+static unsigned long ccu_pll_recalc_rate(struct clk_hw *hw,
+					 unsigned long parent_rate)
+{
+	return __get_vco_freq(hw);
+}
+
+static long ccu_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+			       unsigned long *prate)
+{
+	struct ccu_pll *p = hw_to_ccu_pll(hw);
+	struct ccu_pll_config *params = &p->pll;
+	unsigned long max_rate = 0;
+	unsigned int i;
+
+	for (i = 0; i < params->tbl_size; i++) {
+		if (params->rate_tbl[i].rate <= rate) {
+			if (max_rate < params->rate_tbl[i].rate)
+				max_rate = params->rate_tbl[i].rate;
+		}
+	}
+
+	return MAX(max_rate, PLL_MIN_FREQ);
+}
+
+const struct clk_ops spacemit_ccu_pll_ops = {
+	.enable		= ccu_pll_enable,
+	.disable	= ccu_pll_disable,
+	.set_rate	= ccu_pll_set_rate,
+	.recalc_rate	= ccu_pll_recalc_rate,
+	.round_rate	= ccu_pll_round_rate,
+	.is_enabled	= ccu_pll_is_enabled,
+};
+
diff --git a/drivers/clk/spacemit/ccu_pll.h b/drivers/clk/spacemit/ccu_pll.h
new file mode 100644
index 000000000000..a2252e79ff4a
--- /dev/null
+++ b/drivers/clk/spacemit/ccu_pll.h
@@ -0,0 +1,80 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2024 SpacemiT Technology Co. Ltd
+ * Copyright (c) 2024 Haylen Chu <heylenay@outlook.com>
+ */
+
+#ifndef _CCU_PLL_H_
+#define _CCU_PLL_H_
+
+#include <linux/clk-provider.h>
+
+#include "ccu_common.h"
+
+struct ccu_pll_rate_tbl {
+	unsigned long long rate;
+	u32 reg5;
+	u32 reg6;
+	u32 reg7;
+	u32 reg8;
+	unsigned int div_int;
+	unsigned int div_frac;
+};
+
+struct ccu_pll_config {
+	struct ccu_pll_rate_tbl *rate_tbl;
+	u32 tbl_size;
+	u32 reg_lock;
+	u32 lock_enable_bit;
+};
+
+#define CCU_PLL_RATE(_rate, _reg5, _reg6, _reg7, _reg8, _div_int, _div_frac) \
+	{									\
+		.rate		= (_rate),					\
+		.reg5		= (_reg5),					\
+		.reg6		= (_reg6),					\
+		.reg7		= (_reg7),					\
+		.reg8		= (_reg8),					\
+		.div_int	= (_div_int),				\
+		.div_frac	= (_div_frac),				\
+	}
+
+struct ccu_pll {
+	struct ccu_pll_config	pll;
+	struct ccu_common	common;
+};
+
+#define CCU_PLL_CONFIG(_table, _reg_lock, _lock_enable_bit) \
+	{									\
+		.rate_tbl	 = (struct ccu_pll_rate_tbl *)&(_table),	\
+		.tbl_size	 = ARRAY_SIZE(_table),				\
+		.reg_lock	 = (_reg_lock),					\
+		.lock_enable_bit = (_lock_enable_bit),				\
+	}
+
+#define CCU_PLL_HWINIT(_name, _flags) \
+	CLK_HW_INIT_NO_PARENT(_name, &spacemit_ccu_pll_ops, _flags)
+
+#define CCU_PLL_DEFINE(_struct, _name, _table, _reg_swcr1, _reg_swcr2,	\
+		       _reg_swcr3, _reg_lock, _lock_enable_bit, _flags)		\
+										\
+	struct ccu_pll _struct = {						\
+		.pll	= CCU_PLL_CONFIG(_table, _reg_lock, _lock_enable_bit),	\
+		.common = {							\
+			.reg_swcr1	= _reg_swcr1,				\
+			.reg_swcr2	= _reg_swcr2,				\
+			.reg_swcr3	= _reg_swcr3,				\
+			.hw.init	= CCU_PLL_HWINIT(_name, _flags)		\
+		}								\
+	}
+
+static inline struct ccu_pll *hw_to_ccu_pll(struct clk_hw *hw)
+{
+	struct ccu_common *common = hw_to_ccu_common(hw);
+
+	return container_of(common, struct ccu_pll, common);
+}
+
+extern const struct clk_ops spacemit_ccu_pll_ops;
+
+#endif
-- 
2.47.0

Re: [PATCH v3 3/3] clk: spacemit: Add clock support for Spacemit K1 SoC

[kernel test robot]

Hi Haylen,

kernel test robot noticed the following build warnings:

[auto build test WARNING on 2d5404caa8c7bb5c4e0435f94b28834ae5456623]

url:    https://github.com/intel-lab-lkp/linux/commits/Haylen-Chu/dt-bindings-clock-spacemit-Add-clock-controllers-of-Spacemit-K1-SoC/20241128-101248
base:   2d5404caa8c7bb5c4e0435f94b28834ae5456623
patch link:    https://lore.kernel.org/r/20241126143125.9980-7-heylenay%404d2.org
patch subject: [PATCH v3 3/3] clk: spacemit: Add clock support for Spacemit K1 SoC
config: arm-randconfig-001-20241128 (https://download.01.org/0day-ci/archive/20241128/202411281451.lC2FKL6C-lkp@intel.com/config)
compiler: clang version 20.0.0git (https://github.com/llvm/llvm-project 592c0fe55f6d9a811028b5f3507be91458ab2713)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20241128/202411281451.lC2FKL6C-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202411281451.lC2FKL6C-lkp@intel.com/

All warnings (new ones prefixed by >>):

   drivers/clk/spacemit/ccu_pll.c:128:16: warning: variable 'old_rate' set but not used [-Wunused-but-set-variable]
     128 |         unsigned long old_rate;
         |                       ^
>> drivers/clk/spacemit/ccu_pll.c:152:2: warning: variable 'val' is uninitialized when used here [-Wuninitialized]
     152 |         val |= entry->reg5 << PLL_SWCR1_REG5_OFF;
         |         ^~~
   drivers/clk/spacemit/ccu_pll.c:130:15: note: initialize the variable 'val' to silence this warning
     130 |         u32 mask, val;
         |                      ^
         |                       = 0
>> drivers/clk/spacemit/ccu_pll.c:141:14: warning: variable 'entry' is used uninitialized whenever 'for' loop exits because its condition is false [-Wsometimes-uninitialized]
     141 |         for (i = 0; i < params->tbl_size; i++) {
         |                     ^~~~~~~~~~~~~~~~~~~~
   drivers/clk/spacemit/ccu_pll.c:152:9: note: uninitialized use occurs here
     152 |         val |= entry->reg5 << PLL_SWCR1_REG5_OFF;
         |                ^~~~~
   drivers/clk/spacemit/ccu_pll.c:141:14: note: remove the condition if it is always true
     141 |         for (i = 0; i < params->tbl_size; i++) {
         |                     ^~~~~~~~~~~~~~~~~~~~
   drivers/clk/spacemit/ccu_pll.c:127:32: note: initialize the variable 'entry' to silence this warning
     127 |         struct ccu_pll_rate_tbl *entry;
         |                                       ^
         |                                        = NULL
   3 warnings generated.


vim +/val +152 drivers/clk/spacemit/ccu_pll.c

   115	
   116	/*
   117	 * pll rate change requires sequence:
   118	 * clock off -> change rate setting -> clock on
   119	 * This function doesn't really change rate, but cache the config
   120	 */
   121	static int ccu_pll_set_rate(struct clk_hw *hw, unsigned long rate,
   122				       unsigned long parent_rate)
   123	{
   124		struct ccu_pll *p = hw_to_ccu_pll(hw);
   125		struct ccu_common *common = &p->common;
   126		struct ccu_pll_config *params = &p->pll;
   127		struct ccu_pll_rate_tbl *entry;
 > 128		unsigned long old_rate;
   129		bool found = false;
   130		u32 mask, val;
   131		int i;
   132	
   133		if (ccu_pll_is_enabled(hw)) {
   134			pr_err("%s %s is enabled, ignore the setrate!\n",
   135			       __func__, __clk_get_name(hw->clk));
   136			return 0;
   137		}
   138	
   139		old_rate = __get_vco_freq(hw);
   140	
 > 141		for (i = 0; i < params->tbl_size; i++) {
   142			if (rate == params->rate_tbl[i].rate) {
   143				found = true;
   144				entry = &params->rate_tbl[i];
   145				break;
   146			}
   147		}
   148		WARN_ON_ONCE(!found);
   149	
   150		mask = PLL_SWCR1_REG5_MASK | PLL_SWCR1_REG6_MASK;
   151		mask |= PLL_SWCR1_REG7_MASK | PLL_SWCR1_REG8_MASK;
 > 152		val |= entry->reg5 << PLL_SWCR1_REG5_OFF;
   153		val |= entry->reg6 << PLL_SWCR1_REG6_OFF;
   154		val |= entry->reg7 << PLL_SWCR1_REG7_OFF;
   155		val |= entry->reg8 << PLL_SWCR1_REG8_OFF;
   156		ccu_update(swcr1, common, mask, val);
   157	
   158		mask = PLL_SWCR3_DIV_INT_MASK | PLL_SWCR3_DIV_FRC_MASK;
   159		val = entry->div_int << PLL_SWCR3_DIV_INT_OFF;
   160		val |= entry->div_frac << PLL_SWCR3_DIV_FRC_OFF;
   161		ccu_update(swcr3, common, mask, val);
   162	
   163		return 0;
   164	}
   165	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [PATCH v3 3/3] clk: spacemit: Add clock support for Spacemit K1 SoC

[kernel test robot]

Hi Haylen,

kernel test robot noticed the following build warnings:

[auto build test WARNING on 2d5404caa8c7bb5c4e0435f94b28834ae5456623]

url:    https://github.com/intel-lab-lkp/linux/commits/Haylen-Chu/dt-bindings-clock-spacemit-Add-clock-controllers-of-Spacemit-K1-SoC/20241128-101248
base:   2d5404caa8c7bb5c4e0435f94b28834ae5456623
patch link:    https://lore.kernel.org/r/20241126143125.9980-7-heylenay%404d2.org
patch subject: [PATCH v3 3/3] clk: spacemit: Add clock support for Spacemit K1 SoC
config: loongarch-allyesconfig (https://download.01.org/0day-ci/archive/20241128/202411282305.iJ9x0lmj-lkp@intel.com/config)
compiler: loongarch64-linux-gcc (GCC) 14.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20241128/202411282305.iJ9x0lmj-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202411282305.iJ9x0lmj-lkp@intel.com/

All warnings (new ones prefixed by >>):

   drivers/clk/spacemit/ccu_pll.c: In function 'ccu_pll_set_rate':
>> drivers/clk/spacemit/ccu_pll.c:128:23: warning: variable 'old_rate' set but not used [-Wunused-but-set-variable]
     128 |         unsigned long old_rate;
         |                       ^~~~~~~~
--
   drivers/clk/spacemit/ccu_mix.c: In function 'ccu_mix_set_rate':
>> drivers/clk/spacemit/ccu_mix.c:180:23: warning: variable 'best_rate' set but not used [-Wunused-but-set-variable]
     180 |         unsigned long best_rate = 0;
         |                       ^~~~~~~~~
--
   drivers/clk/spacemit/ccu_ddn.c: In function 'clk_ddn_set_rate':
>> drivers/clk/spacemit/ccu_ddn.c:115:23: warning: variable 'prev_rate' set but not used [-Wunused-but-set-variable]
     115 |         unsigned long prev_rate, rate = 0;
         |                       ^~~~~~~~~


vim +/old_rate +128 drivers/clk/spacemit/ccu_pll.c

   115	
   116	/*
   117	 * pll rate change requires sequence:
   118	 * clock off -> change rate setting -> clock on
   119	 * This function doesn't really change rate, but cache the config
   120	 */
   121	static int ccu_pll_set_rate(struct clk_hw *hw, unsigned long rate,
   122				       unsigned long parent_rate)
   123	{
   124		struct ccu_pll *p = hw_to_ccu_pll(hw);
   125		struct ccu_common *common = &p->common;
   126		struct ccu_pll_config *params = &p->pll;
   127		struct ccu_pll_rate_tbl *entry;
 > 128		unsigned long old_rate;
   129		bool found = false;
   130		u32 mask, val;
   131		int i;
   132	
   133		if (ccu_pll_is_enabled(hw)) {
   134			pr_err("%s %s is enabled, ignore the setrate!\n",
   135			       __func__, __clk_get_name(hw->clk));
   136			return 0;
   137		}
   138	
   139		old_rate = __get_vco_freq(hw);
   140	
   141		for (i = 0; i < params->tbl_size; i++) {
   142			if (rate == params->rate_tbl[i].rate) {
   143				found = true;
   144				entry = &params->rate_tbl[i];
   145				break;
   146			}
   147		}
   148		WARN_ON_ONCE(!found);
   149	
   150		mask = PLL_SWCR1_REG5_MASK | PLL_SWCR1_REG6_MASK;
   151		mask |= PLL_SWCR1_REG7_MASK | PLL_SWCR1_REG8_MASK;
   152		val |= entry->reg5 << PLL_SWCR1_REG5_OFF;
   153		val |= entry->reg6 << PLL_SWCR1_REG6_OFF;
   154		val |= entry->reg7 << PLL_SWCR1_REG7_OFF;
   155		val |= entry->reg8 << PLL_SWCR1_REG8_OFF;
   156		ccu_update(swcr1, common, mask, val);
   157	
   158		mask = PLL_SWCR3_DIV_INT_MASK | PLL_SWCR3_DIV_FRC_MASK;
   159		val = entry->div_int << PLL_SWCR3_DIV_INT_OFF;
   160		val |= entry->div_frac << PLL_SWCR3_DIV_FRC_OFF;
   161		ccu_update(swcr3, common, mask, val);
   162	
   163		return 0;
   164	}
   165	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [PATCH v3 3/3] clk: spacemit: Add clock support for Spacemit K1 SoC

[kernel test robot]

Hi Haylen,

kernel test robot noticed the following build errors:

[auto build test ERROR on 2d5404caa8c7bb5c4e0435f94b28834ae5456623]

url:    https://github.com/intel-lab-lkp/linux/commits/Haylen-Chu/dt-bindings-clock-spacemit-Add-clock-controllers-of-Spacemit-K1-SoC/20241128-101248
base:   2d5404caa8c7bb5c4e0435f94b28834ae5456623
patch link:    https://lore.kernel.org/r/20241126143125.9980-7-heylenay%404d2.org
patch subject: [PATCH v3 3/3] clk: spacemit: Add clock support for Spacemit K1 SoC
config: parisc-allmodconfig (https://download.01.org/0day-ci/archive/20241129/202411292351.6EVdr1rF-lkp@intel.com/config)
compiler: hppa-linux-gcc (GCC) 14.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20241129/202411292351.6EVdr1rF-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202411292351.6EVdr1rF-lkp@intel.com/

All errors (new ones prefixed by >>, old ones prefixed by <<):

ERROR: modpost: missing MODULE_LICENSE() in drivers/clk/spacemit/ccu_pll.o
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/spacemit/ccu_pll.o
ERROR: modpost: missing MODULE_LICENSE() in drivers/clk/spacemit/ccu_mix.o
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/spacemit/ccu_mix.o
ERROR: modpost: missing MODULE_LICENSE() in drivers/clk/spacemit/ccu_ddn.o
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/spacemit/ccu_ddn.o
>> ERROR: modpost: "spacemit_ccu_mix_ops" [drivers/clk/spacemit/ccu-k1.ko] undefined!
>> ERROR: modpost: "spacemit_ccu_ddn_ops" [drivers/clk/spacemit/ccu-k1.ko] undefined!
>> ERROR: modpost: "spacemit_ccu_pll_ops" [drivers/clk/spacemit/ccu-k1.ko] undefined!

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [PATCH v3 3/3] clk: spacemit: Add clock support for Spacemit K1 SoC

[Inochi Amaoto]

On Tue, Nov 26, 2024 at 02:31:28PM +0000, Haylen Chu wrote:
> The clock tree of K1 SoC contains three main types of clock hardware
> (PLL/DDN/MIX) and is managed by several independent controllers in
> different SoC parts (APBC, APBS and etc.), thus different compatible
> strings are added to distinguish them.
> 
> Some controllers may share IO region with reset controller and other low
> speed peripherals like watchdog, so all register operations are done
> through regmap to avoid competition.
> 
> Signed-off-by: Haylen Chu <heylenay@4d2.org>
> ---
>  drivers/clk/Kconfig               |    1 +
>  drivers/clk/Makefile              |    1 +
>  drivers/clk/spacemit/Kconfig      |   20 +
>  drivers/clk/spacemit/Makefile     |    5 +
>  drivers/clk/spacemit/ccu-k1.c     | 1747 +++++++++++++++++++++++++++++
>  drivers/clk/spacemit/ccu_common.h |   62 +
>  drivers/clk/spacemit/ccu_ddn.c    |  146 +++
>  drivers/clk/spacemit/ccu_ddn.h    |   85 ++
>  drivers/clk/spacemit/ccu_mix.c    |  296 +++++
>  drivers/clk/spacemit/ccu_mix.h    |  336 ++++++
>  drivers/clk/spacemit/ccu_pll.c    |  198 ++++
>  drivers/clk/spacemit/ccu_pll.h    |   80 ++
>  12 files changed, 2977 insertions(+)
>  create mode 100644 drivers/clk/spacemit/Kconfig
>  create mode 100644 drivers/clk/spacemit/Makefile
>  create mode 100644 drivers/clk/spacemit/ccu-k1.c
>  create mode 100644 drivers/clk/spacemit/ccu_common.h
>  create mode 100644 drivers/clk/spacemit/ccu_ddn.c
>  create mode 100644 drivers/clk/spacemit/ccu_ddn.h
>  create mode 100644 drivers/clk/spacemit/ccu_mix.c
>  create mode 100644 drivers/clk/spacemit/ccu_mix.h
>  create mode 100644 drivers/clk/spacemit/ccu_pll.c
>  create mode 100644 drivers/clk/spacemit/ccu_pll.h
> 
> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> index 299bc678ed1b..fa8b5e8f2926 100644
> --- a/drivers/clk/Kconfig
> +++ b/drivers/clk/Kconfig
> @@ -498,6 +498,7 @@ source "drivers/clk/samsung/Kconfig"
>  source "drivers/clk/sifive/Kconfig"
>  source "drivers/clk/socfpga/Kconfig"
>  source "drivers/clk/sophgo/Kconfig"
> +source "drivers/clk/spacemit/Kconfig"
>  source "drivers/clk/sprd/Kconfig"
>  source "drivers/clk/starfive/Kconfig"
>  source "drivers/clk/sunxi/Kconfig"
> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> index fb8878a5d7d9..e82ece2d0095 100644
> --- a/drivers/clk/Makefile
> +++ b/drivers/clk/Makefile
> @@ -129,6 +129,7 @@ obj-$(CONFIG_COMMON_CLK_SAMSUNG)	+= samsung/
>  obj-$(CONFIG_CLK_SIFIVE)		+= sifive/
>  obj-y					+= socfpga/
>  obj-y					+= sophgo/
> +obj-y					+= spacemit/
>  obj-$(CONFIG_PLAT_SPEAR)		+= spear/
>  obj-y					+= sprd/
>  obj-$(CONFIG_ARCH_STI)			+= st/
> diff --git a/drivers/clk/spacemit/Kconfig b/drivers/clk/spacemit/Kconfig
> new file mode 100644
> index 000000000000..76090cd85668
> --- /dev/null
> +++ b/drivers/clk/spacemit/Kconfig
> @@ -0,0 +1,20 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +
> +config SPACEMIT_CCU
> +	tristate "Clock support for Spacemit SoCs"
> +	default y
> +	depends on ARCH_SPACEMIT || COMPILE_TEST
> +	select MFD_SYSCON
> +	help
> +	  Say Y to enable clock controller unit support for Spacemit SoCs.
> +
> +if SPACEMIT_CCU
> +
> +config SPACEMIT_K1_CCU
> +	tristate "Support for Spacemit K1 SoC"
> +	default y
> +	depends on ARCH_SPACEMIT || COMPILE_TEST
> +	help
> +	  Support for clock controller unit in Spacemit K1 SoC.
> +
> +endif
> diff --git a/drivers/clk/spacemit/Makefile b/drivers/clk/spacemit/Makefile
> new file mode 100644
> index 000000000000..9d1d5f759eb1
> --- /dev/null
> +++ b/drivers/clk/spacemit/Makefile
> @@ -0,0 +1,5 @@
> +# SPDX-License-Identifier: GPL-2.0
> +
> +obj-$(CONFIG_SPACEMIT_CCU)	+= ccu_pll.o ccu_mix.o ccu_ddn.o
> +
> +obj-$(CONFIG_SPACEMIT_K1_CCU)	+= ccu-k1.o
> diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c
> new file mode 100644
> index 000000000000..0b003fba4a8b
> --- /dev/null
> +++ b/drivers/clk/spacemit/ccu-k1.c
> @@ -0,0 +1,1747 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2024 SpacemiT Technology Co. Ltd
> + * Copyright (c) 2024 Haylen Chu <heylenay@outlook.com>
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/delay.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +
> +#include "ccu_common.h"
> +#include "ccu_pll.h"
> +#include "ccu_mix.h"
> +#include "ccu_ddn.h"
> +
> +#include <dt-bindings/clock/spacemit,k1-ccu.h>
> +
> +/*	APBS register offset	*/
> +/*	pll1	*/
> +#define APB_SPARE1_REG			0x100
> +#define APB_SPARE2_REG			0x104
> +#define APB_SPARE3_REG			0x108
> +/*	pll2	*/
> +#define APB_SPARE7_REG			0x118
> +#define APB_SPARE8_REG			0x11c
> +#define APB_SPARE9_REG			0x120
> +/*	pll3	*/
> +#define APB_SPARE10_REG			0x124
> +#define APB_SPARE11_REG			0x128
> +#define APB_SPARE12_REG			0x12c
> +
> +/* MPMU register offset */
> +#define MPMU_POSR			0x10
> +#define POSR_PLL1_LOCK			BIT(27)
> +#define POSR_PLL2_LOCK			BIT(28)
> +#define POSR_PLL3_LOCK			BIT(29)
> +
> +#define MPMU_WDTPCR			0x200
> +#define MPMU_RIPCCR			0x210
> +#define MPMU_ACGR			0x1024
> +#define MPMU_SUCCR			0x14
> +#define MPMU_ISCCR			0x44
> +#define MPMU_SUCCR_1			0x10b0
> +#define MPMU_APBCSCR			0x1050
> +
> +/* APBC register offset */
> +#define APBC_UART1_CLK_RST		0x0
> +#define APBC_UART2_CLK_RST		0x4
> +#define APBC_GPIO_CLK_RST		0x8
> +#define APBC_PWM0_CLK_RST		0xc
> +#define APBC_PWM1_CLK_RST		0x10
> +#define APBC_PWM2_CLK_RST		0x14
> +#define APBC_PWM3_CLK_RST		0x18
> +#define APBC_TWSI8_CLK_RST		0x20
> +#define APBC_UART3_CLK_RST		0x24
> +#define APBC_RTC_CLK_RST		0x28
> +#define APBC_TWSI0_CLK_RST		0x2c
> +#define APBC_TWSI1_CLK_RST		0x30
> +#define APBC_TIMERS1_CLK_RST		0x34
> +#define APBC_TWSI2_CLK_RST		0x38
> +#define APBC_AIB_CLK_RST		0x3c
> +#define APBC_TWSI4_CLK_RST		0x40
> +#define APBC_TIMERS2_CLK_RST		0x44
> +#define APBC_ONEWIRE_CLK_RST		0x48
> +#define APBC_TWSI5_CLK_RST		0x4c
> +#define APBC_DRO_CLK_RST		0x58
> +#define APBC_IR_CLK_RST			0x5c
> +#define APBC_TWSI6_CLK_RST		0x60
> +#define APBC_COUNTER_CLK_SEL		0x64
> +#define APBC_TWSI7_CLK_RST		0x68
> +#define APBC_TSEN_CLK_RST		0x6c
> +#define APBC_UART4_CLK_RST		0x70
> +#define APBC_UART5_CLK_RST		0x74
> +#define APBC_UART6_CLK_RST		0x78
> +#define APBC_SSP3_CLK_RST		0x7c
> +#define APBC_SSPA0_CLK_RST		0x80
> +#define APBC_SSPA1_CLK_RST		0x84
> +#define APBC_IPC_AP2AUD_CLK_RST		0x90
> +#define APBC_UART7_CLK_RST		0x94
> +#define APBC_UART8_CLK_RST		0x98
> +#define APBC_UART9_CLK_RST		0x9c
> +#define APBC_CAN0_CLK_RST		0xa0
> +#define APBC_PWM4_CLK_RST		0xa8
> +#define APBC_PWM5_CLK_RST		0xac
> +#define APBC_PWM6_CLK_RST		0xb0
> +#define APBC_PWM7_CLK_RST		0xb4
> +#define APBC_PWM8_CLK_RST		0xb8
> +#define APBC_PWM9_CLK_RST		0xbc
> +#define APBC_PWM10_CLK_RST		0xc0
> +#define APBC_PWM11_CLK_RST		0xc4
> +#define APBC_PWM12_CLK_RST		0xc8
> +#define APBC_PWM13_CLK_RST		0xcc
> +#define APBC_PWM14_CLK_RST		0xd0
> +#define APBC_PWM15_CLK_RST		0xd4
> +#define APBC_PWM16_CLK_RST		0xd8
> +#define APBC_PWM17_CLK_RST		0xdc
> +#define APBC_PWM18_CLK_RST		0xe0
> +#define APBC_PWM19_CLK_RST		0xe4
> +
> +/* APMU register offset */
> +#define APMU_CCI550_CLK_CTRL		0x300
> +#define APMU_CPU_C0_CLK_CTRL		0x38C
> +#define APMU_CPU_C1_CLK_CTRL		0x390
> +#define APMU_JPG_CLK_RES_CTRL		0x20
> +#define APMU_CSI_CCIC2_CLK_RES_CTRL	0x24
> +#define APMU_ISP_CLK_RES_CTRL		0x38
> +#define APMU_LCD_CLK_RES_CTRL1		0x44
> +#define APMU_LCD_SPI_CLK_RES_CTRL	0x48
> +#define APMU_LCD_CLK_RES_CTRL2		0x4c
> +#define APMU_CCIC_CLK_RES_CTRL		0x50
> +#define APMU_SDH0_CLK_RES_CTRL		0x54
> +#define APMU_SDH1_CLK_RES_CTRL		0x58
> +#define APMU_USB_CLK_RES_CTRL		0x5c
> +#define APMU_QSPI_CLK_RES_CTRL		0x60
> +#define APMU_USB_CLK_RES_CTRL		0x5c
> +#define APMU_DMA_CLK_RES_CTRL		0x64
> +#define APMU_AES_CLK_RES_CTRL		0x68
> +#define APMU_VPU_CLK_RES_CTRL		0xa4
> +#define APMU_GPU_CLK_RES_CTRL		0xcc
> +#define APMU_SDH2_CLK_RES_CTRL		0xe0
> +#define APMU_PMUA_MC_CTRL		0xe8
> +#define APMU_PMU_CC2_AP			0x100
> +#define APMU_PMUA_EM_CLK_RES_CTRL	0x104
> +#define APMU_AUDIO_CLK_RES_CTRL		0x14c
> +#define APMU_HDMI_CLK_RES_CTRL		0x1B8
> +#define APMU_CCI550_CLK_CTRL		0x300
> +#define APMU_ACLK_CLK_CTRL		0x388
> +#define APMU_CPU_C0_CLK_CTRL		0x38C
> +#define APMU_CPU_C1_CLK_CTRL		0x390
> +#define APMU_PCIE_CLK_RES_CTRL_0	0x3cc
> +#define APMU_PCIE_CLK_RES_CTRL_1	0x3d4
> +#define APMU_PCIE_CLK_RES_CTRL_2	0x3dc
> +#define APMU_EMAC0_CLK_RES_CTRL		0x3e4
> +#define APMU_EMAC1_CLK_RES_CTRL		0x3ec
> +
> +/*	APBS clocks start	*/
> +
> +/* Frequency of pll{1,2} should not be updated at runtime */
> +static const struct ccu_pll_rate_tbl pll1_rate_tbl[] = {
> +	CCU_PLL_RATE(2457600000UL, 0x64, 0xdd, 0x50, 0x00, 0x33, 0x0ccccd),
> +};
> +
> +static const struct ccu_pll_rate_tbl pll2_rate_tbl[] = {
> +	CCU_PLL_RATE(3000000000UL, 0x66, 0xdd, 0x50, 0x00, 0x3f, 0xe00000),
> +};
> +
> +static const struct ccu_pll_rate_tbl pll3_rate_tbl[] = {
> +	CCU_PLL_RATE(3000000000UL, 0x66, 0xdd, 0x50, 0x00, 0x3f, 0xe00000),
> +	CCU_PLL_RATE(3200000000UL, 0x67, 0xdd, 0x50, 0x00, 0x43, 0xeaaaab),
> +	CCU_PLL_RATE(2457600000UL, 0x64, 0xdd, 0x50, 0x00, 0x33, 0x0ccccd),
> +};
> +
> +static CCU_PLL_DEFINE(pll1, "pll1", pll1_rate_tbl,
> +		      APB_SPARE1_REG, APB_SPARE2_REG, APB_SPARE3_REG,
> +		      MPMU_POSR, POSR_PLL1_LOCK, 0);
> +static CCU_PLL_DEFINE(pll2, "pll2", pll2_rate_tbl,
> +		      APB_SPARE7_REG, APB_SPARE8_REG, APB_SPARE9_REG,
> +		      MPMU_POSR, POSR_PLL2_LOCK, 0);
> +static CCU_PLL_DEFINE(pll3, "pll3", pll3_rate_tbl,
> +		      APB_SPARE10_REG, APB_SPARE11_REG, APB_SPARE12_REG,
> +		      MPMU_POSR, POSR_PLL3_LOCK, 0);
> +
> +static CCU_GATE_FACTOR_DEFINE(pll1_d2, "pll1_d2", CCU_PARENT_HW(pll1),
> +			      APB_SPARE2_REG,
> +			      BIT(1), BIT(1), 0, 2, 1, 0);
> +static CCU_GATE_FACTOR_DEFINE(pll1_d3, "pll1_d3", CCU_PARENT_HW(pll1),
> +			      APB_SPARE2_REG,
> +			      BIT(2), BIT(2), 0, 3, 1, 0);
> +static CCU_GATE_FACTOR_DEFINE(pll1_d4, "pll1_d4", CCU_PARENT_HW(pll1),
> +			      APB_SPARE2_REG,
> +			      BIT(3), BIT(3), 0, 4, 1, 0);
> +static CCU_GATE_FACTOR_DEFINE(pll1_d5, "pll1_d5", CCU_PARENT_HW(pll1),
> +			      APB_SPARE2_REG,
> +			      BIT(4), BIT(4), 0, 5, 1, 0);
> +static CCU_GATE_FACTOR_DEFINE(pll1_d6, "pll1_d6", CCU_PARENT_HW(pll1),
> +			      APB_SPARE2_REG,
> +			      BIT(5), BIT(5), 0, 6, 1, 0);
> +static CCU_GATE_FACTOR_DEFINE(pll1_d7, "pll1_d7", CCU_PARENT_HW(pll1),
> +			      APB_SPARE2_REG,
> +			      BIT(6), BIT(6), 0, 7, 1, 0);
> +static CCU_GATE_FACTOR_DEFINE(pll1_d8, "pll1_d8", CCU_PARENT_HW(pll1),
> +			      APB_SPARE2_REG,
> +			      BIT(7), BIT(7), 0, 8, 1, 0);
> +static CCU_GATE_FACTOR_DEFINE(pll1_d11_223p4, "pll1_d11_223p4", CCU_PARENT_HW(pll1),
> +			      APB_SPARE2_REG,
> +			      BIT(15), BIT(15), 0, 11, 1, 0);
> +static CCU_GATE_FACTOR_DEFINE(pll1_d13_189, "pll1_d13_189", CCU_PARENT_HW(pll1),
> +			      APB_SPARE2_REG,
> +			      BIT(16), BIT(16), 0, 13, 1, 0);
> +static CCU_GATE_FACTOR_DEFINE(pll1_d23_106p8, "pll1_d23_106p8", CCU_PARENT_HW(pll1),
> +			      APB_SPARE2_REG,
> +			      BIT(20), BIT(20), 0, 23, 1, 0);
> +static CCU_GATE_FACTOR_DEFINE(pll1_d64_38p4, "pll1_d64_38p4", CCU_PARENT_HW(pll1),
> +			      APB_SPARE2_REG,
> +			      BIT(0), BIT(0), 0, 64, 1, 0);
> +static CCU_GATE_FACTOR_DEFINE(pll1_aud_245p7, "pll1_aud_245p7", CCU_PARENT_HW(pll1),
> +			      APB_SPARE2_REG,
> +			      BIT(10), BIT(10), 0, 10, 1, 0);
> +static CCU_GATE_FACTOR_DEFINE(pll1_aud_24p5, "pll1_aud_24p5", CCU_PARENT_HW(pll1),
> +			      APB_SPARE2_REG,
> +			      BIT(11), BIT(11), 0, 100, 1, 0);
> +
> +static CCU_GATE_FACTOR_DEFINE(pll2_d1, "pll2_d1", CCU_PARENT_HW(pll2),
> +			      APB_SPARE8_REG,
> +			      BIT(0), BIT(0), 0, 1, 1, 0);
> +static CCU_GATE_FACTOR_DEFINE(pll2_d2, "pll2_d2", CCU_PARENT_HW(pll2),
> +			      APB_SPARE8_REG,
> +			      BIT(1), BIT(1), 0, 2, 1, 0);
> +static CCU_GATE_FACTOR_DEFINE(pll2_d3, "pll2_d3", CCU_PARENT_HW(pll2),
> +			      APB_SPARE8_REG,
> +			      BIT(2), BIT(2), 0, 3, 1, 0);
> +static CCU_GATE_FACTOR_DEFINE(pll2_d4, "pll2_d4", CCU_PARENT_HW(pll2),
> +			      APB_SPARE8_REG,
> +			      BIT(3), BIT(3), 0, 4, 1, 0);
> +static CCU_GATE_FACTOR_DEFINE(pll2_d5, "pll2_d5", CCU_PARENT_HW(pll2),
> +			      APB_SPARE8_REG,
> +			      BIT(4), BIT(4), 0, 5, 1, 0);
> +static CCU_GATE_FACTOR_DEFINE(pll2_d6, "pll2_d6", CCU_PARENT_HW(pll2),
> +			      APB_SPARE8_REG,
> +			      BIT(5), BIT(5), 0, 6, 1, 0);
> +static CCU_GATE_FACTOR_DEFINE(pll2_d7, "pll2_d7", CCU_PARENT_HW(pll2),
> +			      APB_SPARE8_REG,
> +			      BIT(6), BIT(6), 0, 7, 1, 0);
> +static CCU_GATE_FACTOR_DEFINE(pll2_d8, "pll2_d8", CCU_PARENT_HW(pll2),
> +			      APB_SPARE8_REG,
> +			      BIT(7), BIT(7), 0, 8, 1, 0);
> +
> +static CCU_GATE_FACTOR_DEFINE(pll3_d1, "pll3_d1", CCU_PARENT_HW(pll3),
> +			      APB_SPARE11_REG,
> +			      BIT(0), BIT(0), 0, 1, 1, 0);
> +static CCU_GATE_FACTOR_DEFINE(pll3_d2, "pll3_d2", CCU_PARENT_HW(pll3),
> +			      APB_SPARE11_REG,
> +			      BIT(1), BIT(1), 0, 2, 1, 0);
> +static CCU_GATE_FACTOR_DEFINE(pll3_d3, "pll3_d3", CCU_PARENT_HW(pll3),
> +			      APB_SPARE11_REG,
> +			      BIT(2), BIT(2), 0, 3, 1, 0);
> +static CCU_GATE_FACTOR_DEFINE(pll3_d4, "pll3_d4", CCU_PARENT_HW(pll3),
> +			      APB_SPARE11_REG,
> +			      BIT(3), BIT(3), 0, 4, 1, 0);
> +static CCU_GATE_FACTOR_DEFINE(pll3_d5, "pll3_d5", CCU_PARENT_HW(pll3),
> +			      APB_SPARE11_REG,
> +			      BIT(4), BIT(4), 0, 5, 1, 0);
> +static CCU_GATE_FACTOR_DEFINE(pll3_d6, "pll3_d6", CCU_PARENT_HW(pll3),
> +			      APB_SPARE11_REG,
> +			      BIT(5), BIT(5), 0, 6, 1, 0);
> +static CCU_GATE_FACTOR_DEFINE(pll3_d7, "pll3_d7", CCU_PARENT_HW(pll3),
> +			      APB_SPARE11_REG,
> +			      BIT(6), BIT(6), 0, 7, 1, 0);
> +static CCU_GATE_FACTOR_DEFINE(pll3_d8, "pll3_d8", CCU_PARENT_HW(pll3),
> +			      APB_SPARE11_REG,
> +			      BIT(7), BIT(7), 0, 8, 1, 0);
> +
> +static CCU_FACTOR_DEFINE(pll3_20, "pll3_20", CCU_PARENT_HW(pll3_d8), 20, 1);
> +static CCU_FACTOR_DEFINE(pll3_40, "pll3_40", CCU_PARENT_HW(pll3_d8), 10, 1);
> +static CCU_FACTOR_DEFINE(pll3_80, "pll3_80", CCU_PARENT_HW(pll3_d8), 5, 1);
> +
> +/*	APBS clocks end		*/
> +
> +/*	MPMU clocks start	*/
> +static CCU_GATE_DEFINE(pll1_d8_307p2, "pll1_d8_307p2", CCU_PARENT_HW(pll1_d8),
> +		       MPMU_ACGR,
> +		       BIT(13), BIT(13), 0, 0);
> +static CCU_FACTOR_DEFINE(pll1_d32_76p8, "pll1_d32_76p8", CCU_PARENT_HW(pll1_d8_307p2),
> +			 4, 1);
> +static CCU_FACTOR_DEFINE(pll1_d40_61p44, "pll1_d40_61p44", CCU_PARENT_HW(pll1_d8_307p2),
> +			 5, 1);
> +static CCU_FACTOR_DEFINE(pll1_d16_153p6, "pll1_d16_153p6", CCU_PARENT_HW(pll1_d8),
> +			 2, 1);
> +static CCU_GATE_FACTOR_DEFINE(pll1_d24_102p4, "pll1_d24_102p4", CCU_PARENT_HW(pll1_d8),
> +			      MPMU_ACGR,
> +			      BIT(12), BIT(12), 0, 3, 1, 0);
> +static CCU_GATE_FACTOR_DEFINE(pll1_d48_51p2, "pll1_d48_51p2", CCU_PARENT_HW(pll1_d8),
> +			      MPMU_ACGR,
> +			      BIT(7), BIT(7), 0, 6, 1, 0);
> +static CCU_GATE_FACTOR_DEFINE(pll1_d48_51p2_ap, "pll1_d48_51p2_ap", CCU_PARENT_HW(pll1_d8),
> +			      MPMU_ACGR,
> +			      BIT(11), BIT(11), 0, 6, 1, 0);
> +static CCU_GATE_FACTOR_DEFINE(pll1_m3d128_57p6, "pll1_m3d128_57p6", CCU_PARENT_HW(pll1_d8),
> +			      MPMU_ACGR,
> +			      BIT(8), BIT(8), 0, 16, 3, 0);
> +static CCU_GATE_FACTOR_DEFINE(pll1_d96_25p6, "pll1_d96_25p6", CCU_PARENT_HW(pll1_d8),
> +			      MPMU_ACGR,
> +			      BIT(4), BIT(4), 0, 12, 1, 0);
> +static CCU_GATE_FACTOR_DEFINE(pll1_d192_12p8, "pll1_d192_12p8", CCU_PARENT_HW(pll1_d8),
> +			      MPMU_ACGR,
> +			      BIT(3), BIT(3), 0, 24, 1, 0);
> +static CCU_GATE_FACTOR_DEFINE(pll1_d192_12p8_wdt, "pll1_d192_12p8_wdt", CCU_PARENT_HW(pll1_d8),
> +			      MPMU_ACGR,
> +			      BIT(19), BIT(19), 0x0, 24, 1, 0);
> +static CCU_GATE_FACTOR_DEFINE(pll1_d384_6p4, "pll1_d384_6p4", CCU_PARENT_HW(pll1_d8),
> +			      MPMU_ACGR,
> +			      BIT(2), BIT(2), 0, 48, 1, 0);
> +static CCU_FACTOR_DEFINE(pll1_d768_3p2, "pll1_d768_3p2", CCU_PARENT_HW(pll1_d384_6p4),
> +			 2, 1);
> +static CCU_FACTOR_DEFINE(pll1_d1536_1p6, "pll1_d1536_1p6", CCU_PARENT_HW(pll1_d384_6p4),
> +			 4, 1);
> +static CCU_FACTOR_DEFINE(pll1_d3072_0p8, "pll1_d3072_0p8", CCU_PARENT_HW(pll1_d384_6p4),
> +			 8, 1);
> +
> +static CCU_FACTOR_DEFINE(pll1_d7_351p08, "pll1_d7_351p08", CCU_PARENT_HW(pll1_d7),
> +			 1, 1);
> +
> +static CCU_GATE_DEFINE(pll1_d6_409p6, "pll1_d6_409p6", CCU_PARENT_HW(pll1_d6),
> +		       MPMU_ACGR,
> +		       BIT(0), BIT(0), 0, 0);
> +static CCU_GATE_FACTOR_DEFINE(pll1_d12_204p8, "pll1_d12_204p8", CCU_PARENT_HW(pll1_d6),
> +			      MPMU_ACGR,
> +			      BIT(5), BIT(5), 0, 2, 1, 0);
> +
> +static CCU_GATE_DEFINE(pll1_d5_491p52, "pll1_d5_491p52", CCU_PARENT_HW(pll1_d5),
> +		       MPMU_ACGR,
> +		       BIT(21), BIT(21), 0, 0);
> +static CCU_GATE_FACTOR_DEFINE(pll1_d10_245p76, "pll1_d10_245p76", CCU_PARENT_HW(pll1_d5),
> +			      MPMU_ACGR,
> +			      BIT(18), BIT(18), 0, 2, 1, 0);
> +
> +static CCU_GATE_DEFINE(pll1_d4_614p4, "pll1_d4_614p4", CCU_PARENT_HW(pll1_d4),
> +		       MPMU_ACGR,
> +		       BIT(15), BIT(15), 0, 0);
> +static CCU_GATE_FACTOR_DEFINE(pll1_d52_47p26, "pll1_d52_47p26", CCU_PARENT_HW(pll1_d4),
> +			      MPMU_ACGR,
> +			      BIT(10), BIT(10), 0, 13, 1, 0);
> +static CCU_GATE_FACTOR_DEFINE(pll1_d78_31p5, "pll1_d78_31p5", CCU_PARENT_HW(pll1_d4),
> +			      MPMU_ACGR,
> +			      BIT(6), BIT(6), 0, 39, 2, 0);
> +
> +static CCU_GATE_DEFINE(pll1_d3_819p2, "pll1_d3_819p2", CCU_PARENT_HW(pll1_d3),
> +		       MPMU_ACGR,
> +		       BIT(14), BIT(14), 0, 0);
> +
> +static CCU_GATE_DEFINE(pll1_d2_1228p8, "pll1_d2_1228p8", CCU_PARENT_HW(pll1_d2),
> +		       MPMU_ACGR,
> +		       BIT(16), BIT(16), 0, 0);
> +
> +static struct ccu_ddn_info uart_ddn_mask_info = {
> +	.factor		= 2,
> +	.num_mask	= 0x1fff,
> +	.den_mask	= 0x1fff,
> +	.num_shift	= 16,
> +	.den_shift	= 0,
> +};
> +static struct ccu_ddn_tbl slow_uart1_tbl[] = {
> +	{ .num = 125, .den = 24 },
> +};
> +static struct ccu_ddn_tbl slow_uart2_tbl[] = {
> +	{ .num = 6144, .den = 960 },
> +};
> +static CCU_GATE_DEFINE(slow_uart, "slow_uart", CCU_PARENT_NAME(osc_32k),
> +		       MPMU_ACGR,
> +		       BIT(1), BIT(1), 0, CLK_IGNORE_UNUSED);
> +static CCU_DDN_DEFINE(slow_uart1_14p74, "slow_uart1_14p74", pll1_d16_153p6,
> +		      &uart_ddn_mask_info, slow_uart1_tbl,
> +		      MPMU_SUCCR, 0);
> +static CCU_DDN_DEFINE(slow_uart2_48, "slow_uart2_48", pll1_d4_614p4,
> +		      &uart_ddn_mask_info, slow_uart2_tbl,
> +		      MPMU_SUCCR_1, 0);
> +
> +static CCU_GATE_DEFINE(wdt_clk, "wdt_clk", CCU_PARENT_HW(pll1_d96_25p6),
> +		       MPMU_WDTPCR,
> +		       BIT(1), BIT(1), 0x0,
> +		       0);
> +
> +static CCU_GATE_DEFINE(ripc_clk, "ripc_clk", CCU_PARENT_NAME(vctcxo_24m),
> +		       MPMU_RIPCCR,
> +		       0x3, 0x3, 0x0,
> +		       0);
> +
> +static CCU_GATE_FACTOR_DEFINE(i2s_sysclk, "i2s_sysclk", CCU_PARENT_HW(pll1_d16_153p6),
> +			      MPMU_ISCCR,
> +			      BIT(31), BIT(31), 0x0, 50, 1,
> +			      0);
> +static CCU_GATE_FACTOR_DEFINE(i2s_bclk, "i2s_bclk", CCU_PARENT_HW(i2s_sysclk),
> +			      MPMU_ISCCR,
> +			      BIT(29), BIT(29), 0x0, 1, 1,
> +			      0);
> +
> +static const struct clk_parent_data apb_parents[] = {
> +	CCU_PARENT_HW(pll1_d96_25p6),
> +	CCU_PARENT_HW(pll1_d48_51p2),
> +	CCU_PARENT_HW(pll1_d96_25p6),
> +	CCU_PARENT_HW(pll1_d24_102p4),
> +};
> +static CCU_MUX_DEFINE(apb_clk, "apb_clk", apb_parents,
> +		      MPMU_APBCSCR,
> +		      0, 2,
> +		      0);
> +
> +static CCU_GATE_DEFINE(wdt_bus_clk, "wdt_bus_clk", CCU_PARENT_HW(apb_clk),
> +		       MPMU_WDTPCR,
> +		       BIT(2), BIT(2), 0x0,
> +		       0);
> +/*	MPMU clocks end		*/
> +
> +/*	APBC clocks start	*/
> +static const struct clk_parent_data uart_clk_parents[] = {
> +	CCU_PARENT_HW(pll1_m3d128_57p6),
> +	CCU_PARENT_HW(slow_uart1_14p74),
> +	CCU_PARENT_HW(slow_uart2_48),
> +};
> +static CCU_MUX_GATE_DEFINE(uart0_clk, "uart0_clk", uart_clk_parents,
> +			   APBC_UART1_CLK_RST,
> +			   4, 3, BIT(1), BIT(1), 0x0,
> +			   CLK_IS_CRITICAL);
> +static CCU_MUX_GATE_DEFINE(uart2_clk, "uart2_clk", uart_clk_parents,
> +			   APBC_UART2_CLK_RST,
> +			   4, 3, BIT(1), BIT(1), 0x0,
> +			   0);
> +static CCU_MUX_GATE_DEFINE(uart3_clk, "uart3_clk", uart_clk_parents,
> +			   APBC_UART3_CLK_RST,
> +			   4, 3, BIT(1), BIT(1), 0x0,
> +			   0);
> +static CCU_MUX_GATE_DEFINE(uart4_clk, "uart4_clk", uart_clk_parents,
> +			   APBC_UART4_CLK_RST,
> +			   4, 3, BIT(1), BIT(1), 0x0,
> +			   0);
> +static CCU_MUX_GATE_DEFINE(uart5_clk, "uart5_clk", uart_clk_parents,
> +			   APBC_UART5_CLK_RST,
> +			   4, 3, BIT(1), BIT(1), 0x0,
> +			   0);
> +static CCU_MUX_GATE_DEFINE(uart6_clk, "uart6_clk", uart_clk_parents,
> +			   APBC_UART6_CLK_RST,
> +			   4, 3, BIT(1), BIT(1), 0x0,
> +			   0);
> +static CCU_MUX_GATE_DEFINE(uart7_clk, "uart7_clk", uart_clk_parents,
> +			   APBC_UART7_CLK_RST,
> +			   4, 3, BIT(1), BIT(1), 0x0,
> +			   0);
> +static CCU_MUX_GATE_DEFINE(uart8_clk, "uart8_clk", uart_clk_parents,
> +			   APBC_UART8_CLK_RST,
> +			   4, 3, BIT(1), BIT(1), 0x0,
> +			   0);
> +static CCU_MUX_GATE_DEFINE(uart9_clk, "uart9_clk", uart_clk_parents,
> +			   APBC_UART9_CLK_RST,
> +			   4, 3, BIT(1), BIT(1), 0x0,
> +			   0);
> +
> +static CCU_GATE_DEFINE(gpio_clk, "gpio_clk", CCU_PARENT_NAME(vctcxo_24m),
> +		       APBC_GPIO_CLK_RST,
> +		       BIT(1), BIT(1), 0x0,
> +		       0);
> +
> +static const struct clk_parent_data pwm_parents[] = {
> +	CCU_PARENT_HW(pll1_d192_12p8),
> +	CCU_PARENT_NAME(osc_32k),
> +};
> +static CCU_MUX_GATE_DEFINE(pwm0_clk, "pwm0_clk", pwm_parents,
> +			   APBC_PWM0_CLK_RST,
> +			   4, 3, BIT(1), BIT(1), 0x0,
> +			   0);
> +static CCU_MUX_GATE_DEFINE(pwm1_clk, "pwm1_clk", pwm_parents,
> +			   APBC_PWM1_CLK_RST,
> +			   4, 3, BIT(1), BIT(1), 0x0,
> +			   0);
> +static CCU_MUX_GATE_DEFINE(pwm2_clk, "pwm2_clk", pwm_parents,
> +			   APBC_PWM2_CLK_RST,
> +			   4, 3, BIT(1), BIT(1), 0x0,
> +			   0);
> +static CCU_MUX_GATE_DEFINE(pwm3_clk, "pwm3_clk", pwm_parents,
> +			   APBC_PWM3_CLK_RST,
> +			   4, 3, BIT(1), BIT(1), 0x0,
> +			   0);
> +static CCU_MUX_GATE_DEFINE(pwm4_clk, "pwm4_clk", pwm_parents,
> +			   APBC_PWM4_CLK_RST,
> +			   4, 3, BIT(1), BIT(1), 0x0,
> +			   0);
> +static CCU_MUX_GATE_DEFINE(pwm5_clk, "pwm5_clk", pwm_parents,
> +			   APBC_PWM5_CLK_RST,
> +			   4, 3, BIT(1), BIT(1), 0x0,
> +			   0);
> +static CCU_MUX_GATE_DEFINE(pwm6_clk, "pwm6_clk", pwm_parents,
> +			   APBC_PWM6_CLK_RST,
> +			   4, 3, BIT(1), BIT(1), 0x0,
> +			   0);
> +static CCU_MUX_GATE_DEFINE(pwm7_clk, "pwm7_clk", pwm_parents,
> +			   APBC_PWM7_CLK_RST,
> +			   4, 3, BIT(1), BIT(1), 0x0,
> +			   0);
> +static CCU_MUX_GATE_DEFINE(pwm8_clk, "pwm8_clk", pwm_parents,
> +			   APBC_PWM8_CLK_RST,
> +			   4, 3, BIT(1), BIT(1), 0x0,
> +			   0);
> +static CCU_MUX_GATE_DEFINE(pwm9_clk, "pwm9_clk", pwm_parents,
> +			   APBC_PWM9_CLK_RST,
> +			   4, 3, BIT(1), BIT(1), 0x0,
> +			   0);
> +static CCU_MUX_GATE_DEFINE(pwm10_clk, "pwm10_clk", pwm_parents,
> +			   APBC_PWM10_CLK_RST,
> +			   4, 3, BIT(1), BIT(1), 0x0,
> +			   0);
> +static CCU_MUX_GATE_DEFINE(pwm11_clk, "pwm11_clk", pwm_parents,
> +			   APBC_PWM11_CLK_RST,
> +			   4, 3, BIT(1), BIT(1), 0x0,
> +			   0);
> +static CCU_MUX_GATE_DEFINE(pwm12_clk, "pwm12_clk", pwm_parents,
> +			   APBC_PWM12_CLK_RST,
> +			   4, 3, BIT(1), BIT(1), 0x0,
> +			   0);
> +static CCU_MUX_GATE_DEFINE(pwm13_clk, "pwm13_clk", pwm_parents,
> +			   APBC_PWM13_CLK_RST,
> +			   4, 3, BIT(1), BIT(1), 0x0,
> +			   0);
> +static CCU_MUX_GATE_DEFINE(pwm14_clk, "pwm14_clk", pwm_parents,
> +			   APBC_PWM14_CLK_RST,
> +			   4, 3, BIT(1), BIT(1), 0x0,
> +			   0);
> +static CCU_MUX_GATE_DEFINE(pwm15_clk, "pwm15_clk", pwm_parents,
> +			   APBC_PWM15_CLK_RST,
> +			   4, 3, BIT(1), BIT(1), 0x0,
> +			   0);
> +static CCU_MUX_GATE_DEFINE(pwm16_clk, "pwm16_clk", pwm_parents,
> +			   APBC_PWM16_CLK_RST,
> +			   4, 3, BIT(1), BIT(1), 0x0,
> +			   0);
> +static CCU_MUX_GATE_DEFINE(pwm17_clk, "pwm17_clk", pwm_parents,
> +			   APBC_PWM17_CLK_RST,
> +			   4, 3, BIT(1), BIT(1), 0x0,
> +			   0);
> +static CCU_MUX_GATE_DEFINE(pwm18_clk, "pwm18_clk", pwm_parents,
> +			   APBC_PWM18_CLK_RST,
> +			   4, 3, BIT(1), BIT(1), 0x0,
> +			   0);
> +static CCU_MUX_GATE_DEFINE(pwm19_clk, "pwm19_clk", pwm_parents,
> +			   APBC_PWM19_CLK_RST,
> +			   4, 3, BIT(1), BIT(1), 0x0,
> +			   0);
> +
> +static const struct clk_parent_data ssp_parents[] = {
> +	CCU_PARENT_HW(pll1_d384_6p4),
> +	CCU_PARENT_HW(pll1_d192_12p8),
> +	CCU_PARENT_HW(pll1_d96_25p6),
> +	CCU_PARENT_HW(pll1_d48_51p2),
> +	CCU_PARENT_HW(pll1_d768_3p2),
> +	CCU_PARENT_HW(pll1_d1536_1p6),
> +	CCU_PARENT_HW(pll1_d3072_0p8),
> +};
> +static CCU_MUX_GATE_DEFINE(ssp3_clk, "ssp3_clk", ssp_parents,
> +			   APBC_SSP3_CLK_RST,
> +			   4, 3, BIT(1), BIT(1), 0x0,
> +			   0);
> +
> +static CCU_GATE_DEFINE(rtc_clk, "rtc_clk", CCU_PARENT_NAME(osc_32k),
> +		       APBC_RTC_CLK_RST,
> +		       0x82, 0x82, 0x0,
> +		       0);
> +
> +static const struct clk_parent_data twsi_parents[] = {
> +	CCU_PARENT_HW(pll1_d78_31p5),
> +	CCU_PARENT_HW(pll1_d48_51p2),
> +	CCU_PARENT_HW(pll1_d40_61p44),
> +};
> +static CCU_MUX_GATE_DEFINE(twsi0_clk, "twsi0_clk", twsi_parents,
> +			   APBC_TWSI0_CLK_RST,
> +			   4, 3, BIT(1), BIT(1), 0x0,
> +			   0);
> +static CCU_MUX_GATE_DEFINE(twsi1_clk, "twsi1_clk", twsi_parents,
> +			   APBC_TWSI1_CLK_RST,
> +			   4, 3, BIT(1), BIT(1), 0x0,
> +			   0);
> +static CCU_MUX_GATE_DEFINE(twsi2_clk, "twsi2_clk", twsi_parents,
> +			   APBC_TWSI2_CLK_RST,
> +			   4, 3, BIT(1), BIT(1), 0x0,
> +			   0);
> +static CCU_MUX_GATE_DEFINE(twsi4_clk, "twsi4_clk", twsi_parents,
> +			   APBC_TWSI4_CLK_RST,
> +			   4, 3, BIT(1), BIT(1), 0x0,
> +			   0);
> +static CCU_MUX_GATE_DEFINE(twsi5_clk, "twsi5_clk", twsi_parents,
> +			   APBC_TWSI5_CLK_RST,
> +			   4, 3, BIT(1), BIT(1), 0x0,
> +			   0);
> +static CCU_MUX_GATE_DEFINE(twsi6_clk, "twsi6_clk", twsi_parents,
> +			   APBC_TWSI6_CLK_RST,
> +			   4, 3, BIT(1), BIT(1), 0x0,
> +			   0);
> +static CCU_MUX_GATE_DEFINE(twsi7_clk, "twsi7_clk", twsi_parents,
> +			   APBC_TWSI7_CLK_RST,
> +			   4, 3, BIT(1), BIT(1), 0x0,
> +			   0);
> +static CCU_MUX_GATE_DEFINE(twsi8_clk, "twsi8_clk", twsi_parents,
> +			   APBC_TWSI8_CLK_RST,
> +			   4, 3, BIT(1), BIT(1), 0x0,
> +			   0);
> +
> +static const struct clk_parent_data timer_parents[] = {
> +	CCU_PARENT_HW(pll1_d192_12p8),
> +	CCU_PARENT_NAME(osc_32k),
> +	CCU_PARENT_HW(pll1_d384_6p4),
> +	CCU_PARENT_NAME(vctcxo_3m),
> +	CCU_PARENT_NAME(vctcxo_1m),
> +};
> +static CCU_MUX_GATE_DEFINE(timers1_clk, "timers1_clk", timer_parents,
> +			   APBC_TIMERS1_CLK_RST,
> +			   4, 3, 0x3, 0x3, 0x0,
> +			   0);
> +static CCU_MUX_GATE_DEFINE(timers2_clk, "timers2_clk", timer_parents,
> +			   APBC_TIMERS2_CLK_RST,
> +			   4, 3, 0x3, 0x3, 0x0,
> +			   0);
> +
> +static CCU_GATE_DEFINE(aib_clk, "aib_clk", CCU_PARENT_NAME(vctcxo_24m),
> +		       APBC_AIB_CLK_RST,
> +		       BIT(1), BIT(1), 0x0,
> +		       0);
> +
> +static CCU_GATE_DEFINE(onewire_clk, "onewire_clk", CCU_PARENT_NAME(vctcxo_24m),
> +		       APBC_ONEWIRE_CLK_RST,
> +		       BIT(1), BIT(1), 0x0,
> +		       0);
> +
> +static const struct clk_parent_data sspa_parents[] = {
> +	CCU_PARENT_HW(pll1_d384_6p4),
> +	CCU_PARENT_HW(pll1_d192_12p8),
> +	CCU_PARENT_HW(pll1_d96_25p6),
> +	CCU_PARENT_HW(pll1_d48_51p2),
> +	CCU_PARENT_HW(pll1_d768_3p2),
> +	CCU_PARENT_HW(pll1_d1536_1p6),
> +	CCU_PARENT_HW(pll1_d3072_0p8),
> +	CCU_PARENT_HW(i2s_bclk),
> +};
> +static CCU_MUX_GATE_DEFINE(sspa0_clk, "sspa0_clk", sspa_parents,
> +			   APBC_SSPA0_CLK_RST,
> +			   4, 3, BIT(1), BIT(1), 0x0,
> +			   0);
> +static CCU_MUX_GATE_DEFINE(sspa1_clk, "sspa1_clk", sspa_parents,
> +			   APBC_SSPA1_CLK_RST,
> +			   4, 3, BIT(1), BIT(1), 0x0,
> +			   0);
> +static CCU_GATE_DEFINE(dro_clk, "dro_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_DRO_CLK_RST,
> +		       BIT(1), BIT(1), 0x0,
> +		       0);
> +static CCU_GATE_DEFINE(ir_clk, "ir_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_IR_CLK_RST,
> +		       BIT(1), BIT(1), 0x0,
> +		       0);
> +static CCU_GATE_DEFINE(tsen_clk, "tsen_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_TSEN_CLK_RST,
> +		       BIT(1), BIT(1), 0x0,
> +		       0);
> +static CCU_GATE_DEFINE(ipc_ap2aud_clk, "ipc_ap2aud_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_IPC_AP2AUD_CLK_RST,
> +		       BIT(1), BIT(1), 0x0,
> +		       0);
> +
> +static const struct clk_parent_data can_parents[] = {
> +	CCU_PARENT_HW(pll3_20),
> +	CCU_PARENT_HW(pll3_40),
> +	CCU_PARENT_HW(pll3_80),
> +};
> +static CCU_MUX_GATE_DEFINE(can0_clk, "can0_clk", can_parents,
> +			   APBC_CAN0_CLK_RST,
> +			   4, 3, BIT(1), BIT(1), 0x0,
> +			   0);
> +static CCU_GATE_DEFINE(can0_bus_clk, "can0_bus_clk", CCU_PARENT_NAME(vctcxo_24m),
> +		       APBC_CAN0_CLK_RST,
> +		       BIT(0), BIT(0), 0x0,
> +		       0);
> +
> +static CCU_GATE_DEFINE(uart0_bus_clk, "uart0_bus_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_UART1_CLK_RST,
> +		       BIT(0), BIT(0), 0x0,
> +		       CLK_IS_CRITICAL);
> +static CCU_GATE_DEFINE(uart2_bus_clk, "uart2_bus_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_UART2_CLK_RST,
> +		       BIT(0), BIT(0), 0x0,
> +		       0);
> +static CCU_GATE_DEFINE(uart3_bus_clk, "uart3_bus_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_UART3_CLK_RST,
> +		       BIT(0), BIT(0), 0x0,
> +		       0);
> +static CCU_GATE_DEFINE(uart4_bus_clk, "uart4_bus_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_UART4_CLK_RST,
> +		       BIT(0), BIT(0), 0x0,
> +		       0);
> +static CCU_GATE_DEFINE(uart5_bus_clk, "uart5_bus_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_UART5_CLK_RST,
> +		       BIT(0), BIT(0), 0x0,
> +		       0);
> +static CCU_GATE_DEFINE(uart6_bus_clk, "uart6_bus_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_UART6_CLK_RST,
> +		       BIT(0), BIT(0), 0x0,
> +		       0);
> +static CCU_GATE_DEFINE(uart7_bus_clk, "uart7_bus_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_UART7_CLK_RST,
> +		       BIT(0), BIT(0), 0x0,
> +		       0);
> +static CCU_GATE_DEFINE(uart8_bus_clk, "uart8_bus_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_UART8_CLK_RST,
> +		       BIT(0), BIT(0), 0x0,
> +		       0);
> +static CCU_GATE_DEFINE(uart9_bus_clk, "uart9_bus_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_UART9_CLK_RST,
> +		       BIT(0), BIT(0), 0x0,
> +		       0);
> +
> +static CCU_GATE_DEFINE(gpio_bus_clk, "gpio_bus_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_GPIO_CLK_RST,
> +		       BIT(0), BIT(0), 0x0,
> +		       0);
> +
> +static CCU_GATE_DEFINE(pwm0_bus_clk, "pwm0_bus_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_PWM0_CLK_RST,
> +		       BIT(0), BIT(0), 0x0,
> +		       0);
> +static CCU_GATE_DEFINE(pwm1_bus_clk, "pwm1_bus_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_PWM1_CLK_RST,
> +		       BIT(0), BIT(0), 0x0,
> +		       0);
> +static CCU_GATE_DEFINE(pwm2_bus_clk, "pwm2_bus_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_PWM2_CLK_RST,
> +		       BIT(0), BIT(0), 0x0,
> +		       0);
> +static CCU_GATE_DEFINE(pwm3_bus_clk, "pwm3_bus_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_PWM3_CLK_RST,
> +		       BIT(0), BIT(0), 0x0,
> +		       0);
> +static CCU_GATE_DEFINE(pwm4_bus_clk, "pwm4_bus_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_PWM4_CLK_RST,
> +		       BIT(0), BIT(0), 0x0,
> +		       0);
> +static CCU_GATE_DEFINE(pwm5_bus_clk, "pwm5_bus_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_PWM5_CLK_RST,
> +		       BIT(0), BIT(0), 0x0,
> +		       0);
> +static CCU_GATE_DEFINE(pwm6_bus_clk, "pwm6_bus_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_PWM6_CLK_RST,
> +		       BIT(0), BIT(0), 0x0,
> +		       0);
> +static CCU_GATE_DEFINE(pwm7_bus_clk, "pwm7_bus_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_PWM7_CLK_RST,
> +		       BIT(0), BIT(0), 0x0,
> +		       0);
> +static CCU_GATE_DEFINE(pwm8_bus_clk, "pwm8_bus_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_PWM8_CLK_RST,
> +		       BIT(0), BIT(0), 0x0,
> +		       0);
> +static CCU_GATE_DEFINE(pwm9_bus_clk, "pwm9_bus_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_PWM9_CLK_RST,
> +		       BIT(0), BIT(0), 0x0,
> +		       0);
> +static CCU_GATE_DEFINE(pwm10_bus_clk, "pwm10_bus_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_PWM10_CLK_RST,
> +		       BIT(0), BIT(0), 0x0,
> +		       0);
> +static CCU_GATE_DEFINE(pwm11_bus_clk, "pwm11_bus_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_PWM11_CLK_RST,
> +		       BIT(0), BIT(0), 0x0,
> +		       0);
> +static CCU_GATE_DEFINE(pwm12_bus_clk, "pwm12_bus_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_PWM12_CLK_RST,
> +		       BIT(0), BIT(0), 0x0,
> +		       0);
> +static CCU_GATE_DEFINE(pwm13_bus_clk, "pwm13_bus_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_PWM13_CLK_RST,
> +		       BIT(0), BIT(0), 0x0,
> +		       0);
> +static CCU_GATE_DEFINE(pwm14_bus_clk, "pwm14_bus_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_PWM14_CLK_RST,
> +		       BIT(0), BIT(0), 0x0,
> +		       0);
> +static CCU_GATE_DEFINE(pwm15_bus_clk, "pwm15_bus_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_PWM15_CLK_RST,
> +		       BIT(0), BIT(0), 0x0,
> +		       0);
> +static CCU_GATE_DEFINE(pwm16_bus_clk, "pwm16_bus_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_PWM16_CLK_RST,
> +		       BIT(0), BIT(0), 0x0,
> +		       0);
> +static CCU_GATE_DEFINE(pwm17_bus_clk, "pwm17_bus_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_PWM17_CLK_RST,
> +		       BIT(0), BIT(0), 0x0,
> +		       0);
> +static CCU_GATE_DEFINE(pwm18_bus_clk, "pwm18_bus_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_PWM18_CLK_RST,
> +		       BIT(0), BIT(0), 0x0,
> +		       0);
> +static CCU_GATE_DEFINE(pwm19_bus_clk, "pwm19_bus_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_PWM19_CLK_RST,
> +		       BIT(0), BIT(0), 0x0,
> +		       0);
> +
> +static CCU_GATE_DEFINE(ssp3_bus_clk, "ssp3_bus_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_SSP3_CLK_RST,
> +		       BIT(0), BIT(0), 0x0,
> +		       0);
> +
> +static CCU_GATE_DEFINE(rtc_bus_clk, "rtc_bus_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_RTC_CLK_RST,
> +		       BIT(0), BIT(0), 0x0,
> +		       0);
> +
> +static CCU_GATE_DEFINE(twsi0_bus_clk, "twsi0_bus_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_TWSI0_CLK_RST,
> +		       BIT(0), BIT(0), 0x0,
> +		       0);
> +static CCU_GATE_DEFINE(twsi1_bus_clk, "twsi1_bus_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_TWSI1_CLK_RST,
> +		       BIT(0), BIT(0), 0x0,
> +		       0);
> +static CCU_GATE_DEFINE(twsi2_bus_clk, "twsi2_bus_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_TWSI2_CLK_RST,
> +		       BIT(0), BIT(0), 0x0,
> +		       0);
> +static CCU_GATE_DEFINE(twsi4_bus_clk, "twsi4_bus_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_TWSI4_CLK_RST,
> +		       BIT(0), BIT(0), 0x0,
> +		       0);
> +static CCU_GATE_DEFINE(twsi5_bus_clk, "twsi5_bus_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_TWSI5_CLK_RST,
> +		       BIT(0), BIT(0), 0x0,
> +		       0);
> +static CCU_GATE_DEFINE(twsi6_bus_clk, "twsi6_bus_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_TWSI6_CLK_RST,
> +		       BIT(0), BIT(0), 0x0,
> +		       0);
> +static CCU_GATE_DEFINE(twsi7_bus_clk, "twsi7_bus_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_TWSI7_CLK_RST,
> +		       BIT(0), BIT(0), 0x0,
> +		       0);
> +static CCU_GATE_DEFINE(twsi8_bus_clk, "twsi8_bus_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_TWSI8_CLK_RST,
> +		       BIT(0), BIT(0), 0x0,
> +		       0);
> +
> +static CCU_GATE_DEFINE(timers1_bus_clk, "timers1_bus_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_TIMERS1_CLK_RST,
> +		       BIT(0), BIT(0), 0x0,
> +		       0);
> +static CCU_GATE_DEFINE(timers2_bus_clk, "timers2_bus_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_TIMERS2_CLK_RST,
> +		       BIT(0), BIT(0), 0x0,
> +		       0);
> +
> +static CCU_GATE_DEFINE(aib_bus_clk, "aib_bus_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_AIB_CLK_RST,
> +		       BIT(0), BIT(0), 0x0,
> +		       0);
> +
> +static CCU_GATE_DEFINE(onewire_bus_clk, "onewire_bus_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_ONEWIRE_CLK_RST,
> +		       BIT(0), BIT(0), 0x0,
> +		       0);
> +
> +static CCU_GATE_DEFINE(sspa0_bus_clk, "sspa0_bus_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_SSPA0_CLK_RST,
> +		       BIT(0), BIT(0), 0x0,
> +		       0);
> +static CCU_GATE_DEFINE(sspa1_bus_clk, "sspa1_bus_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_SSPA1_CLK_RST,
> +		       BIT(0), BIT(0), 0x0,
> +		       0);
> +
> +static CCU_GATE_DEFINE(tsen_bus_clk, "tsen_bus_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_TSEN_CLK_RST,
> +		       BIT(0), BIT(0), 0x0,
> +		       0);
> +
> +static CCU_GATE_DEFINE(ipc_ap2aud_bus_clk, "ipc_ap2aud_bus_clk", CCU_PARENT_HW(apb_clk),
> +		       APBC_IPC_AP2AUD_CLK_RST,
> +		       BIT(0), BIT(0), 0x0,
> +		       0);
> +/*	APBC clocks end		*/
> +
> +/*	APMU clocks start	*/
> +static const struct clk_parent_data pmua_aclk_parents[] = {
> +	CCU_PARENT_HW(pll1_d10_245p76),
> +	CCU_PARENT_HW(pll1_d8_307p2),
> +};
> +static CCU_DIV_FC_MUX_DEFINE(pmua_aclk, "pmua_aclk", pmua_aclk_parents,
> +			     APMU_ACLK_CLK_CTRL,
> +			     1, 2, BIT(4),
> +			     0, 1,
> +			     0);
> +
> +static const struct clk_parent_data cci550_clk_parents[] = {
> +	CCU_PARENT_HW(pll1_d5_491p52),
> +	CCU_PARENT_HW(pll1_d4_614p4),
> +	CCU_PARENT_HW(pll1_d3_819p2),
> +	CCU_PARENT_HW(pll2_d3),
> +};
> +static CCU_DIV_FC_MUX_DEFINE(cci550_clk, "cci550_clk", cci550_clk_parents,
> +			     APMU_CCI550_CLK_CTRL,
> +			     8, 3, BIT(12), 0, 2, CLK_IS_CRITICAL);
> +
> +static const struct clk_parent_data cpu_c0_hi_clk_parents[] = {
> +	CCU_PARENT_HW(pll3_d2),
> +	CCU_PARENT_HW(pll3_d1),
> +};
> +static CCU_MUX_DEFINE(cpu_c0_hi_clk, "cpu_c0_hi_clk", cpu_c0_hi_clk_parents,
> +		      APMU_CPU_C0_CLK_CTRL,
> +		      13, 1, 0);
> +static const struct clk_parent_data cpu_c0_clk_parents[] = {
> +	CCU_PARENT_HW(pll1_d4_614p4),
> +	CCU_PARENT_HW(pll1_d3_819p2),
> +	CCU_PARENT_HW(pll1_d6_409p6),
> +	CCU_PARENT_HW(pll1_d5_491p52),
> +	CCU_PARENT_HW(pll1_d2_1228p8),
> +	CCU_PARENT_HW(pll3_d3),
> +	CCU_PARENT_HW(pll2_d3),
> +	CCU_PARENT_HW(cpu_c0_hi_clk),
> +};
> +static CCU_MUX_FC_DEFINE(cpu_c0_core_clk, "cpu_c0_core_clk", cpu_c0_clk_parents,
> +			 APMU_CPU_C0_CLK_CTRL,
> +			 BIT(12), 0, 3, CLK_IS_CRITICAL);
> +static CCU_DIV_DEFINE(cpu_c0_ace_clk, "cpu_c0_ace_clk", CCU_PARENT_HW(cpu_c0_core_clk),
> +		      APMU_CPU_C0_CLK_CTRL,
> +		      6, 3, CLK_IS_CRITICAL);
> +static CCU_DIV_DEFINE(cpu_c0_tcm_clk, "cpu_c0_tcm_clk", CCU_PARENT_HW(cpu_c0_core_clk),
> +		      APMU_CPU_C0_CLK_CTRL, 9, 3, CLK_IS_CRITICAL);
> +
> +static const struct clk_parent_data cpu_c1_hi_clk_parents[] = {
> +	CCU_PARENT_HW(pll3_d2),
> +	CCU_PARENT_HW(pll3_d1),
> +};
> +static CCU_MUX_DEFINE(cpu_c1_hi_clk, "cpu_c1_hi_clk", cpu_c1_hi_clk_parents,
> +		      APMU_CPU_C1_CLK_CTRL,
> +		      13, 1, CLK_IS_CRITICAL);
> +static const struct clk_parent_data cpu_c1_clk_parents[] = {
> +	CCU_PARENT_HW(pll1_d4_614p4),
> +	CCU_PARENT_HW(pll1_d3_819p2),
> +	CCU_PARENT_HW(pll1_d6_409p6),
> +	CCU_PARENT_HW(pll1_d5_491p52),
> +	CCU_PARENT_HW(pll1_d2_1228p8),
> +	CCU_PARENT_HW(pll3_d3),
> +	CCU_PARENT_HW(pll2_d3),
> +	CCU_PARENT_HW(cpu_c1_hi_clk),
> +};
> +static CCU_MUX_FC_DEFINE(cpu_c1_core_clk, "cpu_c1_core_clk", cpu_c1_clk_parents,
> +			 APMU_CPU_C1_CLK_CTRL,
> +			 BIT(12), 0, 3, CLK_IS_CRITICAL);
> +static CCU_DIV_DEFINE(cpu_c1_ace_clk, "cpu_c1_ace_clk", CCU_PARENT_HW(cpu_c1_core_clk),
> +		      APMU_CPU_C1_CLK_CTRL,
> +		      6, 3, CLK_IS_CRITICAL);
> +
> +static const struct clk_parent_data jpg_parents[] = {
> +	CCU_PARENT_HW(pll1_d4_614p4),
> +	CCU_PARENT_HW(pll1_d6_409p6),
> +	CCU_PARENT_HW(pll1_d5_491p52),
> +	CCU_PARENT_HW(pll1_d3_819p2),
> +	CCU_PARENT_HW(pll1_d2_1228p8),
> +	CCU_PARENT_HW(pll2_d4),
> +	CCU_PARENT_HW(pll2_d3),
> +};
> +static CCU_DIV_FC_MUX_GATE_DEFINE(jpg_clk, "jpg_clk", jpg_parents,
> +				  APMU_JPG_CLK_RES_CTRL,
> +				  5, 3, BIT(15),
> +				  2, 3, BIT(1), BIT(1), 0x0,
> +				  0);
> +
> +static const struct clk_parent_data ccic2phy_parents[] = {
> +	CCU_PARENT_HW(pll1_d24_102p4),
> +	CCU_PARENT_HW(pll1_d48_51p2_ap),
> +};
> +static CCU_MUX_GATE_DEFINE(ccic2phy_clk, "ccic2phy_clk", ccic2phy_parents,
> +			   APMU_CSI_CCIC2_CLK_RES_CTRL,
> +			   7, 1, BIT(5), BIT(5), 0x0,
> +			   0);
> +
> +static const struct clk_parent_data ccic3phy_parents[] = {
> +	CCU_PARENT_HW(pll1_d24_102p4),
> +	CCU_PARENT_HW(pll1_d48_51p2_ap),
> +};
> +static CCU_MUX_GATE_DEFINE(ccic3phy_clk, "ccic3phy_clk", ccic3phy_parents,
> +			   APMU_CSI_CCIC2_CLK_RES_CTRL,
> +			   31, 1, BIT(30), BIT(30), 0x0,
> +			   0);
> +
> +static const struct clk_parent_data csi_parents[] = {
> +	CCU_PARENT_HW(pll1_d5_491p52),
> +	CCU_PARENT_HW(pll1_d6_409p6),
> +	CCU_PARENT_HW(pll1_d4_614p4),
> +	CCU_PARENT_HW(pll1_d3_819p2),
> +	CCU_PARENT_HW(pll2_d2),
> +	CCU_PARENT_HW(pll2_d3),
> +	CCU_PARENT_HW(pll2_d4),
> +	CCU_PARENT_HW(pll1_d2_1228p8),
> +};
> +static CCU_DIV_FC_MUX_GATE_DEFINE(csi_clk, "csi_clk", csi_parents,
> +				  APMU_CSI_CCIC2_CLK_RES_CTRL,
> +				  20, 3, BIT(15),
> +				  16, 3, BIT(4), BIT(4), 0x0,
> +				  0);
> +
> +static const struct clk_parent_data camm_parents[] = {
> +	CCU_PARENT_HW(pll1_d8_307p2),
> +	CCU_PARENT_HW(pll2_d5),
> +	CCU_PARENT_HW(pll1_d6_409p6),
> +	CCU_PARENT_NAME(vctcxo_24m),
> +};
> +static CCU_DIV_MUX_GATE_DEFINE(camm0_clk, "camm0_clk", camm_parents,
> +			       APMU_CSI_CCIC2_CLK_RES_CTRL,
> +			       23, 4, 8, 2,
> +			       BIT(28), BIT(28), 0x0,
> +			       0);
> +static CCU_DIV_MUX_GATE_DEFINE(camm1_clk, "camm1_clk", camm_parents,
> +			       APMU_CSI_CCIC2_CLK_RES_CTRL,
> +			       23, 4, 8, 2, BIT(6), BIT(6), 0x0,
> +			       0);
> +static CCU_DIV_MUX_GATE_DEFINE(camm2_clk, "camm2_clk", camm_parents,
> +			       APMU_CSI_CCIC2_CLK_RES_CTRL,
> +			       23, 4, 8, 2, BIT(3), BIT(3), 0x0,
> +			       0);
> +
> +static const struct clk_parent_data isp_cpp_parents[] = {
> +	CCU_PARENT_HW(pll1_d8_307p2),
> +	CCU_PARENT_HW(pll1_d6_409p6),
> +};
> +static CCU_DIV_MUX_GATE_DEFINE(isp_cpp_clk, "isp_cpp_clk", isp_cpp_parents,
> +			       APMU_ISP_CLK_RES_CTRL,
> +			       24, 2, 26, 1, BIT(28), BIT(28), 0x0,
> +			       0);
> +static const struct clk_parent_data isp_bus_parents[] = {
> +	CCU_PARENT_HW(pll1_d6_409p6),
> +	CCU_PARENT_HW(pll1_d5_491p52),
> +	CCU_PARENT_HW(pll1_d8_307p2),
> +	CCU_PARENT_HW(pll1_d10_245p76),
> +};
> +static CCU_DIV_FC_MUX_GATE_DEFINE(isp_bus_clk, "isp_bus_clk", isp_bus_parents,
> +				  APMU_ISP_CLK_RES_CTRL,
> +				  18, 3, BIT(23),
> +				  21, 2, BIT(17), BIT(17), 0x0,
> +				  0);
> +static const struct clk_parent_data isp_parents[] = {
> +	CCU_PARENT_HW(pll1_d6_409p6),
> +	CCU_PARENT_HW(pll1_d5_491p52),
> +	CCU_PARENT_HW(pll1_d4_614p4),
> +	CCU_PARENT_HW(pll1_d8_307p2),
> +};
> +static CCU_DIV_FC_MUX_GATE_DEFINE(isp_clk, "isp_clk", isp_parents,
> +				  APMU_ISP_CLK_RES_CTRL,
> +				  4, 3, BIT(7),
> +				  8, 2, BIT(1), BIT(1), 0x0,
> +				  0);
> +
> +static const struct clk_parent_data dpumclk_parents[] = {
> +	CCU_PARENT_HW(pll1_d6_409p6),
> +	CCU_PARENT_HW(pll1_d5_491p52),
> +	CCU_PARENT_HW(pll1_d4_614p4),
> +	CCU_PARENT_HW(pll1_d8_307p2),
> +};
> +static CCU_DIV2_FC_MUX_GATE_DEFINE(dpu_mclk, "dpu_mclk", dpumclk_parents,
> +				   APMU_LCD_CLK_RES_CTRL1,
> +				   APMU_LCD_CLK_RES_CTRL2,
> +				   1, 4, BIT(29),
> +				   5, 3, BIT(0), BIT(0), 0x0,
> +				   0);
> +
> +static const struct clk_parent_data dpuesc_parents[] = {
> +	CCU_PARENT_HW(pll1_d48_51p2_ap),
> +	CCU_PARENT_HW(pll1_d52_47p26),
> +	CCU_PARENT_HW(pll1_d96_25p6),
> +	CCU_PARENT_HW(pll1_d32_76p8),
> +};
> +static CCU_MUX_GATE_DEFINE(dpu_esc_clk, "dpu_esc_clk", dpuesc_parents,
> +			   APMU_LCD_CLK_RES_CTRL1,
> +			   0, 2, BIT(2), BIT(2), 0x0,
> +			   0);
> +
> +static const struct clk_parent_data dpubit_parents[] = {
> +	CCU_PARENT_HW(pll1_d3_819p2),
> +	CCU_PARENT_HW(pll2_d2),
> +	CCU_PARENT_HW(pll2_d3),
> +	CCU_PARENT_HW(pll1_d2_1228p8),
> +	CCU_PARENT_HW(pll2_d4),
> +	CCU_PARENT_HW(pll2_d5),
> +	CCU_PARENT_HW(pll2_d8),
> +	CCU_PARENT_HW(pll2_d8),
> +};
> +static CCU_DIV_FC_MUX_GATE_DEFINE(dpu_bit_clk, "dpu_bit_clk", dpubit_parents,
> +				  APMU_LCD_CLK_RES_CTRL1,
> +				  17, 3, BIT(31),
> +				  20, 3, BIT(16), BIT(16), 0x0,
> +				  0);
> +
> +static const struct clk_parent_data dpupx_parents[] = {
> +	CCU_PARENT_HW(pll1_d6_409p6),
> +	CCU_PARENT_HW(pll1_d5_491p52),
> +	CCU_PARENT_HW(pll1_d4_614p4),
> +	CCU_PARENT_HW(pll1_d8_307p2),
> +	CCU_PARENT_HW(pll2_d7),
> +	CCU_PARENT_HW(pll2_d8),
> +};
> +static CCU_DIV2_FC_MUX_GATE_DEFINE(dpu_pxclk, "dpu_pxclk", dpupx_parents,
> +				  APMU_LCD_CLK_RES_CTRL1,
> +				  APMU_LCD_CLK_RES_CTRL2,
> +				  17, 4, BIT(30),
> +				  21, 3, BIT(16), BIT(16), 0x0,
> +				  0);
> +
> +static CCU_GATE_DEFINE(dpu_hclk, "dpu_hclk", CCU_PARENT_HW(pmua_aclk),
> +		       APMU_LCD_CLK_RES_CTRL1,
> +		       BIT(5), BIT(5), 0x0,
> +		       0);
> +
> +static const struct clk_parent_data dpu_spi_parents[] = {
> +	CCU_PARENT_HW(pll1_d8_307p2),
> +	CCU_PARENT_HW(pll1_d6_409p6),
> +	CCU_PARENT_HW(pll1_d10_245p76),
> +	CCU_PARENT_HW(pll1_d11_223p4),
> +	CCU_PARENT_HW(pll1_d13_189),
> +	CCU_PARENT_HW(pll1_d23_106p8),
> +	CCU_PARENT_HW(pll2_d3),
> +	CCU_PARENT_HW(pll2_d5),
> +};
> +static CCU_DIV_FC_MUX_GATE_DEFINE(dpu_spi_clk, "dpu_spi_clk", dpu_spi_parents,
> +				  APMU_LCD_SPI_CLK_RES_CTRL,
> +				  8, 3, BIT(7),
> +				  12, 3, BIT(1), BIT(1), 0x0,
> +				  0);
> +static CCU_GATE_DEFINE(dpu_spi_hbus_clk, "dpu_spi_hbus_clk", CCU_PARENT_HW(pmua_aclk),
> +		       APMU_LCD_SPI_CLK_RES_CTRL,
> +		       BIT(3), BIT(3), 0x0,
> +		       0);
> +static CCU_GATE_DEFINE(dpu_spi_bus_clk, "dpu_spi_bus_clk", CCU_PARENT_HW(pmua_aclk),
> +		       APMU_LCD_SPI_CLK_RES_CTRL,
> +		       BIT(5), BIT(5), 0x0,
> +		       0);
> +static CCU_GATE_DEFINE(dpu_spi_aclk, "dpu_spi_aclk", CCU_PARENT_HW(pmua_aclk),
> +		       APMU_LCD_SPI_CLK_RES_CTRL,
> +		       BIT(6), BIT(6), 0x0,
> +		       0);
> +
> +static const struct clk_parent_data v2d_parents[] = {
> +	CCU_PARENT_HW(pll1_d5_491p52),
> +	CCU_PARENT_HW(pll1_d6_409p6),
> +	CCU_PARENT_HW(pll1_d8_307p2),
> +	CCU_PARENT_HW(pll1_d4_614p4),
> +};
> +static CCU_DIV_FC_MUX_GATE_DEFINE(v2d_clk, "v2d_clk", v2d_parents,
> +				  APMU_LCD_CLK_RES_CTRL1,
> +				  9, 3, BIT(28),
> +				  12, 2, BIT(8), BIT(8), 0x0,
> +				  0);
> +
> +static const struct clk_parent_data ccic_4x_parents[] = {
> +	CCU_PARENT_HW(pll1_d5_491p52),
> +	CCU_PARENT_HW(pll1_d6_409p6),
> +	CCU_PARENT_HW(pll1_d4_614p4),
> +	CCU_PARENT_HW(pll1_d3_819p2),
> +	CCU_PARENT_HW(pll2_d2),
> +	CCU_PARENT_HW(pll2_d3),
> +	CCU_PARENT_HW(pll2_d4),
> +	CCU_PARENT_HW(pll1_d2_1228p8),
> +};
> +static CCU_DIV_FC_MUX_GATE_DEFINE(ccic_4x_clk, "ccic_4x_clk", ccic_4x_parents,
> +				  APMU_CCIC_CLK_RES_CTRL,
> +				  18, 3, BIT(15),
> +				  23, 2, BIT(4), BIT(4), 0x0,
> +				  0);
> +
> +static const struct clk_parent_data ccic1phy_parents[] = {
> +	CCU_PARENT_HW(pll1_d24_102p4),
> +	CCU_PARENT_HW(pll1_d48_51p2_ap),
> +};
> +static CCU_MUX_GATE_DEFINE(ccic1phy_clk, "ccic1phy_clk", ccic1phy_parents,
> +			   APMU_CCIC_CLK_RES_CTRL,
> +			   7, 1, BIT(5), BIT(5), 0x0,
> +			   0);
> +
> +static CCU_GATE_DEFINE(sdh_axi_aclk, "sdh_axi_aclk", CCU_PARENT_HW(pmua_aclk),
> +		       APMU_SDH0_CLK_RES_CTRL,
> +		       BIT(3), BIT(3), 0x0,
> +		       0);
> +static const struct clk_parent_data sdh01_parents[] = {
> +	CCU_PARENT_HW(pll1_d6_409p6),
> +	CCU_PARENT_HW(pll1_d4_614p4),
> +	CCU_PARENT_HW(pll2_d8),
> +	CCU_PARENT_HW(pll2_d5),
> +	CCU_PARENT_HW(pll1_d11_223p4),
> +	CCU_PARENT_HW(pll1_d13_189),
> +	CCU_PARENT_HW(pll1_d23_106p8),
> +};
> +static CCU_DIV_FC_MUX_GATE_DEFINE(sdh0_clk, "sdh0_clk", sdh01_parents,
> +				  APMU_SDH0_CLK_RES_CTRL,
> +				  8, 3, BIT(11),
> +				  5, 3, BIT(4), BIT(4), 0x0,
> +				  0);
> +static CCU_DIV_FC_MUX_GATE_DEFINE(sdh1_clk, "sdh1_clk", sdh01_parents,
> +				  APMU_SDH1_CLK_RES_CTRL,
> +				  8, 3, BIT(11),
> +				  5, 3, BIT(4), BIT(4), 0x0,
> +				  0);
> +static const struct clk_parent_data sdh2_parents[] = {
> +	CCU_PARENT_HW(pll1_d6_409p6),
> +	CCU_PARENT_HW(pll1_d4_614p4),
> +	CCU_PARENT_HW(pll2_d8),
> +	CCU_PARENT_HW(pll1_d3_819p2),
> +	CCU_PARENT_HW(pll1_d11_223p4),
> +	CCU_PARENT_HW(pll1_d13_189),
> +	CCU_PARENT_HW(pll1_d23_106p8),
> +};
> +static CCU_DIV_FC_MUX_GATE_DEFINE(sdh2_clk, "sdh2_clk", sdh2_parents,
> +				  APMU_SDH2_CLK_RES_CTRL,
> +				  8, 3, BIT(11),
> +				  5, 3, BIT(4), BIT(4), 0x0,
> +				  0);
> +
> +static CCU_GATE_DEFINE(usb_axi_clk, "usb_axi_clk", CCU_PARENT_HW(pmua_aclk),
> +		       APMU_USB_CLK_RES_CTRL,
> +		       BIT(1), BIT(1), 0x0,
> +		       0);
> +static CCU_GATE_DEFINE(usb_p1_aclk, "usb_p1_aclk", CCU_PARENT_HW(pmua_aclk),
> +		       APMU_USB_CLK_RES_CTRL,
> +		       BIT(5), BIT(5), 0x0,
> +		       0);
> +static CCU_GATE_DEFINE(usb30_clk, "usb30_clk", CCU_PARENT_HW(pmua_aclk),
> +		       APMU_USB_CLK_RES_CTRL,
> +		       BIT(8), BIT(8), 0x0,
> +		       0);
> +
> +static const struct clk_parent_data qspi_parents[] = {
> +	CCU_PARENT_HW(pll1_d6_409p6),
> +	CCU_PARENT_HW(pll2_d8),
> +	CCU_PARENT_HW(pll1_d8_307p2),
> +	CCU_PARENT_HW(pll1_d10_245p76),
> +	CCU_PARENT_HW(pll1_d11_223p4),
> +	CCU_PARENT_HW(pll1_d23_106p8),
> +	CCU_PARENT_HW(pll1_d5_491p52),
> +	CCU_PARENT_HW(pll1_d13_189),
> +};
> +static CCU_DIV_MFC_MUX_GATE_DEFINE(qspi_clk, "qspi_clk", qspi_parents,
> +				   APMU_QSPI_CLK_RES_CTRL,
> +				   9, 3, BIT(12),
> +				   6, 3, BIT(4), BIT(4), 0x0,
> +				   0);
> +static CCU_GATE_DEFINE(qspi_bus_clk, "qspi_bus_clk", CCU_PARENT_HW(pmua_aclk),
> +		       APMU_QSPI_CLK_RES_CTRL,
> +		       BIT(3), BIT(3), 0x0,
> +		       0);
> +static CCU_GATE_DEFINE(dma_clk, "dma_clk", CCU_PARENT_HW(pmua_aclk),
> +		       APMU_DMA_CLK_RES_CTRL,
> +		       BIT(3), BIT(3), 0x0,
> +		       0);
> +
> +static const struct clk_parent_data aes_parents[] = {
> +	CCU_PARENT_HW(pll1_d12_204p8),
> +	CCU_PARENT_HW(pll1_d24_102p4),
> +};
> +static CCU_MUX_GATE_DEFINE(aes_clk, "aes_clk", aes_parents,
> +			   APMU_AES_CLK_RES_CTRL,
> +			   6, 1, BIT(5), BIT(5), 0x0,
> +			   0);
> +
> +static const struct clk_parent_data vpu_parents[] = {
> +	CCU_PARENT_HW(pll1_d4_614p4),
> +	CCU_PARENT_HW(pll1_d5_491p52),
> +	CCU_PARENT_HW(pll1_d3_819p2),
> +	CCU_PARENT_HW(pll1_d6_409p6),
> +	CCU_PARENT_HW(pll3_d6),
> +	CCU_PARENT_HW(pll2_d3),
> +	CCU_PARENT_HW(pll2_d4),
> +	CCU_PARENT_HW(pll2_d5),
> +};
> +static CCU_DIV_FC_MUX_GATE_DEFINE(vpu_clk, "vpu_clk", vpu_parents,
> +				  APMU_VPU_CLK_RES_CTRL,
> +				  13, 3, BIT(21),
> +				  10, 3,
> +				  BIT(3), BIT(3), 0x0,
> +				  0);
> +
> +static const struct clk_parent_data gpu_parents[] = {
> +	CCU_PARENT_HW(pll1_d4_614p4),
> +	CCU_PARENT_HW(pll1_d5_491p52),
> +	CCU_PARENT_HW(pll1_d3_819p2),
> +	CCU_PARENT_HW(pll1_d6_409p6),
> +	CCU_PARENT_HW(pll3_d6),
> +	CCU_PARENT_HW(pll2_d3),
> +	CCU_PARENT_HW(pll2_d4),
> +	CCU_PARENT_HW(pll2_d5),
> +};
> +static CCU_DIV_FC_MUX_GATE_DEFINE(gpu_clk, "gpu_clk", gpu_parents,
> +				  APMU_GPU_CLK_RES_CTRL,
> +				  12, 3, BIT(15),
> +				  18, 3,
> +				  BIT(4), BIT(4), 0x0,
> +				  0);
> +
> +static const struct clk_parent_data emmc_parents[] = {
> +	CCU_PARENT_HW(pll1_d6_409p6),
> +	CCU_PARENT_HW(pll1_d4_614p4),
> +	CCU_PARENT_HW(pll1_d52_47p26),
> +	CCU_PARENT_HW(pll1_d3_819p2),
> +};
> +static CCU_DIV_FC_MUX_GATE_DEFINE(emmc_clk, "emmc_clk", emmc_parents,
> +				  APMU_PMUA_EM_CLK_RES_CTRL,
> +				  8, 3, BIT(11),
> +				  6, 2,
> +				  BIT(4), BIT(4), 0x0,
> +				  0);
> +static CCU_DIV_GATE_DEFINE(emmc_x_clk, "emmc_x_clk", CCU_PARENT_HW(pll1_d2_1228p8),
> +			   APMU_PMUA_EM_CLK_RES_CTRL,
> +			   12, 3, BIT(15), BIT(15), 0x0,
> +			   0);
> +
> +static const struct clk_parent_data audio_parents[] = {
> +	CCU_PARENT_HW(pll1_aud_245p7),
> +	CCU_PARENT_HW(pll1_d8_307p2),
> +	CCU_PARENT_HW(pll1_d6_409p6),
> +};
> +static CCU_DIV_FC_MUX_GATE_DEFINE(audio_clk, "audio_clk", audio_parents,
> +				  APMU_AUDIO_CLK_RES_CTRL,
> +				  4, 3, BIT(15),
> +				  7, 3,
> +				  BIT(12), BIT(12), 0x0,
> +				  0);
> +
> +static const struct clk_parent_data hdmi_parents[] = {
> +	CCU_PARENT_HW(pll1_d6_409p6),
> +	CCU_PARENT_HW(pll1_d5_491p52),
> +	CCU_PARENT_HW(pll1_d4_614p4),
> +	CCU_PARENT_HW(pll1_d8_307p2),
> +};
> +static CCU_DIV_FC_MUX_GATE_DEFINE(hdmi_mclk, "hdmi_mclk", hdmi_parents,
> +				  APMU_HDMI_CLK_RES_CTRL,
> +				  1, 4, BIT(29),
> +				  5, 3,
> +				  BIT(0), BIT(0), 0x0,
> +				  0);
> +
> +static CCU_GATE_DEFINE(pcie0_clk, "pcie0_clk", CCU_PARENT_HW(pmua_aclk),
> +		       APMU_PCIE_CLK_RES_CTRL_0,
> +		       0x7, 0x7, 0x0,
> +		       0);
> +static CCU_GATE_DEFINE(pcie1_clk, "pcie1_clk", CCU_PARENT_HW(pmua_aclk),
> +		       APMU_PCIE_CLK_RES_CTRL_1,
> +		       0x7, 0x7, 0x0,
> +		       0);
> +static CCU_GATE_DEFINE(pcie2_clk, "pcie2_clk", CCU_PARENT_HW(pmua_aclk),
> +		       APMU_PCIE_CLK_RES_CTRL_2,
> +		       0x7, 0x7, 0x0,
> +		       0);
> +
> +static CCU_GATE_DEFINE(emac0_bus_clk, "emac0_bus_clk", CCU_PARENT_HW(pmua_aclk),
> +		       APMU_EMAC0_CLK_RES_CTRL,
> +		       BIT(0), BIT(0), 0x0,
> +		       0);
> +static CCU_GATE_DEFINE(emac0_ptp_clk, "emac0_ptp_clk", CCU_PARENT_HW(pll2_d6),
> +		       APMU_EMAC0_CLK_RES_CTRL,
> +		       BIT(15), BIT(15), 0x0,
> +		       0);
> +static CCU_GATE_DEFINE(emac1_bus_clk, "emac1_bus_clk", CCU_PARENT_HW(pmua_aclk),
> +		       APMU_EMAC1_CLK_RES_CTRL,
> +		       BIT(0), BIT(0), 0x0,
> +		       0);
> +static CCU_GATE_DEFINE(emac1_ptp_clk, "emac1_ptp_clk", CCU_PARENT_HW(pll2_d6),
> +		       APMU_EMAC1_CLK_RES_CTRL,
> +		       BIT(15), BIT(15), 0x0,
> +		       0);
> +
> +static CCU_GATE_DEFINE(emmc_bus_clk, "emmc_bus_clk", CCU_PARENT_HW(pmua_aclk),
> +		       APMU_PMUA_EM_CLK_RES_CTRL,
> +		       BIT(3), BIT(3), 0,
> +		       0);
> +/*	APMU clocks end		*/
> +
> +static struct clk_hw_onecell_data k1_ccu_apbs_clks = {
> +	.hws = {
> +		[CLK_PLL1]		= &pll1.common.hw,
> +		[CLK_PLL2]		= &pll2.common.hw,
> +		[CLK_PLL3]		= &pll3.common.hw,
> +		[CLK_PLL1_D2]		= &pll1_d2.common.hw,
> +		[CLK_PLL1_D3]		= &pll1_d3.common.hw,
> +		[CLK_PLL1_D4]		= &pll1_d4.common.hw,
> +		[CLK_PLL1_D5]		= &pll1_d5.common.hw,
> +		[CLK_PLL1_D6]		= &pll1_d6.common.hw,
> +		[CLK_PLL1_D7]		= &pll1_d7.common.hw,
> +		[CLK_PLL1_D8]		= &pll1_d8.common.hw,
> +		[CLK_PLL1_D11]		= &pll1_d11_223p4.common.hw,
> +		[CLK_PLL1_D13]		= &pll1_d13_189.common.hw,
> +		[CLK_PLL1_D23]		= &pll1_d23_106p8.common.hw,
> +		[CLK_PLL1_D64]		= &pll1_d64_38p4.common.hw,
> +		[CLK_PLL1_D10_AUD]	= &pll1_aud_245p7.common.hw,
> +		[CLK_PLL1_D100_AUD]	= &pll1_aud_24p5.common.hw,
> +		[CLK_PLL2_D1]		= &pll2_d1.common.hw,
> +		[CLK_PLL2_D2]		= &pll2_d2.common.hw,
> +		[CLK_PLL2_D3]		= &pll2_d3.common.hw,
> +		[CLK_PLL2_D3]		= &pll2_d4.common.hw,
> +		[CLK_PLL2_D5]		= &pll2_d5.common.hw,
> +		[CLK_PLL2_D6]		= &pll2_d6.common.hw,
> +		[CLK_PLL2_D7]		= &pll2_d7.common.hw,
> +		[CLK_PLL2_D8]		= &pll2_d8.common.hw,
> +		[CLK_PLL3_D1]		= &pll3_d1.common.hw,
> +		[CLK_PLL3_D2]		= &pll3_d2.common.hw,
> +		[CLK_PLL3_D3]		= &pll3_d3.common.hw,
> +		[CLK_PLL3_D4]		= &pll3_d4.common.hw,
> +		[CLK_PLL3_D5]		= &pll3_d5.common.hw,
> +		[CLK_PLL3_D6]		= &pll3_d6.common.hw,
> +		[CLK_PLL3_D7]		= &pll3_d7.common.hw,
> +		[CLK_PLL3_D8]		= &pll3_d8.common.hw,
> +		[CLK_PLL3_80]		= &pll3_80.common.hw,
> +		[CLK_PLL3_40]		= &pll3_40.common.hw,
> +		[CLK_PLL3_20]		= &pll3_20.common.hw,
> +
> +	},
> +	.num = CLK_APBS_NUM,
> +};
> +
> +static struct clk_hw_onecell_data k1_ccu_mpmu_clks = {
> +	.hws = {
> +		[CLK_PLL1_307P2]	= &pll1_d8_307p2.common.hw,
> +		[CLK_PLL1_76P8]		= &pll1_d32_76p8.common.hw,
> +		[CLK_PLL1_61P44]	= &pll1_d40_61p44.common.hw,
> +		[CLK_PLL1_153P6]	= &pll1_d16_153p6.common.hw,
> +		[CLK_PLL1_102P4]	= &pll1_d24_102p4.common.hw,
> +		[CLK_PLL1_51P2]		= &pll1_d48_51p2.common.hw,
> +		[CLK_PLL1_51P2_AP]	= &pll1_d48_51p2_ap.common.hw,
> +		[CLK_PLL1_57P6]		= &pll1_m3d128_57p6.common.hw,
> +		[CLK_PLL1_25P6]		= &pll1_d96_25p6.common.hw,
> +		[CLK_PLL1_12P8]		= &pll1_d192_12p8.common.hw,
> +		[CLK_PLL1_12P8_WDT]	= &pll1_d192_12p8_wdt.common.hw,
> +		[CLK_PLL1_6P4]		= &pll1_d384_6p4.common.hw,
> +		[CLK_PLL1_3P2]		= &pll1_d768_3p2.common.hw,
> +		[CLK_PLL1_1P6]		= &pll1_d1536_1p6.common.hw,
> +		[CLK_PLL1_0P8]		= &pll1_d3072_0p8.common.hw,
> +		[CLK_PLL1_351]		= &pll1_d7_351p08.common.hw,
> +		[CLK_PLL1_409P6]	= &pll1_d6_409p6.common.hw,
> +		[CLK_PLL1_204P8]	= &pll1_d12_204p8.common.hw,
> +		[CLK_PLL1_491]		= &pll1_d5_491p52.common.hw,
> +		[CLK_PLL1_245P76]	= &pll1_d10_245p76.common.hw,
> +		[CLK_PLL1_614]		= &pll1_d4_614p4.common.hw,
> +		[CLK_PLL1_47P26]	= &pll1_d52_47p26.common.hw,
> +		[CLK_PLL1_31P5]		= &pll1_d78_31p5.common.hw,
> +		[CLK_PLL1_819]		= &pll1_d3_819p2.common.hw,
> +		[CLK_PLL1_1228]		= &pll1_d2_1228p8.common.hw,
> +		[CLK_SLOW_UART]		= &slow_uart.common.hw,
> +		[CLK_SLOW_UART1]	= &slow_uart1_14p74.common.hw,
> +		[CLK_SLOW_UART2]	= &slow_uart2_48.common.hw,
> +		[CLK_WDT]		= &wdt_clk.common.hw,
> +		[CLK_RIPC]		= &ripc_clk.common.hw,
> +		[CLK_I2S_SYSCLK]	= &i2s_sysclk.common.hw,
> +		[CLK_I2S_BCLK]		= &i2s_bclk.common.hw,
> +		[CLK_APB]		= &apb_clk.common.hw,
> +		[CLK_WDT_BUS]		= &wdt_bus_clk.common.hw,
> +	},
> +	.num = CLK_MPMU_NUM,
> +};
> +
> +static struct clk_hw_onecell_data k1_ccu_apbc_clks = {
> +	.hws = {
> +		[CLK_UART0]		= &uart0_clk.common.hw,
> +		[CLK_UART2]		= &uart2_clk.common.hw,
> +		[CLK_UART3]		= &uart3_clk.common.hw,
> +		[CLK_UART4]		= &uart4_clk.common.hw,
> +		[CLK_UART5]		= &uart5_clk.common.hw,
> +		[CLK_UART6]		= &uart6_clk.common.hw,
> +		[CLK_UART7]		= &uart7_clk.common.hw,
> +		[CLK_UART8]		= &uart8_clk.common.hw,
> +		[CLK_UART9]		= &uart9_clk.common.hw,
> +		[CLK_GPIO]		= &gpio_clk.common.hw,
> +		[CLK_PWM0]		= &pwm0_clk.common.hw,
> +		[CLK_PWM1]		= &pwm1_clk.common.hw,
> +		[CLK_PWM2]		= &pwm2_clk.common.hw,
> +		[CLK_PWM3]		= &pwm3_clk.common.hw,
> +		[CLK_PWM4]		= &pwm4_clk.common.hw,
> +		[CLK_PWM5]		= &pwm5_clk.common.hw,
> +		[CLK_PWM6]		= &pwm6_clk.common.hw,
> +		[CLK_PWM7]		= &pwm7_clk.common.hw,
> +		[CLK_PWM8]		= &pwm8_clk.common.hw,
> +		[CLK_PWM9]		= &pwm9_clk.common.hw,
> +		[CLK_PWM10]		= &pwm10_clk.common.hw,
> +		[CLK_PWM11]		= &pwm11_clk.common.hw,
> +		[CLK_PWM12]		= &pwm12_clk.common.hw,
> +		[CLK_PWM13]		= &pwm13_clk.common.hw,
> +		[CLK_PWM14]		= &pwm14_clk.common.hw,
> +		[CLK_PWM15]		= &pwm15_clk.common.hw,
> +		[CLK_PWM16]		= &pwm16_clk.common.hw,
> +		[CLK_PWM17]		= &pwm17_clk.common.hw,
> +		[CLK_PWM18]		= &pwm18_clk.common.hw,
> +		[CLK_PWM19]		= &pwm19_clk.common.hw,
> +		[CLK_SSP3]		= &ssp3_clk.common.hw,
> +		[CLK_RTC]		= &rtc_clk.common.hw,
> +		[CLK_TWSI0]		= &twsi0_clk.common.hw,
> +		[CLK_TWSI1]		= &twsi1_clk.common.hw,
> +		[CLK_TWSI2]		= &twsi2_clk.common.hw,
> +		[CLK_TWSI4]		= &twsi4_clk.common.hw,
> +		[CLK_TWSI5]		= &twsi5_clk.common.hw,
> +		[CLK_TWSI6]		= &twsi6_clk.common.hw,
> +		[CLK_TWSI7]		= &twsi7_clk.common.hw,
> +		[CLK_TWSI8]		= &twsi8_clk.common.hw,
> +		[CLK_TIMERS1]		= &timers1_clk.common.hw,
> +		[CLK_TIMERS2]		= &timers2_clk.common.hw,
> +		[CLK_AIB]		= &aib_clk.common.hw,
> +		[CLK_ONEWIRE]		= &onewire_clk.common.hw,
> +		[CLK_SSPA0]		= &sspa0_clk.common.hw,
> +		[CLK_SSPA1]		= &sspa1_clk.common.hw,
> +		[CLK_DRO]		= &dro_clk.common.hw,
> +		[CLK_IR]		= &ir_clk.common.hw,
> +		[CLK_TSEN]		= &tsen_clk.common.hw,
> +		[CLK_IPC_AP2AUD]	= &ipc_ap2aud_clk.common.hw,
> +		[CLK_CAN0]		= &can0_clk.common.hw,
> +		[CLK_CAN0_BUS]		= &can0_bus_clk.common.hw,
> +		[CLK_UART0_BUS]		= &uart0_bus_clk.common.hw,
> +		[CLK_UART2_BUS]		= &uart2_bus_clk.common.hw,
> +		[CLK_UART3_BUS]		= &uart3_bus_clk.common.hw,
> +		[CLK_UART4_BUS]		= &uart4_bus_clk.common.hw,
> +		[CLK_UART5_BUS]		= &uart5_bus_clk.common.hw,
> +		[CLK_UART6_BUS]		= &uart6_bus_clk.common.hw,
> +		[CLK_UART7_BUS]		= &uart7_bus_clk.common.hw,
> +		[CLK_UART8_BUS]		= &uart8_bus_clk.common.hw,
> +		[CLK_UART9_BUS]		= &uart9_bus_clk.common.hw,
> +		[CLK_GPIO_BUS]		= &gpio_bus_clk.common.hw,
> +		[CLK_PWM0_BUS]		= &pwm0_bus_clk.common.hw,
> +		[CLK_PWM1_BUS]		= &pwm1_bus_clk.common.hw,
> +		[CLK_PWM2_BUS]		= &pwm2_bus_clk.common.hw,
> +		[CLK_PWM3_BUS]		= &pwm3_bus_clk.common.hw,
> +		[CLK_PWM4_BUS]		= &pwm4_bus_clk.common.hw,
> +		[CLK_PWM5_BUS]		= &pwm5_bus_clk.common.hw,
> +		[CLK_PWM6_BUS]		= &pwm6_bus_clk.common.hw,
> +		[CLK_PWM7_BUS]		= &pwm7_bus_clk.common.hw,
> +		[CLK_PWM8_BUS]		= &pwm8_bus_clk.common.hw,
> +		[CLK_PWM9_BUS]		= &pwm9_bus_clk.common.hw,
> +		[CLK_PWM10_BUS]		= &pwm10_bus_clk.common.hw,
> +		[CLK_PWM11_BUS]		= &pwm11_bus_clk.common.hw,
> +		[CLK_PWM12_BUS]		= &pwm12_bus_clk.common.hw,
> +		[CLK_PWM13_BUS]		= &pwm13_bus_clk.common.hw,
> +		[CLK_PWM14_BUS]		= &pwm14_bus_clk.common.hw,
> +		[CLK_PWM15_BUS]		= &pwm15_bus_clk.common.hw,
> +		[CLK_PWM16_BUS]		= &pwm16_bus_clk.common.hw,
> +		[CLK_PWM17_BUS]		= &pwm17_bus_clk.common.hw,
> +		[CLK_PWM18_BUS]		= &pwm18_bus_clk.common.hw,
> +		[CLK_PWM19_BUS]		= &pwm19_bus_clk.common.hw,
> +		[CLK_SSP3_BUS]		= &ssp3_bus_clk.common.hw,
> +		[CLK_RTC_BUS]		= &rtc_bus_clk.common.hw,
> +		[CLK_TWSI0_BUS]		= &twsi0_bus_clk.common.hw,
> +		[CLK_TWSI1_BUS]		= &twsi1_bus_clk.common.hw,
> +		[CLK_TWSI2_BUS]		= &twsi2_bus_clk.common.hw,
> +		[CLK_TWSI4_BUS]		= &twsi4_bus_clk.common.hw,
> +		[CLK_TWSI5_BUS]		= &twsi5_bus_clk.common.hw,
> +		[CLK_TWSI6_BUS]		= &twsi6_bus_clk.common.hw,
> +		[CLK_TWSI7_BUS]		= &twsi7_bus_clk.common.hw,
> +		[CLK_TWSI8_BUS]		= &twsi8_bus_clk.common.hw,
> +		[CLK_TIMERS1_BUS]	= &timers1_bus_clk.common.hw,
> +		[CLK_TIMERS2_BUS]	= &timers2_bus_clk.common.hw,
> +		[CLK_AIB_BUS]		= &aib_bus_clk.common.hw,
> +		[CLK_ONEWIRE_BUS]	= &onewire_bus_clk.common.hw,
> +		[CLK_SSPA0_BUS]		= &sspa0_bus_clk.common.hw,
> +		[CLK_SSPA1_BUS]		= &sspa1_bus_clk.common.hw,
> +		[CLK_TSEN_BUS]		= &tsen_bus_clk.common.hw,
> +		[CLK_IPC_AP2AUD_BUS]	= &ipc_ap2aud_bus_clk.common.hw,
> +	},
> +	.num = CLK_APBC_NUM,
> +};
> +
> +static struct clk_hw_onecell_data k1_ccu_apmu_clks = {
> +	.hws = {
> +		[CLK_CCI550]		= &cci550_clk.common.hw,
> +		[CLK_CPU_C0_HI]		= &cpu_c0_hi_clk.common.hw,
> +		[CLK_CPU_C0_CORE]	= &cpu_c0_core_clk.common.hw,
> +		[CLK_CPU_C0_ACE]	= &cpu_c0_ace_clk.common.hw,
> +		[CLK_CPU_C0_TCM]	= &cpu_c0_tcm_clk.common.hw,
> +		[CLK_CPU_C1_HI]		= &cpu_c1_hi_clk.common.hw,
> +		[CLK_CPU_C1_CORE]	= &cpu_c1_core_clk.common.hw,
> +		[CLK_CPU_C1_ACE]	= &cpu_c1_ace_clk.common.hw,
> +		[CLK_CCIC_4X]		= &ccic_4x_clk.common.hw,
> +		[CLK_CCIC1PHY]		= &ccic1phy_clk.common.hw,
> +		[CLK_SDH_AXI]		= &sdh_axi_aclk.common.hw,
> +		[CLK_SDH0]		= &sdh0_clk.common.hw,
> +		[CLK_SDH1]		= &sdh1_clk.common.hw,
> +		[CLK_SDH2]		= &sdh2_clk.common.hw,
> +		[CLK_USB_P1]		= &usb_p1_aclk.common.hw,
> +		[CLK_USB_AXI]		= &usb_axi_clk.common.hw,
> +		[CLK_USB30]		= &usb30_clk.common.hw,
> +		[CLK_QSPI]		= &qspi_clk.common.hw,
> +		[CLK_QSPI_BUS]		= &qspi_bus_clk.common.hw,
> +		[CLK_DMA]		= &dma_clk.common.hw,
> +		[CLK_AES]		= &aes_clk.common.hw,
> +		[CLK_VPU]		= &vpu_clk.common.hw,
> +		[CLK_GPU]		= &gpu_clk.common.hw,
> +		[CLK_EMMC]		= &emmc_clk.common.hw,
> +		[CLK_EMMC_X]		= &emmc_x_clk.common.hw,
> +		[CLK_AUDIO]		= &audio_clk.common.hw,
> +		[CLK_HDMI]		= &hdmi_mclk.common.hw,
> +		[CLK_PMUA_ACLK]		= &pmua_aclk.common.hw,
> +		[CLK_PCIE0]		= &pcie0_clk.common.hw,
> +		[CLK_PCIE1]		= &pcie1_clk.common.hw,
> +		[CLK_PCIE2]		= &pcie2_clk.common.hw,
> +		[CLK_EMAC0_BUS]		= &emac0_bus_clk.common.hw,
> +		[CLK_EMAC0_PTP]		= &emac0_ptp_clk.common.hw,
> +		[CLK_EMAC1_BUS]		= &emac1_bus_clk.common.hw,
> +		[CLK_EMAC1_PTP]		= &emac1_ptp_clk.common.hw,
> +		[CLK_JPG]		= &jpg_clk.common.hw,
> +		[CLK_CCIC2PHY]		= &ccic2phy_clk.common.hw,
> +		[CLK_CCIC3PHY]		= &ccic3phy_clk.common.hw,
> +		[CLK_CSI]		= &csi_clk.common.hw,
> +		[CLK_CAMM0]		= &camm0_clk.common.hw,
> +		[CLK_CAMM1]		= &camm1_clk.common.hw,
> +		[CLK_CAMM2]		= &camm2_clk.common.hw,
> +		[CLK_ISP_CPP]		= &isp_cpp_clk.common.hw,
> +		[CLK_ISP_BUS]		= &isp_bus_clk.common.hw,
> +		[CLK_ISP]		= &isp_clk.common.hw,
> +		[CLK_DPU_MCLK]		= &dpu_mclk.common.hw,
> +		[CLK_DPU_ESC]		= &dpu_esc_clk.common.hw,
> +		[CLK_DPU_BIT]		= &dpu_bit_clk.common.hw,
> +		[CLK_DPU_PXCLK]		= &dpu_pxclk.common.hw,
> +		[CLK_DPU_HCLK]		= &dpu_hclk.common.hw,
> +		[CLK_DPU_SPI]		= &dpu_spi_clk.common.hw,
> +		[CLK_DPU_SPI_HBUS]	= &dpu_spi_hbus_clk.common.hw,
> +		[CLK_DPU_SPIBUS]	= &dpu_spi_bus_clk.common.hw,
> +		[CLK_DPU_SPI_ACLK]	= &dpu_spi_aclk.common.hw,
> +		[CLK_V2D]		= &v2d_clk.common.hw,
> +		[CLK_EMMC_BUS]		= &emmc_bus_clk.common.hw,
> +	},
> +	.num = CLK_APMU_NUM
> +};
> +
> +struct spacemit_ccu_data {
> +	struct clk_hw_onecell_data *hw_clks;
> +	bool need_pll_lock;
> +};
> +
> +struct spacemit_ccu_priv {
> +	const struct spacemit_ccu_data *data;
> +	struct regmap *base;
> +	struct regmap *lock_base;
> +};
> +
> +static int spacemit_ccu_register(struct device *dev,
> +				 struct spacemit_ccu_priv *priv)
> +{
> +	const struct spacemit_ccu_data *data = priv->data;
> +	int i, ret;
> +
> +	for (i = 0; i < data->hw_clks->num; i++) {
> +		struct clk_hw *hw = data->hw_clks->hws[i];
> +		struct ccu_common *common;
> +		const char *name;
> +
> +		if (!hw)
> +			continue;
> +
> +		common = hw_to_ccu_common(hw);
> +		name = hw->init->name;
> +
> +		common->base		= priv->base;
> +		common->lock_base	= priv->lock_base;
> +
> +		ret = devm_clk_hw_register(dev, hw);
> +		if (ret) {
> +			dev_err(dev, "Cannot register clock %d - %s\n",
> +				i, name);
> +			return ret;
> +		}
> +	}
> +
> +	return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
> +					   data->hw_clks);
> +}
> +
> +static int k1_ccu_probe(struct platform_device *pdev)
> +{
> +	const struct spacemit_ccu_data *data;
> +	struct regmap *base_map, *lock_map;
> +	struct device *dev = &pdev->dev;
> +	struct spacemit_ccu_priv *priv;
> +	struct device_node *parent;
> +	int ret;
> +
> +	data = of_device_get_match_data(dev);
> +	if (WARN_ON(!data))
> +		return -EINVAL;
> +
> +	parent   = of_get_parent(dev->of_node);
> +	base_map = syscon_node_to_regmap(parent);
> +	of_node_put(parent);
> +
> +	if (IS_ERR(base_map))
> +		return dev_err_probe(dev, PTR_ERR(base_map),
> +				     "failed to get regmap\n");
> +
> +	if (data->need_pll_lock) {
> +		lock_map = syscon_regmap_lookup_by_phandle(dev->of_node,
> +							   "spacemit,mpmu");
> +		if (IS_ERR(lock_map))
> +			return dev_err_probe(dev, PTR_ERR(lock_map),
> +					     "failed to get lock regmap\n");
> +	}
> +
> +	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> +	if (!priv)
> +		return -ENOMEM;
> +
> +	priv->data	= data;
> +	priv->base	= base_map;
> +	priv->lock_base	= lock_map;
> +
> +	ret = spacemit_ccu_register(dev, priv);
> +	if (ret)
> +		return dev_err_probe(dev, ret, "failed to register clocks\n");
> +
> +	return 0;
> +}
> +
> +static const struct spacemit_ccu_data k1_ccu_apbs_data = {
> +	.need_pll_lock	= true,
> +	.hw_clks	= &k1_ccu_apbs_clks,
> +};
> +
> +static const struct spacemit_ccu_data k1_ccu_mpmu_data = {
> +	.need_pll_lock	= false,
> +	.hw_clks	= &k1_ccu_mpmu_clks,
> +};
> +
> +static const struct spacemit_ccu_data k1_ccu_apbc_data = {
> +	.need_pll_lock	= false,
> +	.hw_clks	= &k1_ccu_apbc_clks,
> +};
> +
> +static const struct spacemit_ccu_data k1_ccu_apmu_data = {
> +	.need_pll_lock	= false,
> +	.hw_clks	= &k1_ccu_apmu_clks,
> +};
> +
> +static const struct of_device_id of_k1_ccu_match[] = {
> +	{
> +		.compatible	= "spacemit,k1-ccu-apbs",
> +		.data		= &k1_ccu_apbs_data,
> +	},
> +	{
> +		.compatible	= "spacemit,k1-ccu-mpmu",
> +		.data		= &k1_ccu_mpmu_data,
> +	},
> +	{
> +		.compatible	= "spacemit,k1-ccu-apbc",
> +		.data		= &k1_ccu_apbc_data,
> +	},
> +	{
> +		.compatible	= "spacemit,k1-ccu-apmu",
> +		.data		= &k1_ccu_apmu_data,
> +	},
> +	{ }
> +};
> +MODULE_DEVICE_TABLE(of, of_k1_ccu_match);
> +
> +static struct platform_driver k1_ccu_driver = {
> +	.driver = {
> +		.name		= "spacemit,k1-ccu",
> +		.of_match_table = of_k1_ccu_match,
> +	},
> +	.probe	= k1_ccu_probe,
> +};
> +module_platform_driver(k1_ccu_driver);
> +
> +MODULE_DESCRIPTION("Spacemit K1 CCU driver");
> +MODULE_AUTHOR("Haylen Chu <heylenay@outlook.com>");
> +MODULE_LICENSE("GPL");
> diff --git a/drivers/clk/spacemit/ccu_common.h b/drivers/clk/spacemit/ccu_common.h
> new file mode 100644
> index 000000000000..9910fb69bc9e
> --- /dev/null
> +++ b/drivers/clk/spacemit/ccu_common.h
> @@ -0,0 +1,62 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2024 SpacemiT Technology Co. Ltd
> + * Copyright (c) 2024 Haylen Chu <heylenay@outlook.com>
> + */
> +
> +#ifndef _CCU_COMMON_H_
> +#define _CCU_COMMON_H_
> +
> +#include <linux/regmap.h>
> +
> +enum ccu_div_type {
> +	CLK_DIV_TYPE_1REG_NOFC_V1 = 0,
> +	CLK_DIV_TYPE_1REG_FC_V2,
> +	CLK_DIV_TYPE_2REG_NOFC_V3,
> +	CLK_DIV_TYPE_2REG_FC_V4,
> +	CLK_DIV_TYPE_1REG_FC_DIV_V5,
> +	CLK_DIV_TYPE_1REG_FC_MUX_V6,
> +};
> +
> +struct ccu_common {
> +	struct regmap *base;
> +	struct regmap *lock_base;
> +
> +	enum ccu_div_type reg_type;
> +
> +	union {
> +		struct {
> +			u32 reg_ctrl;
> +			u32 reg_sel;
> +			u32 reg_xtc;
> +			u32 fc;
> +		};
> +		struct {
> +			u32 reg_swcr1;
> +			u32 reg_swcr2;
> +			u32 reg_swcr3;
> +		};
> +	};
> +
> +	unsigned long flags;
> +	const char *name;
> +	const char * const *parent_names;
> +	int num_parents;
> +
> +	struct clk_hw hw;
> +};
> +
> +static inline struct ccu_common *hw_to_ccu_common(struct clk_hw *hw)
> +{
> +	return container_of(hw, struct ccu_common, hw);
> +}
> +
> +#define ccu_read(reg, c, val)	regmap_read((c)->base, (c)->reg_##reg, val)
> +#define ccu_write(reg, c, val)	regmap_write((c)->base, (c)->reg_##reg, val)
> +#define ccu_update(reg, c, mask, val) \
> +	regmap_update_bits((c)->base, (c)->reg_##reg, mask, val)
> +#define ccu_poll(reg, c, tmp, cond, sleep, timeout) \
> +	regmap_read_poll_timeout_atomic((c)->base, (c)->reg_##reg,	\
> +					tmp, cond, sleep, timeout)
> +
> +#endif /* _CCU_COMMON_H_ */
> diff --git a/drivers/clk/spacemit/ccu_ddn.c b/drivers/clk/spacemit/ccu_ddn.c
> new file mode 100644
> index 000000000000..7a68652676ce
> --- /dev/null
> +++ b/drivers/clk/spacemit/ccu_ddn.c
> @@ -0,0 +1,146 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Spacemit clock type ddn
> + *
> + * Copyright (c) 2024 SpacemiT Technology Co. Ltd
> + * Copyright (c) 2024 Haylen Chu <heylenay@outlook.com>
> + */
> +
> +#include <linux/clk-provider.h>
> +
> +#include "ccu_ddn.h"
> +
> +/*
> + * It is M/N clock
> + *
> + * Fout from synthesizer can be given from two equations:
> + * numerator/denominator = Fin / (Fout * factor)
> + */
> +static void ccu_ddn_disable(struct clk_hw *hw)
> +{
> +	struct ccu_ddn *ddn = hw_to_ccu_ddn(hw);
> +	struct ccu_common *common = &ddn->common;
> +
> +	if (!ddn->gate)
> +		return;

Use a new clk_ops to represent the gateable ddn clock and remove this
check. This also applys to the following function.

> +
> +	ccu_update(sel, common, ddn->gate, 0);
> +}
> +
> +static int ccu_ddn_enable(struct clk_hw *hw)
> +{
> +	struct ccu_ddn *ddn = hw_to_ccu_ddn(hw);
> +	struct ccu_common *common = &ddn->common;
> +
> +	if (!ddn->gate)
> +		return 0;
> +
> +	ccu_update(sel, common, ddn->gate, ddn->gate);
> +
> +	return 0;
> +}
> +
> +static int ccu_ddn_is_enabled(struct clk_hw *hw)
> +{
> +	struct ccu_ddn *ddn = hw_to_ccu_ddn(hw);
> +	struct ccu_common *common = &ddn->common;
> +	u32 tmp;
> +
> +	if (!ddn->gate)
> +		return 1;
> +
> +	ccu_read(sel, common, &tmp);
> +
> +	return tmp & ddn->gate;
> +}
> +
> +static long clk_ddn_round_rate(struct clk_hw *hw, unsigned long drate,
> +			       unsigned long *prate)
> +{
> +	struct ccu_ddn *ddn = hw_to_ccu_ddn(hw);
> +	struct ccu_ddn_config *params = &ddn->ddn;
> +	unsigned long rate = 0, prev_rate;
> +	unsigned long result;
> +	int i;
> +
> +	for (i = 0; i < params->tbl_size; i++) {
> +		prev_rate = rate;
> +		rate = (((*prate / 10000) * params->tbl[i].den) /
> +			(params->tbl[i].num * params->info->factor)) * 10000;
> +		if (rate > drate)
> +			break;
> +	}
> +
> +	if ((i == 0) || (i == params->tbl_size)) {
> +		result = rate;
> +	} else {
> +		if ((drate - prev_rate) > (rate - drate))
> +			result = rate;
> +		else
> +			result = prev_rate;
> +	}
> +
> +	return result;
> +}
> +
> +static unsigned long clk_ddn_recalc_rate(struct clk_hw *hw,
> +		unsigned long parent_rate)
> +{
> +	struct ccu_ddn *ddn = hw_to_ccu_ddn(hw);
> +	struct ccu_ddn_config *params = &ddn->ddn;
> +	unsigned int val, num, den;
> +	unsigned long rate;
> +
> +	ccu_read(ctrl, &ddn->common, &val);
> +
> +	num = (val >> params->info->num_shift) & params->info->num_mask;
> +	den = (val >> params->info->den_shift) & params->info->den_mask;
> +
> +	if (!den)
> +		return 0;
> +
> +	rate = ((parent_rate / 10000)  * den) / (num * params->info->factor);
> +	rate *= 10000;
> +

It is pretty interested here. Why you need to divide the clock by 10000
and multiple it? Is "(parent_rate * den) / (num * params->info->factor)"
OK?

> +	return rate;
> +}
> +
> +/* Configures new clock rate*/
> +static int clk_ddn_set_rate(struct clk_hw *hw, unsigned long drate,
> +			    unsigned long prate)
> +{
> +	struct ccu_ddn *ddn = hw_to_ccu_ddn(hw);
> +	struct ccu_ddn_config *params = &ddn->ddn;
> +	struct ccu_ddn_info *info = params->info;
> +	unsigned long prev_rate, rate = 0;
> +	int i;
> +
> +	for (i = 0; i < params->tbl_size; i++) {
> +		prev_rate = rate;
> +		rate = ((prate / 10000) * params->tbl[i].den) /
> +		       (params->tbl[i].num * info->factor);
> +		rate *= 10000;
> +
> +		if (rate > drate)
> +			break;
> +	}
> +
> +	if (i > 0)
> +		i--;
> +
> +	ccu_update(ctrl, &ddn->common,
> +		   info->num_mask | info->den_mask,
> +		   (params->tbl[i].num << info->num_shift) |
> +		   (params->tbl[i].den << info->den_shift));
> +
> +	return 0;
> +}
> +
> +const struct clk_ops spacemit_ccu_ddn_ops = {
> +	.disable	= ccu_ddn_disable,
> +	.enable		= ccu_ddn_enable,
> +	.is_enabled	= ccu_ddn_is_enabled,
> +	.recalc_rate	= clk_ddn_recalc_rate,
> +	.round_rate	= clk_ddn_round_rate,
> +	.set_rate	= clk_ddn_set_rate,
> +};
> diff --git a/drivers/clk/spacemit/ccu_ddn.h b/drivers/clk/spacemit/ccu_ddn.h
> new file mode 100644
> index 000000000000..4d369f41404c
> --- /dev/null
> +++ b/drivers/clk/spacemit/ccu_ddn.h
> @@ -0,0 +1,85 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2024 SpacemiT Technology Co. Ltd
> + * Copyright (c) 2024 Haylen Chu <heylenayy@outlook.com>
> + */
> +
> +#ifndef _CCU_DDN_H_
> +#define _CCU_DDN_H_
> +
> +#include <linux/clk-provider.h>
> +
> +#include "ccu_common.h"
> +
> +struct ccu_ddn_tbl {
> +	unsigned int num;
> +	unsigned int den;
> +};
> +
> +struct ccu_ddn_info {
> +	unsigned int factor;
> +	unsigned int num_mask;
> +	unsigned int den_mask;
> +	unsigned int num_shift;
> +	unsigned int den_shift;
> +};
> +
> +struct ccu_ddn_config {
> +	struct ccu_ddn_info *info;
> +	struct ccu_ddn_tbl *tbl;
> +	u32 tbl_size;
> +};
> +
> +struct ccu_ddn {
> +	struct ccu_ddn_config  ddn;
> +	struct ccu_common	common;
> +	u32 gate;
> +};
> +
> +#define CCU_DDN_CONFIG(_info, _table)					\
> +	{								\
> +		.info		= (struct ccu_ddn_info *)_info,		\
> +		.tbl		= (struct ccu_ddn_tbl *)&_table,	\
> +		.tbl_size	= ARRAY_SIZE(_table),			\
> +	}
> +
> +#define CCU_DDN_INIT(_name, _parent, _flags) \
> +	CLK_HW_INIT_HW(_name, &_parent.common.hw,			\
> +		       &spacemit_ccu_ddn_ops, _flags)
> +
> +#define CCU_DDN_DEFINE(_struct, _name, _parent, _info, _table,		\
> +		       _reg_ctrl, _flags)				\
> +	struct ccu_ddn _struct = {					\
> +		.ddn	= CCU_DDN_CONFIG(_info, _table),		\
> +		.common = {						\
> +			.reg_ctrl = _reg_ctrl,				\
> +			.hw.init  = CCU_DDN_INIT(_name, _parent,	\
> +						 _flags),		\
> +		}							\
> +	}
> +
> +#define CCU_DDN_GATE_DEFINE(_struct, _name, _parent, _info, _table,	\
> +			    _reg_ddn, _reg_gate, _gate_mask, _flags)	\
> +	struct ccu_ddn _struct = {					\
> +		.ddn	= CCU_DDN_CONFIG(_info, _table),		\
> +		.common = {						\
> +			.reg_ctrl	= _reg_ddn,			\
> +			.reg_sel	= _reg_gate,			\
> +			.hw.init = CLK_HW_INIT(_name, _parent,		\
> +					       &spacemit_ccu_ddn_ops,	\
> +					       _flags),			\
> +		}							\
> +		.gate	= _gate_mask,					\
> +	}
> +
> +
> +static inline struct ccu_ddn *hw_to_ccu_ddn(struct clk_hw *hw)
> +{
> +	struct ccu_common *common = hw_to_ccu_common(hw);
> +
> +	return container_of(common, struct ccu_ddn, common);
> +}
> +
> +extern const struct clk_ops spacemit_ccu_ddn_ops;
> +
> +#endif
> diff --git a/drivers/clk/spacemit/ccu_mix.c b/drivers/clk/spacemit/ccu_mix.c
> new file mode 100644
> index 000000000000..de343405fcc7
> --- /dev/null
> +++ b/drivers/clk/spacemit/ccu_mix.c
> @@ -0,0 +1,296 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Spacemit clock type mix(div/mux/gate/factor)
> + *
> + * Copyright (c) 2024 SpacemiT Technology Co. Ltd
> + * Copyright (c) 2024 Haylen Chu <heylenay@outlook.com>
> + */
> +
> +#include <linux/clk-provider.h>
> +
> +#include "ccu_mix.h"
> +
> +#define MIX_TIMEOUT	10000
> +
> +#define mix_hwparam_in_sel(c) \
> +	((c)->reg_type == CLK_DIV_TYPE_2REG_NOFC_V3 || \
> +	 (c)->reg_type == CLK_DIV_TYPE_2REG_FC_V4)
> +

> +static void ccu_mix_disable(struct clk_hw *hw)
> +{
> +	struct ccu_mix *mix = hw_to_ccu_mix(hw);
> +	struct ccu_common *common = &mix->common;
> +	struct ccu_gate_config *gate = mix->gate;
> +
> +	if (!gate)
> +		return;
> +
> +	if (mix_hwparam_in_sel(common))
> +		ccu_update(sel, common, gate->gate_mask, gate->val_disable);
> +	else
> +		ccu_update(ctrl, common, gate->gate_mask, gate->val_disable);
> +}
> +
> +static int ccu_mix_enable(struct clk_hw *hw)
> +{
> +	struct ccu_mix *mix = hw_to_ccu_mix(hw);
> +	struct ccu_common *common = &mix->common;
> +	struct ccu_gate_config *gate = mix->gate;
> +	u32 val_enable, mask;
> +	u32 tmp;
> +
> +	if (!gate)
> +		return 0;
> +
> +	val_enable	= gate->val_enable;
> +	mask		= gate->gate_mask;
> +
> +	if (mix_hwparam_in_sel(common))
> +		ccu_update(sel, common, mask, val_enable);
> +	else
> +		ccu_update(ctrl, common, mask, val_enable);
> +
> +	if (common->reg_type == CLK_DIV_TYPE_2REG_NOFC_V3 ||
> +	    common->reg_type == CLK_DIV_TYPE_2REG_FC_V4)
> +		return ccu_poll(sel, common, tmp, (tmp & mask) == val_enable,
> +				10, MIX_TIMEOUT);
> +	else
> +		return ccu_poll(ctrl, common, tmp, (tmp & mask) == val_enable,
> +				10, MIX_TIMEOUT);
> +}
> +
> +static int ccu_mix_is_enabled(struct clk_hw *hw)
> +{
> +	struct ccu_mix *mix = hw_to_ccu_mix(hw);
> +	struct ccu_common *common = &mix->common;
> +	struct ccu_gate_config *gate = mix->gate;
> +	u32 tmp;
> +
> +	if (!gate)
> +		return 1;
> +
> +	if (mix_hwparam_in_sel(common))
> +		ccu_read(sel, common, &tmp);
> +	else
> +		ccu_read(ctrl, common, &tmp);
> +
> +	return (tmp & gate->gate_mask) == gate->val_enable;
> +}
> +
> +static unsigned long ccu_mix_recalc_rate(struct clk_hw *hw,
> +					unsigned long parent_rate)
> +{
> +	struct ccu_mix *mix = hw_to_ccu_mix(hw);
> +	struct ccu_common *common = &mix->common;
> +	struct ccu_div_config *div = mix->div;
> +	unsigned long val;
> +	u32 reg;
> +
> +	if (!div) {
> +		if (mix->factor)
> +			return parent_rate * mix->factor->mul / mix->factor->div;
> +
> +		return parent_rate;
> +	}
> +
> +	if (mix_hwparam_in_sel(common))
> +		ccu_read(sel, common, &reg);
> +	else
> +		ccu_read(ctrl, common, &reg);
> +
> +	val = reg >> div->shift;
> +	val &= (1 << div->width) - 1;
> +
> +	val = divider_recalc_rate(hw, parent_rate, val, div->table,
> +				  div->flags, div->width);
> +
> +	return val;
> +}

I think you should distinguish these muxs, it is not good to
use mix_hwparam_in_sel everywhere. There are two types of mux.

> +
> +

Double empty line here, you should run checkpatch.

> +static int ccu_mix_trigger_fc(struct clk_hw *hw)
> +{
> +	struct ccu_mix *mix = hw_to_ccu_mix(hw);
> +	struct ccu_common *common = &mix->common;
> +	unsigned int val = 0;
> +	int ret = 0;
> +
> +	if (common->reg_type == CLK_DIV_TYPE_1REG_FC_V2 ||
> +	    common->reg_type == CLK_DIV_TYPE_2REG_FC_V4 ||
> +	    common->reg_type == CLK_DIV_TYPE_1REG_FC_DIV_V5 ||
> +	    common->reg_type == CLK_DIV_TYPE_1REG_FC_MUX_V6) {
> +		ccu_update(ctrl, common, common->fc, common->fc);
> +
> +		ret = ccu_poll(ctrl, common, val, !(val & common->fc),
> +			       5, MIX_TIMEOUT);
> +	}
> +
> +	return ret;
> +}
> +
> +static int ccu_mix_determine_rate(struct clk_hw *hw,
> +				  struct clk_rate_request *req)
> +{
> +	return 0;
> +}
> +

Why a empty determine_rate function?

> +static unsigned long
> +ccu_mix_calc_best_rate(struct clk_hw *hw, unsigned long rate, u32 *mux_val,
> +		       u32 *div_val)
> +{
> +	struct ccu_mix *mix = hw_to_ccu_mix(hw);
> +	struct ccu_common *common = &mix->common;
> +	struct ccu_div_config *div = mix->div ? mix->div : NULL;
> +	struct clk_hw *parent;
> +	unsigned long parent_rate = 0, best_rate = 0;
> +	u32 i, j, div_max;
> +
> +	for (i = 0; i < common->num_parents; i++) {
> +		parent = clk_hw_get_parent_by_index(hw, i);
> +		if (!parent)
> +			continue;
> +
> +		parent_rate = clk_hw_get_rate(parent);
> +
> +		if (div)
> +			div_max = 1 << div->width;
> +		else
> +			div_max = 1;
> +
> +		for (j = 1; j <= div_max; j++) {
> +			if (abs(parent_rate/j - rate) < abs(best_rate - rate)) {
> +				best_rate = DIV_ROUND_UP_ULL(parent_rate, j);
> +				*mux_val = i;
> +				*div_val = j - 1;
> +			}
> +		}
> +	}
> +
> +	return best_rate;
> +}
> +
> +static int ccu_mix_set_rate(struct clk_hw *hw, unsigned long rate,
> +			   unsigned long parent_rate)
> +{
> +	struct ccu_mix *mix = hw_to_ccu_mix(hw);
> +	struct ccu_common *common = &mix->common;
> +	struct ccu_div_config *div = mix->div;
> +	struct ccu_mux_config *mux = mix->mux;
> +	u32 cur_mux, cur_div, mux_val = 0, div_val = 0;
> +	unsigned long best_rate = 0;
> +	int ret = 0, tmp = 0;
> +
> +	if (!div && !mux)
> +		return 0;
> +
> +	best_rate = ccu_mix_calc_best_rate(hw, rate, &mux_val, &div_val);
> +
> +	if (mix_hwparam_in_sel(common))
> +		ccu_read(sel, common, &tmp);
> +	else
> +		ccu_read(ctrl, common, &tmp);
> +
> +	if (mux) {
> +		cur_mux = tmp >> mux->shift;
> +		cur_mux &= (1 << mux->width) - 1;
> +
> +		if (cur_mux != mux_val)
> +			clk_hw_set_parent(hw, clk_hw_get_parent_by_index(hw, mux_val));
> +	}
> +
> +	if (div) {
> +		cur_div = tmp >> div->shift;
> +		cur_div &= (1 << div->width) - 1;
> +
> +		if (cur_div == div_val)
> +			return 0;
> +	} else {
> +		return 0;
> +	}
> +
> +	tmp = GENMASK(div->width + div->shift - 1, div->shift);
> +
> +	if (mix_hwparam_in_sel(common))
> +		ccu_update(sel, common, tmp, div_val << div->shift);
> +	else
> +		ccu_update(ctrl, common, tmp, div_val << div->shift);
> +
> +	if (common->reg_type == CLK_DIV_TYPE_1REG_FC_V2 ||
> +	    common->reg_type == CLK_DIV_TYPE_2REG_FC_V4 ||
> +	    common->reg_type == CLK_DIV_TYPE_1REG_FC_DIV_V5)
> +		ret = ccu_mix_trigger_fc(hw);
> +
> +	return ret;
> +}
> +
> +static u8 ccu_mix_get_parent(struct clk_hw *hw)
> +{
> +	struct ccu_mix *mix = hw_to_ccu_mix(hw);
> +	struct ccu_common *common = &mix->common;
> +	struct ccu_mux_config *mux = mix->mux;
> +	u32 reg;
> +	u8 parent;
> +
> +	if (!mux)
> +		return 0;
> +
> +	if (mix_hwparam_in_sel(common))
> +		ccu_read(sel, common, &reg);
> +	else
> +		ccu_read(ctrl, common, &reg);
> +
> +	parent = reg >> mux->shift;
> +	parent &= (1 << mux->width) - 1;
> +
> +	if (mux->table) {
> +		int num_parents = clk_hw_get_num_parents(&common->hw);
> +		int i;
> +
> +		for (i = 0; i < num_parents; i++)
> +			if (mux->table[i] == parent)
> +				return i;
> +	}
> +
> +	return parent;
> +}
> +
> +static int ccu_mix_set_parent(struct clk_hw *hw, u8 index)
> +{
> +	struct ccu_mix *mix = hw_to_ccu_mix(hw);
> +	struct ccu_common *common = &mix->common;
> +	struct ccu_mux_config *mux = mix->mux;
> +	int ret = 0;
> +	u32 mask;
> +
> +	if (!mux)
> +		return 0;
> +
> +	if (mux->table)
> +		index = mux->table[index];
> +
> +	mask = GENMASK(mux->width + mux->shift - 1, mux->shift);
> +
> +	if (mix_hwparam_in_sel(common))
> +		ccu_update(sel, common, mask, index << mux->shift);
> +	else
> +		ccu_update(ctrl, common, mask, index << mux->shift);
> +
> +	if (common->reg_type == CLK_DIV_TYPE_1REG_FC_V2 ||
> +	    common->reg_type == CLK_DIV_TYPE_2REG_FC_V4 ||
> +	    common->reg_type == CLK_DIV_TYPE_1REG_FC_MUX_V6)
> +		ret = ccu_mix_trigger_fc(hw);
> +
> +	return ret;
> +}
> +
> +const struct clk_ops spacemit_ccu_mix_ops = {
> +	.disable	 = ccu_mix_disable,
> +	.enable		 = ccu_mix_enable,
> +	.is_enabled	 = ccu_mix_is_enabled,
> +	.get_parent	 = ccu_mix_get_parent,
> +	.set_parent	 = ccu_mix_set_parent,
> +	.determine_rate  = ccu_mix_determine_rate,
> +	.recalc_rate	 = ccu_mix_recalc_rate,
> +	.set_rate	 = ccu_mix_set_rate,
> +};

I think you should separate the clock into different type and
use pre-defined function to simplify, but not use a unified,
complex and hard to read structure to represent all kinds of
clocks.

> +
> diff --git a/drivers/clk/spacemit/ccu_mix.h b/drivers/clk/spacemit/ccu_mix.h
> new file mode 100644
> index 000000000000..c7d91e1c03fd
> --- /dev/null
> +++ b/drivers/clk/spacemit/ccu_mix.h
> @@ -0,0 +1,336 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2024 SpacemiT Technology Co. Ltd
> + * Copyright (c) 2024 Haylen Chu <heylenay@outlook.com>
> + */
> +
> +#ifndef _CCU_MIX_H_
> +#define _CCU_MIX_H_
> +
> +#include <linux/clk-provider.h>
> +
> +#include "ccu_common.h"
> +
> +struct ccu_gate_config {
> +	u32 gate_mask;
> +	u32 val_enable;
> +	u32 val_disable;
> +	u32 flags;
> +};
> +
> +struct ccu_factor_config {
> +	u32 div;
> +	u32 mul;
> +};
> +
> +struct ccu_mux_config {
> +	const u8 *table;
> +	u32 flags;
> +	u8 shift;
> +	u8 width;
> +};
> +
> +struct ccu_div_config {
> +	struct clk_div_table *table;
> +	u32 max;
> +	u32 offset;
> +	u32 flags;
> +	u8 shift;
> +	u8 width;
> +};
> +
> +struct ccu_mix {
> +	struct ccu_factor_config *factor;
> +	struct ccu_gate_config *gate;
> +	struct ccu_div_config *div;
> +	struct ccu_mux_config *mux;
> +	struct ccu_common common;
> +};
> +
> +#define CCU_GATE_INIT(_gate_mask, _val_enable, _val_disable, _flags)		\
> +	(&(struct ccu_gate_config) {						\
> +		.gate_mask   = _gate_mask,					\
> +		.val_enable  = _val_enable,					\
> +		.val_disable = _val_disable,					\
> +		.flags	     = _flags,						\
> +	})
> +
> +#define CCU_FACTOR_INIT(_div, _mul)					\
> +	(&(struct ccu_factor_config) {					\
> +		.div = _div,						\
> +		.mul = _mul,						\
> +	})
> +
> +
> +#define CCU_MUX_INIT(_shift, _width, _table, _flags)			\
> +	(&(struct ccu_mux_config) {					\
> +		.shift	= _shift,					\
> +		.width	= _width,					\
> +		.table	= _table,					\
> +		.flags	= _flags,					\
> +	})
> +
> +#define CCU_DIV_INIT(_shift, _width, _table, _flags)			\
> +	(&(struct ccu_div_config) {					\
> +		.shift	= _shift,					\
> +		.width	= _width,					\
> +		.flags	= _flags,					\
> +		.table	= _table,					\
> +	})
> +
> +#define CCU_PARENT_HW(_parent)		{ .hw = &_parent.common.hw }
> +#define CCU_PARENT_NAME(_name)		{ .fw_name = #_name }
> +
> +#define CCU_MIX_INITHW(_name, _parent, _flags)				\
> +	(&(struct clk_init_data) {					\
> +		.flags		= _flags,				\
> +		.name		= _name,				\
> +		.parent_data	= (const struct clk_parent_data[])	\
> +					{ _parent },			\
> +		.num_parents	= 1,					\
> +		.ops		= &spacemit_ccu_mix_ops,		\
> +	})
> +
> +#define CCU_MIX_INITHW_PARENTS(_name, _parents, _flags)			\
> +	CLK_HW_INIT_PARENTS_DATA(_name, _parents,			\
> +				 &spacemit_ccu_mix_ops, _flags)
> +
> +#define CCU_GATE_DEFINE(_struct, _name, _parent, _reg, _gate_mask,	\
> +			 _val_enable, _val_disable, _flags)		\
> +struct ccu_mix _struct = {						\
> +	.gate	= CCU_GATE_INIT(_gate_mask, _val_enable,		\
> +				_val_disable, 0),			\
> +	.common	= {							\
> +		.reg_ctrl	= _reg,					\
> +		.name		= _name,				\
> +		.num_parents	= 1,					\
> +		.hw.init	= CCU_MIX_INITHW(_name, _parent,	\
> +						 _flags),		\
> +	}								\
> +}
> +
> +#define CCU_FACTOR_DEFINE(_struct, _name, _parent, _div, _mul)		\
> +struct ccu_mix _struct = {						\
> +	.factor	= CCU_FACTOR_INIT(_div, _mul),				\
> +	.common = {							\
> +		.name		= _name,				\
> +		.num_parents	= 1,					\
> +		.hw.init	= CCU_MIX_INITHW(_name, _parent, 0),	\
> +	}								\
> +}
> +
> +#define CCU_MUX_DEFINE(_struct, _name, _parents, _reg, _shift, _width,	\
> +		       _flags)						\
> +struct ccu_mix _struct = {						\
> +	.mux	= CCU_MUX_INIT(_shift, _width, NULL, 0),		\
> +	.common = {							\
> +		.reg_ctrl	= _reg,					\
> +		.name		= _name,				\
> +		.num_parents	= ARRAY_SIZE(_parents),			\
> +		.hw.init = CCU_MIX_INITHW_PARENTS(_name, _parents,	\
> +						  _flags),		\
> +	}								\
> +}
> +
> +#define CCU_DIV_DEFINE(_struct, _name, _parent, _reg, _shift, _width,	\
> +		       _flags)						\
> +struct ccu_mix _struct = {						\
> +	.div	= CCU_DIV_INIT(_shift, _width, NULL, 0),		\
> +	.common = {							\
> +		.reg_ctrl	= _reg,					\
> +		.name		= _name,				\
> +		.num_parents	= 1,					\
> +		.hw.init = CCU_MIX_INITHW(_name, _parent, _flags)	\
> +	}								\
> +}
> +
> +#define CCU_GATE_FACTOR_DEFINE(_struct, _name, _parent, _reg,		\
> +			       _gate_mask, _val_enable, _val_disable,	\
> +			       _div, _mul, _flags)			\
> +struct ccu_mix _struct = {						\
> +	.gate	= CCU_GATE_INIT(_gate_mask, _val_enable,		\
> +				_val_disable, 0),			\
> +	.factor	= CCU_FACTOR_INIT(_div, _mul),				\
> +	.common = {							\
> +		.reg_ctrl	= _reg,					\
> +		.name		= _name,				\
> +		.num_parents	= 1,					\
> +		.hw.init = CCU_MIX_INITHW(_name, _parent, _flags)	\
> +	}								\
> +}
> +
> +
> +#define CCU_MUX_GATE_DEFINE(_struct, _name, _parents, _reg, _shift,	\
> +			    _width, _gate_mask, _val_enable,		\
> +			    _val_disable, _flags)			\
> +struct ccu_mix _struct = {						\
> +	.gate	= CCU_GATE_INIT(_gate_mask, _val_enable,		\
> +				_val_disable, 0),			\
> +	.mux	= CCU_MUX_INIT(_shift, _width, NULL, 0),		\
> +	.common = {							\
> +		.reg_ctrl	= _reg,					\
> +		.name		= _name,				\
> +		.num_parents	= ARRAY_SIZE(_parents),			\
> +		.hw.init = CCU_MIX_INITHW_PARENTS(_name, _parents,	\
> +						  _flags),		\
> +	}								\
> +}
> +
> +#define CCU_DIV_GATE_DEFINE(_struct, _name, _parent, _reg, _shift,	\
> +			    _width, _gate_mask, _val_enable,		\
> +			    _val_disable, _flags)			\
> +struct ccu_mix _struct = {						\
> +	.gate	= CCU_GATE_INIT(_gate_mask, _val_enable,		\
> +				_val_disable, 0),			\
> +	.div	= CCU_DIV_INIT(_shift, _width, NULL, 0),		\
> +	.common = {							\
> +		.reg_ctrl	= _reg,					\
> +		.name		= _name,				\
> +		.num_parents	= 1,					\
> +		.hw.init	= CCU_MIX_INITHW(_name, _parent,	\
> +						 _flags),		\
> +	}								\
> +}
> +
> +
> +#define CCU_DIV_MUX_GATE_DEFINE(_struct, _name, _parents,  _reg_ctrl,	\
> +				_mshift, _mwidth, _muxshift, _muxwidth,	\
> +				_gate_mask, _val_enable, _val_disable,	\
> +				_flags)					\
> +struct ccu_mix _struct = {						\
> +	.gate	= CCU_GATE_INIT(_gate_mask, _val_enable,		\
> +				_val_disable, 0),			\
> +	.div	= CCU_DIV_INIT(_mshift, _mwidth, NULL, 0),		\
> +	.mux	= CCU_MUX_INIT(_muxshift, _muxwidth, NULL, 0),		\
> +	.common	= {							\
> +		.reg_ctrl	= _reg_ctrl,				\
> +		.name		= _name,				\
> +		.num_parents	= ARRAY_SIZE(_parents),			\
> +		.hw.init = CCU_MIX_INITHW_PARENTS(_name, _parents,	\
> +						  _flags),		\
> +	},								\
> +}
> +
> +#define CCU_DIV2_FC_MUX_GATE_DEFINE(_struct, _name, _parents,		\
> +				    _reg_ctrl, _reg_sel, _mshift,	\
> +				    _mwidth, _fc, _muxshift, _muxwidth,	\
> +				    _gate_mask, _val_enable,		\
> +				    _val_disable, _flags)		\
> +struct ccu_mix _struct = {						\
> +	.gate	= CCU_GATE_INIT(_gate_mask, _val_enable,		\
> +				_val_disable, 0),			\
> +	.div	= CCU_DIV_INIT(_mshift, _mwidth, NULL, 0),		\
> +	.mux	= CCU_MUX_INIT(_muxshift, _muxwidth, NULL, 0),		\
> +	.common = {							\
> +	    .reg_type = CLK_DIV_TYPE_2REG_FC_V4,			\
> +		.reg_ctrl	= _reg_ctrl,				\
> +		.reg_sel	= _reg_sel,				\
> +		.fc		= _fc,					\
> +		.name		= _name,				\
> +		.num_parents	= ARRAY_SIZE(_parents),			\
> +		.hw.init = CCU_MIX_INITHW_PARENTS(_name, _parents,	\
> +						  _flags),		\
> +	},								\
> +}
> +
> +
> +#define CCU_DIV_FC_MUX_GATE_DEFINE(_struct, _name, _parents, _reg_ctrl,	\
> +				   _mshift, _mwidth, _fc, _muxshift,	\
> +				   _muxwidth, _gate_mask, _val_enable,	\
> +				   _val_disable, _flags)		\
> +struct ccu_mix _struct = {						\
> +	.gate	= CCU_GATE_INIT(_gate_mask, _val_enable,		\
> +				_val_disable, 0),			\
> +	.div	= CCU_DIV_INIT(_mshift, _mwidth, NULL, 0),		\
> +	.mux	= CCU_MUX_INIT(_muxshift, _muxwidth, NULL, 0),		\
> +	.common = {							\
> +		.reg_type	= CLK_DIV_TYPE_1REG_FC_V2,		\
> +		.reg_ctrl	= _reg_ctrl,				\
> +		.fc		= _fc,					\
> +		.name		= _name,				\
> +		.num_parents	= ARRAY_SIZE(_parents),			\
> +		.hw.init = CCU_MIX_INITHW_PARENTS(_name, _parents,	\
> +						  _flags),		\
> +	},								\
> +}
> +
> +#define CCU_DIV_MFC_MUX_GATE_DEFINE(_struct, _name, _parents,		\
> +				    _reg_ctrl, _mshift, _mwidth, _fc,	\
> +				    _muxshift, _muxwidth, _gate_mask,	\
> +				    _val_enable, _val_disable, _flags)	\
> +struct ccu_mix _struct = {						\
> +	.gate	= CCU_GATE_INIT(_gate_mask, _val_enable,		\
> +				_val_disable, 0),			\
> +	.div	= CCU_DIV_INIT(_mshift, _mwidth, NULL, 0),		\
> +	.mux	= CCU_MUX_INIT(_muxshift, _muxwidth, NULL, 0),		\
> +	.common = {							\
> +		.reg_type = CLK_DIV_TYPE_1REG_FC_MUX_V6,		\
> +		.reg_ctrl	= _reg_ctrl,				\
> +		.fc		= _fc,					\
> +		.name		= _name,				\
> +		.num_parents	= ARRAY_SIZE(_parents),			\
> +		.hw.init = CCU_MIX_INITHW_PARENTS(_name, _parents,	\
> +						  _flags),		\
> +	},								\
> +}
> +
> +#define CCU_DIV_FC_WITH_GATE_DEFINE(_struct, _name, _parent, _reg_ctrl,	\
> +				    _mshift, _mwidth, _fc, _gate_mask,	\
> +				    _val_enable, _val_disable, _flags)	\
> +struct ccu_mix _struct = {						\
> +	.gate	= CCU_GATE_INIT(_gate_mask, _val_enable,		\
> +				_val_disable, 0),			\
> +	.div	= CCU_DIV_INIT(_mshift, _mwidth, NULL, 0),		\
> +	.common = {							\
> +		.reg_type = CLK_DIV_TYPE_1REG_FC_V2,			\
> +		.reg_ctrl	= _reg_ctrl,				\
> +		.fc		= _fc,					\
> +		.name		= _name,				\
> +		.num_parents	= 1,					\
> +		.hw.init	= CCU_MIXINITHW(_name, _parent,		\
> +						_flags),		\
> +	},								\
> +}
> +
> +#define CCU_DIV_FC_MUX_DEFINE(_struct, _name, _parents, _reg_ctrl,	\
> +			      _mshift, _mwidth, _fc, _muxshift,		\
> +			      _muxwidth, _flags)			\
> +struct ccu_mix _struct = {						\
> +	.div	= CCU_DIV_INIT(_mshift, _mwidth, NULL, 0),		\
> +	.mux	= CCU_MUX_INIT(_muxshift, _muxwidth, NULL, 0),		\
> +	.common = {							\
> +		.reg_type	= CLK_DIV_TYPE_1REG_FC_V2,		\
> +		.reg_ctrl	= _reg_ctrl,				\
> +		.fc		= _fc,					\
> +		.name		= _name,				\
> +		.num_parents	= ARRAY_SIZE(_parents),			\
> +		.hw.init = CCU_MIX_INITHW_PARENTS(_name, _parents,	\
> +						  _flags),		\
> +	},								\
> +}
> +
> +#define CCU_MUX_FC_DEFINE(_struct, _name, _parents, _reg_ctrl, _fc,	\
> +			  _muxshift, _muxwidth, _flags)			\
> +struct ccu_mix _struct = {						\
> +	.mux	= CCU_MUX_INIT(_muxshift, _muxwidth, NULL, 0),		\
> +	.common = {							\
> +		.reg_type	= CLK_DIV_TYPE_1REG_FC_V2,		\
> +		.reg_ctrl	= _reg_ctrl,				\
> +		.fc		= _fc,					\
> +		.name		= _name,				\
> +		.num_parents	= ARRAY_SIZE(_parents),			\
> +		.hw.init = CCU_MIX_INITHW_PARENTS(_name, _parents,	\
> +						  _flags)		\
> +	},								\
> +}
> +
> +static inline struct ccu_mix *hw_to_ccu_mix(struct clk_hw *hw)
> +{
> +	struct ccu_common *common = hw_to_ccu_common(hw);
> +
> +	return container_of(common, struct ccu_mix, common);
> +}
> +
> +extern const struct clk_ops spacemit_ccu_mix_ops;
> +
> +#endif /* _CCU_DIV_H_ */
> diff --git a/drivers/clk/spacemit/ccu_pll.c b/drivers/clk/spacemit/ccu_pll.c
> new file mode 100644
> index 000000000000..cf6e547f073b
> --- /dev/null
> +++ b/drivers/clk/spacemit/ccu_pll.c
> @@ -0,0 +1,198 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Spacemit clock type pll
> + *
> + * Copyright (c) 2024 SpacemiT Technology Co. Ltd
> + * Copyright (c) 2024 Haylen Chu <heylenay@outlook.com>
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/regmap.h>
> +
> +#include "ccu_common.h"
> +#include "ccu_pll.h"
> +
> +#define PLL_MIN_FREQ	600000000
> +#define PLL_MAX_FREQ	3400000000
> +#define PLL_DELAY_TIME	3000
> +
> +#define PLL_SWCR1_REG5_OFF	0
> +#define PLL_SWCR1_REG5_MASK	GENMASK(7, 0)
> +#define PLL_SWCR1_REG6_OFF	8
> +#define PLL_SWCR1_REG6_MASK	GENMASK(15, 8)
> +#define PLL_SWCR1_REG7_OFF	16
> +#define PLL_SWCR1_REG7_MASK	GENMASK(23, 16)
> +#define PLL_SWCR1_REG8_OFF	24
> +#define PLL_SWCR1_REG8_MASK	GENMASK(31, 24)
> +
> +#define PLL_SWCR2_DIVn_EN(n)	BIT(n + 1)
> +#define PLL_SWCR2_ATEST_EN	BIT(12)
> +#define PLL_SWCR2_CKTEST_EN	BIT(13)
> +#define PLL_SWCR2_DTEST_EN	BIT(14)
> +
> +#define PLL_SWCR3_DIV_FRC_OFF	0
> +#define PLL_SWCR3_DIV_FRC_MASK	GENMASK(23, 0)
> +#define PLL_SWCR3_DIV_INT_OFF	24
> +#define PLL_SWCR3_DIV_INT_MASK	GENMASK(30, 24)
> +#define PLL_SWCR3_EN		BIT(31)
> +
> +static int ccu_pll_is_enabled(struct clk_hw *hw)
> +{
> +	struct ccu_pll *p = hw_to_ccu_pll(hw);
> +	u32 tmp;
> +
> +	ccu_read(swcr3, &p->common, &tmp);
> +
> +	return tmp & PLL_SWCR3_EN;
> +}
> +
> +/* frequency unit Mhz, return pll vco freq */
> +static unsigned long __get_vco_freq(struct clk_hw *hw)

It is better to use ccu_pll_get_vco_freq.

> +{
> +	unsigned int reg5, reg6, reg7, reg8, size, i;
> +	unsigned int div_int, div_frc;
> +	struct ccu_pll_rate_tbl *freq_pll_regs_table;
> +	struct ccu_pll *p = hw_to_ccu_pll(hw);
> +	struct ccu_common *common = &p->common;
> +	u32 tmp;
> +
> +	ccu_read(swcr1, common, &tmp);
> +	reg5 = (tmp & PLL_SWCR1_REG5_MASK) >> PLL_SWCR1_REG5_OFF;
> +	reg6 = (tmp & PLL_SWCR1_REG6_MASK) >> PLL_SWCR1_REG6_OFF;
> +	reg7 = (tmp & PLL_SWCR1_REG7_MASK) >> PLL_SWCR1_REG7_OFF;
> +	reg8 = (tmp & PLL_SWCR1_REG8_MASK) >> PLL_SWCR1_REG8_OFF;
> +
> +	ccu_read(swcr3, common, &tmp);
> +	div_int = (tmp & PLL_SWCR3_DIV_INT_MASK) >> PLL_SWCR3_DIV_INT_OFF;
> +	div_frc = (tmp & PLL_SWCR3_DIV_FRC_MASK) >> PLL_SWCR3_DIV_FRC_OFF;
> +
> +	freq_pll_regs_table = p->pll.rate_tbl;
> +	size = p->pll.tbl_size;
> +
> +	for (i = 0; i < size; i++)
> +		if ((freq_pll_regs_table[i].reg5 == reg5) &&
> +		    (freq_pll_regs_table[i].reg6 == reg6) &&
> +		    (freq_pll_regs_table[i].reg7 == reg7) &&
> +		    (freq_pll_regs_table[i].reg8 == reg8) &&
> +		    (freq_pll_regs_table[i].div_int == div_int) &&
> +		    (freq_pll_regs_table[i].div_frac == div_frc))
> +			return freq_pll_regs_table[i].rate;
> +
> +	WARN_ON_ONCE(1);
> +
> +	return 0;
> +}
> +
> +static int ccu_pll_enable(struct clk_hw *hw)
> +{
> +	struct ccu_pll *p = hw_to_ccu_pll(hw);
> +	struct ccu_common *common = &p->common;
> +	unsigned int tmp;
> +	int ret;
> +
> +	if (ccu_pll_is_enabled(hw))
> +		return 0;
> +
> +	ccu_update(swcr3, common, PLL_SWCR3_EN, PLL_SWCR3_EN);
> +
> +	/* check lock status */
> +	ret = regmap_read_poll_timeout_atomic(common->lock_base,
> +					      p->pll.reg_lock,
> +					      tmp,
> +					      tmp & p->pll.lock_enable_bit,
> +					      5, PLL_DELAY_TIME);
> +
> +	return ret;
> +}
> +
> +static void ccu_pll_disable(struct clk_hw *hw)
> +{
> +	struct ccu_pll *p = hw_to_ccu_pll(hw);
> +	struct ccu_common *common = &p->common;
> +
> +	ccu_update(swcr3, common, PLL_SWCR3_EN, 0);
> +}
> +
> +/*
> + * pll rate change requires sequence:
> + * clock off -> change rate setting -> clock on
> + * This function doesn't really change rate, but cache the config
> + */
> +static int ccu_pll_set_rate(struct clk_hw *hw, unsigned long rate,
> +			       unsigned long parent_rate)
> +{
> +	struct ccu_pll *p = hw_to_ccu_pll(hw);
> +	struct ccu_common *common = &p->common;
> +	struct ccu_pll_config *params = &p->pll;
> +	struct ccu_pll_rate_tbl *entry;
> +	unsigned long old_rate;
> +	bool found = false;
> +	u32 mask, val;
> +	int i;
> +
> +	if (ccu_pll_is_enabled(hw)) {
> +		pr_err("%s %s is enabled, ignore the setrate!\n",
> +		       __func__, __clk_get_name(hw->clk));

Just use clk_hw_get_name.

> +		return 0;
> +	}
> +
> +	old_rate = __get_vco_freq(hw);
> +
> +	for (i = 0; i < params->tbl_size; i++) {
> +		if (rate == params->rate_tbl[i].rate) {
> +			found = true;
> +			entry = &params->rate_tbl[i];
> +			break;
> +		}
> +	}
> +	WARN_ON_ONCE(!found);
> +
> +	mask = PLL_SWCR1_REG5_MASK | PLL_SWCR1_REG6_MASK;
> +	mask |= PLL_SWCR1_REG7_MASK | PLL_SWCR1_REG8_MASK;
> +	val |= entry->reg5 << PLL_SWCR1_REG5_OFF;
> +	val |= entry->reg6 << PLL_SWCR1_REG6_OFF;
> +	val |= entry->reg7 << PLL_SWCR1_REG7_OFF;
> +	val |= entry->reg8 << PLL_SWCR1_REG8_OFF;
> +	ccu_update(swcr1, common, mask, val);
> +
> +	mask = PLL_SWCR3_DIV_INT_MASK | PLL_SWCR3_DIV_FRC_MASK;
> +	val = entry->div_int << PLL_SWCR3_DIV_INT_OFF;
> +	val |= entry->div_frac << PLL_SWCR3_DIV_FRC_OFF;
> +	ccu_update(swcr3, common, mask, val);
> +
> +	return 0;
> +}
> +
> +static unsigned long ccu_pll_recalc_rate(struct clk_hw *hw,
> +					 unsigned long parent_rate)
> +{
> +	return __get_vco_freq(hw);
> +}
> +
> +static long ccu_pll_round_rate(struct clk_hw *hw, unsigned long rate,
> +			       unsigned long *prate)
> +{
> +	struct ccu_pll *p = hw_to_ccu_pll(hw);
> +	struct ccu_pll_config *params = &p->pll;
> +	unsigned long max_rate = 0;
> +	unsigned int i;
> +
> +	for (i = 0; i < params->tbl_size; i++) {
> +		if (params->rate_tbl[i].rate <= rate) {
> +			if (max_rate < params->rate_tbl[i].rate)
> +				max_rate = params->rate_tbl[i].rate;
> +		}
> +	}
> +
> +	return MAX(max_rate, PLL_MIN_FREQ);
> +}
> +
> +const struct clk_ops spacemit_ccu_pll_ops = {
> +	.enable		= ccu_pll_enable,
> +	.disable	= ccu_pll_disable,
> +	.set_rate	= ccu_pll_set_rate,
> +	.recalc_rate	= ccu_pll_recalc_rate,
> +	.round_rate	= ccu_pll_round_rate,
> +	.is_enabled	= ccu_pll_is_enabled,
> +};
> +
> diff --git a/drivers/clk/spacemit/ccu_pll.h b/drivers/clk/spacemit/ccu_pll.h
> new file mode 100644
> index 000000000000..a2252e79ff4a
> --- /dev/null
> +++ b/drivers/clk/spacemit/ccu_pll.h
> @@ -0,0 +1,80 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2024 SpacemiT Technology Co. Ltd
> + * Copyright (c) 2024 Haylen Chu <heylenay@outlook.com>
> + */
> +
> +#ifndef _CCU_PLL_H_
> +#define _CCU_PLL_H_
> +
> +#include <linux/clk-provider.h>
> +
> +#include "ccu_common.h"
> +
> +struct ccu_pll_rate_tbl {
> +	unsigned long long rate;
> +	u32 reg5;
> +	u32 reg6;
> +	u32 reg7;
> +	u32 reg8;
> +	unsigned int div_int;
> +	unsigned int div_frac;
> +};
> +
> +struct ccu_pll_config {
> +	struct ccu_pll_rate_tbl *rate_tbl;
> +	u32 tbl_size;
> +	u32 reg_lock;
> +	u32 lock_enable_bit;
> +};
> +
> +#define CCU_PLL_RATE(_rate, _reg5, _reg6, _reg7, _reg8, _div_int, _div_frac) \
> +	{									\
> +		.rate		= (_rate),					\
> +		.reg5		= (_reg5),					\
> +		.reg6		= (_reg6),					\
> +		.reg7		= (_reg7),					\
> +		.reg8		= (_reg8),					\
> +		.div_int	= (_div_int),				\
> +		.div_frac	= (_div_frac),				\
> +	}
> +
> +struct ccu_pll {
> +	struct ccu_pll_config	pll;
> +	struct ccu_common	common;
> +};
> +
> +#define CCU_PLL_CONFIG(_table, _reg_lock, _lock_enable_bit) \
> +	{									\
> +		.rate_tbl	 = (struct ccu_pll_rate_tbl *)&(_table),	\
> +		.tbl_size	 = ARRAY_SIZE(_table),				\
> +		.reg_lock	 = (_reg_lock),					\
> +		.lock_enable_bit = (_lock_enable_bit),				\
> +	}
> +
> +#define CCU_PLL_HWINIT(_name, _flags) \
> +	CLK_HW_INIT_NO_PARENT(_name, &spacemit_ccu_pll_ops, _flags)
> +
> +#define CCU_PLL_DEFINE(_struct, _name, _table, _reg_swcr1, _reg_swcr2,	\
> +		       _reg_swcr3, _reg_lock, _lock_enable_bit, _flags)		\
> +										\
> +	struct ccu_pll _struct = {						\
> +		.pll	= CCU_PLL_CONFIG(_table, _reg_lock, _lock_enable_bit),	\
> +		.common = {							\
> +			.reg_swcr1	= _reg_swcr1,				\
> +			.reg_swcr2	= _reg_swcr2,				\
> +			.reg_swcr3	= _reg_swcr3,				\
> +			.hw.init	= CCU_PLL_HWINIT(_name, _flags)		\
> +		}								\
> +	}
> +
> +static inline struct ccu_pll *hw_to_ccu_pll(struct clk_hw *hw)
> +{
> +	struct ccu_common *common = hw_to_ccu_common(hw);
> +
> +	return container_of(common, struct ccu_pll, common);
> +}
> +
> +extern const struct clk_ops spacemit_ccu_pll_ops;
> +
> +#endif
> -- 
> 2.47.0
> 
> 

Re: [PATCH v3 3/3] clk: spacemit: Add clock support for Spacemit K1 SoC

[Yixun Lan]

On 14:47 Sun 08 Dec     , Inochi Amaoto wrote:
> On Tue, Nov 26, 2024 at 02:31:28PM +0000, Haylen Chu wrote:
> > The clock tree of K1 SoC contains three main types of clock hardware
> > (PLL/DDN/MIX) and is managed by several independent controllers in
> > different SoC parts (APBC, APBS and etc.), thus different compatible
> > strings are added to distinguish them.
> > 
> > Some controllers may share IO region with reset controller and other low
> > speed peripherals like watchdog, so all register operations are done
> > through regmap to avoid competition.
> > 
> > Signed-off-by: Haylen Chu <heylenay@4d2.org>
> > ---
> >  drivers/clk/Kconfig               |    1 +
> >  drivers/clk/Makefile              |    1 +
> >  drivers/clk/spacemit/Kconfig      |   20 +
> >  drivers/clk/spacemit/Makefile     |    5 +
> >  drivers/clk/spacemit/ccu-k1.c     | 1747 +++++++++++++++++++++++++++++
> >  drivers/clk/spacemit/ccu_common.h |   62 +
> >  drivers/clk/spacemit/ccu_ddn.c    |  146 +++
> >  drivers/clk/spacemit/ccu_ddn.h    |   85 ++
> >  drivers/clk/spacemit/ccu_mix.c    |  296 +++++
> >  drivers/clk/spacemit/ccu_mix.h    |  336 ++++++
> >  drivers/clk/spacemit/ccu_pll.c    |  198 ++++
> >  drivers/clk/spacemit/ccu_pll.h    |   80 ++
....snip
> > diff --git a/drivers/clk/spacemit/ccu_mix.c b/drivers/clk/spacemit/ccu_mix.c
> > new file mode 100644
> > index 000000000000..de343405fcc7
> > --- /dev/null
> > +++ b/drivers/clk/spacemit/ccu_mix.c
> > @@ -0,0 +1,296 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Spacemit clock type mix(div/mux/gate/factor)
> > + *
> > + * Copyright (c) 2024 SpacemiT Technology Co. Ltd
> > + * Copyright (c) 2024 Haylen Chu <heylenay@outlook.com>
> > + */
> > +
> > +#include <linux/clk-provider.h>
> > +
> > +#include "ccu_mix.h"
> > +
> > +#define MIX_TIMEOUT	10000
> > +
> > +#define mix_hwparam_in_sel(c) \
> > +	((c)->reg_type == CLK_DIV_TYPE_2REG_NOFC_V3 || \
> > +	 (c)->reg_type == CLK_DIV_TYPE_2REG_FC_V4)
> > +
> 
> > +static void ccu_mix_disable(struct clk_hw *hw)
> > +{
> > +	struct ccu_mix *mix = hw_to_ccu_mix(hw);
> > +	struct ccu_common *common = &mix->common;
> > +	struct ccu_gate_config *gate = mix->gate;
> > +
> > +	if (!gate)
> > +		return;
> > +
> > +	if (mix_hwparam_in_sel(common))
> > +		ccu_update(sel, common, gate->gate_mask, gate->val_disable);
> > +	else
> > +		ccu_update(ctrl, common, gate->gate_mask, gate->val_disable);
> > +}
> > +
> > +static int ccu_mix_enable(struct clk_hw *hw)
> > +{
> > +	struct ccu_mix *mix = hw_to_ccu_mix(hw);
> > +	struct ccu_common *common = &mix->common;
> > +	struct ccu_gate_config *gate = mix->gate;
> > +	u32 val_enable, mask;
> > +	u32 tmp;
> > +
> > +	if (!gate)
> > +		return 0;
> > +
> > +	val_enable	= gate->val_enable;
> > +	mask		= gate->gate_mask;
> > +
> > +	if (mix_hwparam_in_sel(common))
> > +		ccu_update(sel, common, mask, val_enable);
> > +	else
> > +		ccu_update(ctrl, common, mask, val_enable);
> > +
> > +	if (common->reg_type == CLK_DIV_TYPE_2REG_NOFC_V3 ||
> > +	    common->reg_type == CLK_DIV_TYPE_2REG_FC_V4)
> > +		return ccu_poll(sel, common, tmp, (tmp & mask) == val_enable,
> > +				10, MIX_TIMEOUT);
> > +	else
> > +		return ccu_poll(ctrl, common, tmp, (tmp & mask) == val_enable,
> > +				10, MIX_TIMEOUT);
> > +}
> > +
> > +static int ccu_mix_is_enabled(struct clk_hw *hw)
> > +{
> > +	struct ccu_mix *mix = hw_to_ccu_mix(hw);
> > +	struct ccu_common *common = &mix->common;
> > +	struct ccu_gate_config *gate = mix->gate;
> > +	u32 tmp;
> > +
> > +	if (!gate)
> > +		return 1;
> > +
> > +	if (mix_hwparam_in_sel(common))
> > +		ccu_read(sel, common, &tmp);
> > +	else
> > +		ccu_read(ctrl, common, &tmp);
> > +
> > +	return (tmp & gate->gate_mask) == gate->val_enable;
> > +}
> > +
> > +static unsigned long ccu_mix_recalc_rate(struct clk_hw *hw,
> > +					unsigned long parent_rate)
> > +{
> > +	struct ccu_mix *mix = hw_to_ccu_mix(hw);
> > +	struct ccu_common *common = &mix->common;
> > +	struct ccu_div_config *div = mix->div;
> > +	unsigned long val;
> > +	u32 reg;
> > +
> > +	if (!div) {
> > +		if (mix->factor)
> > +			return parent_rate * mix->factor->mul / mix->factor->div;
> > +
> > +		return parent_rate;
> > +	}
> > +
> > +	if (mix_hwparam_in_sel(common))
> > +		ccu_read(sel, common, &reg);
> > +	else
> > +		ccu_read(ctrl, common, &reg);
> > +
> > +	val = reg >> div->shift;
> > +	val &= (1 << div->width) - 1;
> > +
> > +	val = divider_recalc_rate(hw, parent_rate, val, div->table,
> > +				  div->flags, div->width);
> > +
> > +	return val;
> > +}
> 
> I think you should distinguish these muxs, it is not good to
> use mix_hwparam_in_sel everywhere. There are two types of mux.
> 
> > +
> > +
> 
> Double empty line here, you should run checkpatch.
> 
> > +static int ccu_mix_trigger_fc(struct clk_hw *hw)
> > +{
> > +	struct ccu_mix *mix = hw_to_ccu_mix(hw);
> > +	struct ccu_common *common = &mix->common;
> > +	unsigned int val = 0;
> > +	int ret = 0;
> > +
> > +	if (common->reg_type == CLK_DIV_TYPE_1REG_FC_V2 ||
> > +	    common->reg_type == CLK_DIV_TYPE_2REG_FC_V4 ||
> > +	    common->reg_type == CLK_DIV_TYPE_1REG_FC_DIV_V5 ||
> > +	    common->reg_type == CLK_DIV_TYPE_1REG_FC_MUX_V6) {
> > +		ccu_update(ctrl, common, common->fc, common->fc);
> > +
> > +		ret = ccu_poll(ctrl, common, val, !(val & common->fc),
> > +			       5, MIX_TIMEOUT);
> > +	}
> > +
> > +	return ret;
> > +}
> > +
> > +static int ccu_mix_determine_rate(struct clk_hw *hw,
> > +				  struct clk_rate_request *req)
> > +{
> > +	return 0;
> > +}
> > +
> 
> Why a empty determine_rate function?
> 
> > +static unsigned long
> > +ccu_mix_calc_best_rate(struct clk_hw *hw, unsigned long rate, u32 *mux_val,
> > +		       u32 *div_val)
> > +{
> > +	struct ccu_mix *mix = hw_to_ccu_mix(hw);
> > +	struct ccu_common *common = &mix->common;
> > +	struct ccu_div_config *div = mix->div ? mix->div : NULL;
> > +	struct clk_hw *parent;
> > +	unsigned long parent_rate = 0, best_rate = 0;
> > +	u32 i, j, div_max;
> > +
> > +	for (i = 0; i < common->num_parents; i++) {
> > +		parent = clk_hw_get_parent_by_index(hw, i);
> > +		if (!parent)
> > +			continue;
> > +
> > +		parent_rate = clk_hw_get_rate(parent);
> > +
> > +		if (div)
> > +			div_max = 1 << div->width;
> > +		else
> > +			div_max = 1;
> > +
> > +		for (j = 1; j <= div_max; j++) {
> > +			if (abs(parent_rate/j - rate) < abs(best_rate - rate)) {
> > +				best_rate = DIV_ROUND_UP_ULL(parent_rate, j);
> > +				*mux_val = i;
> > +				*div_val = j - 1;
> > +			}
> > +		}
> > +	}
> > +
> > +	return best_rate;
> > +}
> > +
> > +static int ccu_mix_set_rate(struct clk_hw *hw, unsigned long rate,
> > +			   unsigned long parent_rate)
> > +{
> > +	struct ccu_mix *mix = hw_to_ccu_mix(hw);
> > +	struct ccu_common *common = &mix->common;
> > +	struct ccu_div_config *div = mix->div;
> > +	struct ccu_mux_config *mux = mix->mux;
> > +	u32 cur_mux, cur_div, mux_val = 0, div_val = 0;
> > +	unsigned long best_rate = 0;
> > +	int ret = 0, tmp = 0;
> > +
> > +	if (!div && !mux)
> > +		return 0;
> > +
> > +	best_rate = ccu_mix_calc_best_rate(hw, rate, &mux_val, &div_val);
> > +
> > +	if (mix_hwparam_in_sel(common))
> > +		ccu_read(sel, common, &tmp);
> > +	else
> > +		ccu_read(ctrl, common, &tmp);
> > +
> > +	if (mux) {
> > +		cur_mux = tmp >> mux->shift;
> > +		cur_mux &= (1 << mux->width) - 1;
> > +
> > +		if (cur_mux != mux_val)
> > +			clk_hw_set_parent(hw, clk_hw_get_parent_by_index(hw, mux_val));
> > +	}
> > +
> > +	if (div) {
> > +		cur_div = tmp >> div->shift;
> > +		cur_div &= (1 << div->width) - 1;
> > +
> > +		if (cur_div == div_val)
> > +			return 0;
> > +	} else {
> > +		return 0;
> > +	}
> > +
> > +	tmp = GENMASK(div->width + div->shift - 1, div->shift);
> > +
> > +	if (mix_hwparam_in_sel(common))
> > +		ccu_update(sel, common, tmp, div_val << div->shift);
> > +	else
> > +		ccu_update(ctrl, common, tmp, div_val << div->shift);
> > +
> > +	if (common->reg_type == CLK_DIV_TYPE_1REG_FC_V2 ||
> > +	    common->reg_type == CLK_DIV_TYPE_2REG_FC_V4 ||
> > +	    common->reg_type == CLK_DIV_TYPE_1REG_FC_DIV_V5)
> > +		ret = ccu_mix_trigger_fc(hw);
> > +
> > +	return ret;
> > +}
> > +
> > +static u8 ccu_mix_get_parent(struct clk_hw *hw)
> > +{
> > +	struct ccu_mix *mix = hw_to_ccu_mix(hw);
> > +	struct ccu_common *common = &mix->common;
> > +	struct ccu_mux_config *mux = mix->mux;
> > +	u32 reg;
> > +	u8 parent;
> > +
> > +	if (!mux)
> > +		return 0;
> > +
> > +	if (mix_hwparam_in_sel(common))
> > +		ccu_read(sel, common, &reg);
> > +	else
> > +		ccu_read(ctrl, common, &reg);
> > +
> > +	parent = reg >> mux->shift;
> > +	parent &= (1 << mux->width) - 1;
> > +
> > +	if (mux->table) {
> > +		int num_parents = clk_hw_get_num_parents(&common->hw);
> > +		int i;
> > +
> > +		for (i = 0; i < num_parents; i++)
> > +			if (mux->table[i] == parent)
> > +				return i;
> > +	}
> > +
> > +	return parent;
> > +}
> > +
> > +static int ccu_mix_set_parent(struct clk_hw *hw, u8 index)
> > +{
> > +	struct ccu_mix *mix = hw_to_ccu_mix(hw);
> > +	struct ccu_common *common = &mix->common;
> > +	struct ccu_mux_config *mux = mix->mux;
> > +	int ret = 0;
> > +	u32 mask;
> > +
> > +	if (!mux)
> > +		return 0;
> > +
> > +	if (mux->table)
> > +		index = mux->table[index];
> > +
> > +	mask = GENMASK(mux->width + mux->shift - 1, mux->shift);
> > +
> > +	if (mix_hwparam_in_sel(common))
> > +		ccu_update(sel, common, mask, index << mux->shift);
> > +	else
> > +		ccu_update(ctrl, common, mask, index << mux->shift);
> > +
> > +	if (common->reg_type == CLK_DIV_TYPE_1REG_FC_V2 ||
> > +	    common->reg_type == CLK_DIV_TYPE_2REG_FC_V4 ||
> > +	    common->reg_type == CLK_DIV_TYPE_1REG_FC_MUX_V6)
> > +		ret = ccu_mix_trigger_fc(hw);
> > +
> > +	return ret;
> > +}
> > +
> > +const struct clk_ops spacemit_ccu_mix_ops = {
> > +	.disable	 = ccu_mix_disable,
> > +	.enable		 = ccu_mix_enable,
> > +	.is_enabled	 = ccu_mix_is_enabled,
> > +	.get_parent	 = ccu_mix_get_parent,
> > +	.set_parent	 = ccu_mix_set_parent,
> > +	.determine_rate  = ccu_mix_determine_rate,
> > +	.recalc_rate	 = ccu_mix_recalc_rate,
> > +	.set_rate	 = ccu_mix_set_rate,
> > +};
> 
> I think you should separate the clock into different type and
> use pre-defined function to simplify, but not use a unified,
> complex and hard to read structure to represent all kinds of
> clocks.
> 
agree

I'd not object to use composite clock, it simplify the implementation,
but, in this version, there is lots of "if" conditions which make it
hard to review and maintain..

would it possibile to use more basic clk prototype? or just the composite
model[1] or something similar as owl-composite.c [2] which has more fine
composite prototype (instead of bundling all in one)

drivers/clk/clk-composite.c [1]
drivers/clk/actions/owl-composite.c [2]

> > +
> > diff --git a/drivers/clk/spacemit/ccu_mix.h b/drivers/clk/spacemit/ccu_mix.h
> > new file mode 100644
> > index 000000000000..c7d91e1c03fd
> > --- /dev/null
> > +++ b/drivers/clk/spacemit/ccu_mix.h
> > @@ -0,0 +1,336 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Copyright (c) 2024 SpacemiT Technology Co. Ltd
> > + * Copyright (c) 2024 Haylen Chu <heylenay@outlook.com>
> > + */
> > +
> > +#ifndef _CCU_MIX_H_
> > +#define _CCU_MIX_H_
> > +
> > +#include <linux/clk-provider.h>
> > +
> > +#include "ccu_common.h"
> > +
> > +struct ccu_gate_config {
> > +	u32 gate_mask;
> > +	u32 val_enable;
> > +	u32 val_disable;
> > +	u32 flags;
> > +};
> > +
> > +struct ccu_factor_config {
> > +	u32 div;
> > +	u32 mul;
> > +};
> > +
> > +struct ccu_mux_config {
> > +	const u8 *table;
> > +	u32 flags;
> > +	u8 shift;
> > +	u8 width;
> > +};
> > +
> > +struct ccu_div_config {
> > +	struct clk_div_table *table;
> > +	u32 max;
> > +	u32 offset;
> > +	u32 flags;
> > +	u8 shift;
> > +	u8 width;
> > +};
> > +
> > +struct ccu_mix {
> > +	struct ccu_factor_config *factor;
> > +	struct ccu_gate_config *gate;
> > +	struct ccu_div_config *div;
> > +	struct ccu_mux_config *mux;
> > +	struct ccu_common common;
> > +};
> > +
> > +#define CCU_GATE_INIT(_gate_mask, _val_enable, _val_disable, _flags)		\
> > +	(&(struct ccu_gate_config) {						\
> > +		.gate_mask   = _gate_mask,					\
> > +		.val_enable  = _val_enable,					\
> > +		.val_disable = _val_disable,					\
> > +		.flags	     = _flags,						\
> > +	})
> > +
> > +#define CCU_FACTOR_INIT(_div, _mul)					\
> > +	(&(struct ccu_factor_config) {					\
> > +		.div = _div,						\
> > +		.mul = _mul,						\
> > +	})
> > +
> > +
> > +#define CCU_MUX_INIT(_shift, _width, _table, _flags)			\
> > +	(&(struct ccu_mux_config) {					\
> > +		.shift	= _shift,					\
> > +		.width	= _width,					\
> > +		.table	= _table,					\
> > +		.flags	= _flags,					\
> > +	})
> > +
> > +#define CCU_DIV_INIT(_shift, _width, _table, _flags)			\
> > +	(&(struct ccu_div_config) {					\
> > +		.shift	= _shift,					\
> > +		.width	= _width,					\
> > +		.flags	= _flags,					\
> > +		.table	= _table,					\
> > +	})
> > +
> > +#define CCU_PARENT_HW(_parent)		{ .hw = &_parent.common.hw }
> > +#define CCU_PARENT_NAME(_name)		{ .fw_name = #_name }
> > +
> > +#define CCU_MIX_INITHW(_name, _parent, _flags)				\
> > +	(&(struct clk_init_data) {					\
> > +		.flags		= _flags,				\
> > +		.name		= _name,				\
> > +		.parent_data	= (const struct clk_parent_data[])	\
> > +					{ _parent },			\
> > +		.num_parents	= 1,					\
> > +		.ops		= &spacemit_ccu_mix_ops,		\
> > +	})
> > +
> > +#define CCU_MIX_INITHW_PARENTS(_name, _parents, _flags)			\
> > +	CLK_HW_INIT_PARENTS_DATA(_name, _parents,			\
> > +				 &spacemit_ccu_mix_ops, _flags)
> > +
> > +#define CCU_GATE_DEFINE(_struct, _name, _parent, _reg, _gate_mask,	\
> > +			 _val_enable, _val_disable, _flags)		\
> > +struct ccu_mix _struct = {						\
> > +	.gate	= CCU_GATE_INIT(_gate_mask, _val_enable,		\
> > +				_val_disable, 0),			\
> > +	.common	= {							\
> > +		.reg_ctrl	= _reg,					\
> > +		.name		= _name,				\
> > +		.num_parents	= 1,					\
> > +		.hw.init	= CCU_MIX_INITHW(_name, _parent,	\
> > +						 _flags),		\
> > +	}								\
> > +}
> > +
> > +#define CCU_FACTOR_DEFINE(_struct, _name, _parent, _div, _mul)		\
> > +struct ccu_mix _struct = {						\
> > +	.factor	= CCU_FACTOR_INIT(_div, _mul),				\
> > +	.common = {							\
> > +		.name		= _name,				\
> > +		.num_parents	= 1,					\
> > +		.hw.init	= CCU_MIX_INITHW(_name, _parent, 0),	\
> > +	}								\
> > +}
> > +
> > +#define CCU_MUX_DEFINE(_struct, _name, _parents, _reg, _shift, _width,	\
> > +		       _flags)						\
> > +struct ccu_mix _struct = {						\
> > +	.mux	= CCU_MUX_INIT(_shift, _width, NULL, 0),		\
> > +	.common = {							\
> > +		.reg_ctrl	= _reg,					\
> > +		.name		= _name,				\
> > +		.num_parents	= ARRAY_SIZE(_parents),			\
> > +		.hw.init = CCU_MIX_INITHW_PARENTS(_name, _parents,	\
> > +						  _flags),		\
> > +	}								\
> > +}
> > +
> > +#define CCU_DIV_DEFINE(_struct, _name, _parent, _reg, _shift, _width,	\
> > +		       _flags)						\
> > +struct ccu_mix _struct = {						\
> > +	.div	= CCU_DIV_INIT(_shift, _width, NULL, 0),		\
> > +	.common = {							\
> > +		.reg_ctrl	= _reg,					\
> > +		.name		= _name,				\
> > +		.num_parents	= 1,					\
> > +		.hw.init = CCU_MIX_INITHW(_name, _parent, _flags)	\
> > +	}								\
> > +}
> > +
> > +#define CCU_GATE_FACTOR_DEFINE(_struct, _name, _parent, _reg,		\
> > +			       _gate_mask, _val_enable, _val_disable,	\
> > +			       _div, _mul, _flags)			\
> > +struct ccu_mix _struct = {						\
> > +	.gate	= CCU_GATE_INIT(_gate_mask, _val_enable,		\
> > +				_val_disable, 0),			\
> > +	.factor	= CCU_FACTOR_INIT(_div, _mul),				\
> > +	.common = {							\
> > +		.reg_ctrl	= _reg,					\
> > +		.name		= _name,				\
> > +		.num_parents	= 1,					\
> > +		.hw.init = CCU_MIX_INITHW(_name, _parent, _flags)	\
> > +	}								\
> > +}
> > +
> > +
> > +#define CCU_MUX_GATE_DEFINE(_struct, _name, _parents, _reg, _shift,	\
> > +			    _width, _gate_mask, _val_enable,		\
> > +			    _val_disable, _flags)			\
> > +struct ccu_mix _struct = {						\
> > +	.gate	= CCU_GATE_INIT(_gate_mask, _val_enable,		\
> > +				_val_disable, 0),			\
> > +	.mux	= CCU_MUX_INIT(_shift, _width, NULL, 0),		\
> > +	.common = {							\
> > +		.reg_ctrl	= _reg,					\
> > +		.name		= _name,				\
> > +		.num_parents	= ARRAY_SIZE(_parents),			\
> > +		.hw.init = CCU_MIX_INITHW_PARENTS(_name, _parents,	\
> > +						  _flags),		\
> > +	}								\
> > +}
> > +
> > +#define CCU_DIV_GATE_DEFINE(_struct, _name, _parent, _reg, _shift,	\
> > +			    _width, _gate_mask, _val_enable,		\
> > +			    _val_disable, _flags)			\
> > +struct ccu_mix _struct = {						\
> > +	.gate	= CCU_GATE_INIT(_gate_mask, _val_enable,		\
> > +				_val_disable, 0),			\
> > +	.div	= CCU_DIV_INIT(_shift, _width, NULL, 0),		\
> > +	.common = {							\
> > +		.reg_ctrl	= _reg,					\
> > +		.name		= _name,				\
> > +		.num_parents	= 1,					\
> > +		.hw.init	= CCU_MIX_INITHW(_name, _parent,	\
> > +						 _flags),		\
> > +	}								\
> > +}
> > +
> > +
> > +#define CCU_DIV_MUX_GATE_DEFINE(_struct, _name, _parents,  _reg_ctrl,	\
> > +				_mshift, _mwidth, _muxshift, _muxwidth,	\
> > +				_gate_mask, _val_enable, _val_disable,	\
> > +				_flags)					\
> > +struct ccu_mix _struct = {						\
> > +	.gate	= CCU_GATE_INIT(_gate_mask, _val_enable,		\
> > +				_val_disable, 0),			\
> > +	.div	= CCU_DIV_INIT(_mshift, _mwidth, NULL, 0),		\
> > +	.mux	= CCU_MUX_INIT(_muxshift, _muxwidth, NULL, 0),		\
> > +	.common	= {							\
> > +		.reg_ctrl	= _reg_ctrl,				\
> > +		.name		= _name,				\
> > +		.num_parents	= ARRAY_SIZE(_parents),			\
> > +		.hw.init = CCU_MIX_INITHW_PARENTS(_name, _parents,	\
> > +						  _flags),		\
> > +	},								\
> > +}
> > +
> > +#define CCU_DIV2_FC_MUX_GATE_DEFINE(_struct, _name, _parents,		\
> > +				    _reg_ctrl, _reg_sel, _mshift,	\
> > +				    _mwidth, _fc, _muxshift, _muxwidth,	\
> > +				    _gate_mask, _val_enable,		\
> > +				    _val_disable, _flags)		\
> > +struct ccu_mix _struct = {						\
> > +	.gate	= CCU_GATE_INIT(_gate_mask, _val_enable,		\
> > +				_val_disable, 0),			\
> > +	.div	= CCU_DIV_INIT(_mshift, _mwidth, NULL, 0),		\
> > +	.mux	= CCU_MUX_INIT(_muxshift, _muxwidth, NULL, 0),		\
> > +	.common = {							\
> > +	    .reg_type = CLK_DIV_TYPE_2REG_FC_V4,			\
> > +		.reg_ctrl	= _reg_ctrl,				\
> > +		.reg_sel	= _reg_sel,				\
> > +		.fc		= _fc,					\
> > +		.name		= _name,				\
> > +		.num_parents	= ARRAY_SIZE(_parents),			\
> > +		.hw.init = CCU_MIX_INITHW_PARENTS(_name, _parents,	\
> > +						  _flags),		\
> > +	},								\
> > +}
> > +
> > +
> > +#define CCU_DIV_FC_MUX_GATE_DEFINE(_struct, _name, _parents, _reg_ctrl,	\
> > +				   _mshift, _mwidth, _fc, _muxshift,	\
> > +				   _muxwidth, _gate_mask, _val_enable,	\
> > +				   _val_disable, _flags)		\
> > +struct ccu_mix _struct = {						\
> > +	.gate	= CCU_GATE_INIT(_gate_mask, _val_enable,		\
> > +				_val_disable, 0),			\
> > +	.div	= CCU_DIV_INIT(_mshift, _mwidth, NULL, 0),		\
> > +	.mux	= CCU_MUX_INIT(_muxshift, _muxwidth, NULL, 0),		\
> > +	.common = {							\
> > +		.reg_type	= CLK_DIV_TYPE_1REG_FC_V2,		\
> > +		.reg_ctrl	= _reg_ctrl,				\
> > +		.fc		= _fc,					\
> > +		.name		= _name,				\
> > +		.num_parents	= ARRAY_SIZE(_parents),			\
> > +		.hw.init = CCU_MIX_INITHW_PARENTS(_name, _parents,	\
> > +						  _flags),		\
> > +	},								\
> > +}
> > +
> > +#define CCU_DIV_MFC_MUX_GATE_DEFINE(_struct, _name, _parents,		\
> > +				    _reg_ctrl, _mshift, _mwidth, _fc,	\
> > +				    _muxshift, _muxwidth, _gate_mask,	\
> > +				    _val_enable, _val_disable, _flags)	\
> > +struct ccu_mix _struct = {						\
> > +	.gate	= CCU_GATE_INIT(_gate_mask, _val_enable,		\
> > +				_val_disable, 0),			\
> > +	.div	= CCU_DIV_INIT(_mshift, _mwidth, NULL, 0),		\
> > +	.mux	= CCU_MUX_INIT(_muxshift, _muxwidth, NULL, 0),		\
> > +	.common = {							\
> > +		.reg_type = CLK_DIV_TYPE_1REG_FC_MUX_V6,		\
> > +		.reg_ctrl	= _reg_ctrl,				\
> > +		.fc		= _fc,					\
> > +		.name		= _name,				\
> > +		.num_parents	= ARRAY_SIZE(_parents),			\
> > +		.hw.init = CCU_MIX_INITHW_PARENTS(_name, _parents,	\
> > +						  _flags),		\
> > +	},								\
> > +}
> > +
> > +#define CCU_DIV_FC_WITH_GATE_DEFINE(_struct, _name, _parent, _reg_ctrl,	\
> > +				    _mshift, _mwidth, _fc, _gate_mask,	\
> > +				    _val_enable, _val_disable, _flags)	\
> > +struct ccu_mix _struct = {						\
> > +	.gate	= CCU_GATE_INIT(_gate_mask, _val_enable,		\
> > +				_val_disable, 0),			\
> > +	.div	= CCU_DIV_INIT(_mshift, _mwidth, NULL, 0),		\
> > +	.common = {							\
> > +		.reg_type = CLK_DIV_TYPE_1REG_FC_V2,			\
> > +		.reg_ctrl	= _reg_ctrl,				\
> > +		.fc		= _fc,					\
> > +		.name		= _name,				\
> > +		.num_parents	= 1,					\
> > +		.hw.init	= CCU_MIXINITHW(_name, _parent,		\
> > +						_flags),		\
> > +	},								\
> > +}
> > +
> > +#define CCU_DIV_FC_MUX_DEFINE(_struct, _name, _parents, _reg_ctrl,	\
> > +			      _mshift, _mwidth, _fc, _muxshift,		\
> > +			      _muxwidth, _flags)			\
> > +struct ccu_mix _struct = {						\
> > +	.div	= CCU_DIV_INIT(_mshift, _mwidth, NULL, 0),		\
> > +	.mux	= CCU_MUX_INIT(_muxshift, _muxwidth, NULL, 0),		\
> > +	.common = {							\
> > +		.reg_type	= CLK_DIV_TYPE_1REG_FC_V2,		\
> > +		.reg_ctrl	= _reg_ctrl,				\
> > +		.fc		= _fc,					\
> > +		.name		= _name,				\
> > +		.num_parents	= ARRAY_SIZE(_parents),			\
> > +		.hw.init = CCU_MIX_INITHW_PARENTS(_name, _parents,	\
> > +						  _flags),		\
> > +	},								\
> > +}
> > +
> > +#define CCU_MUX_FC_DEFINE(_struct, _name, _parents, _reg_ctrl, _fc,	\
> > +			  _muxshift, _muxwidth, _flags)			\
> > +struct ccu_mix _struct = {						\
> > +	.mux	= CCU_MUX_INIT(_muxshift, _muxwidth, NULL, 0),		\
> > +	.common = {							\
> > +		.reg_type	= CLK_DIV_TYPE_1REG_FC_V2,		\
> > +		.reg_ctrl	= _reg_ctrl,				\
> > +		.fc		= _fc,					\
> > +		.name		= _name,				\
> > +		.num_parents	= ARRAY_SIZE(_parents),			\
> > +		.hw.init = CCU_MIX_INITHW_PARENTS(_name, _parents,	\
> > +						  _flags)		\
> > +	},								\
> > +}
> > +
> > +static inline struct ccu_mix *hw_to_ccu_mix(struct clk_hw *hw)
> > +{
> > +	struct ccu_common *common = hw_to_ccu_common(hw);
> > +
> > +	return container_of(common, struct ccu_mix, common);
> > +}
> > +
> > +extern const struct clk_ops spacemit_ccu_mix_ops;
> > +
> > +#endif /* _CCU_DIV_H_ */
> > diff --git a/drivers/clk/spacemit/ccu_pll.c b/drivers/clk/spacemit/ccu_pll.c
> > new file mode 100644
> > index 000000000000..cf6e547f073b
> > --- /dev/null
> > +++ b/drivers/clk/spacemit/ccu_pll.c
> > @@ -0,0 +1,198 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Spacemit clock type pll
> > + *
> > + * Copyright (c) 2024 SpacemiT Technology Co. Ltd
> > + * Copyright (c) 2024 Haylen Chu <heylenay@outlook.com>
> > + */
> > +
> > +#include <linux/clk-provider.h>
> > +#include <linux/regmap.h>
> > +
> > +#include "ccu_common.h"
> > +#include "ccu_pll.h"
> > +
> > +#define PLL_MIN_FREQ	600000000
> > +#define PLL_MAX_FREQ	3400000000
> > +#define PLL_DELAY_TIME	3000
> > +
> > +#define PLL_SWCR1_REG5_OFF	0
> > +#define PLL_SWCR1_REG5_MASK	GENMASK(7, 0)
> > +#define PLL_SWCR1_REG6_OFF	8
> > +#define PLL_SWCR1_REG6_MASK	GENMASK(15, 8)
> > +#define PLL_SWCR1_REG7_OFF	16
> > +#define PLL_SWCR1_REG7_MASK	GENMASK(23, 16)
> > +#define PLL_SWCR1_REG8_OFF	24
> > +#define PLL_SWCR1_REG8_MASK	GENMASK(31, 24)
> > +
> > +#define PLL_SWCR2_DIVn_EN(n)	BIT(n + 1)
> > +#define PLL_SWCR2_ATEST_EN	BIT(12)
> > +#define PLL_SWCR2_CKTEST_EN	BIT(13)
> > +#define PLL_SWCR2_DTEST_EN	BIT(14)
> > +
> > +#define PLL_SWCR3_DIV_FRC_OFF	0
> > +#define PLL_SWCR3_DIV_FRC_MASK	GENMASK(23, 0)
> > +#define PLL_SWCR3_DIV_INT_OFF	24
> > +#define PLL_SWCR3_DIV_INT_MASK	GENMASK(30, 24)
> > +#define PLL_SWCR3_EN		BIT(31)
> > +
> > +static int ccu_pll_is_enabled(struct clk_hw *hw)
> > +{
> > +	struct ccu_pll *p = hw_to_ccu_pll(hw);
> > +	u32 tmp;
> > +
> > +	ccu_read(swcr3, &p->common, &tmp);
> > +
> > +	return tmp & PLL_SWCR3_EN;
> > +}
> > +
> > +/* frequency unit Mhz, return pll vco freq */
> > +static unsigned long __get_vco_freq(struct clk_hw *hw)
> 
> It is better to use ccu_pll_get_vco_freq.
> 
> > +{
> > +	unsigned int reg5, reg6, reg7, reg8, size, i;
> > +	unsigned int div_int, div_frc;
> > +	struct ccu_pll_rate_tbl *freq_pll_regs_table;
> > +	struct ccu_pll *p = hw_to_ccu_pll(hw);
> > +	struct ccu_common *common = &p->common;
> > +	u32 tmp;
> > +
> > +	ccu_read(swcr1, common, &tmp);
> > +	reg5 = (tmp & PLL_SWCR1_REG5_MASK) >> PLL_SWCR1_REG5_OFF;
> > +	reg6 = (tmp & PLL_SWCR1_REG6_MASK) >> PLL_SWCR1_REG6_OFF;
> > +	reg7 = (tmp & PLL_SWCR1_REG7_MASK) >> PLL_SWCR1_REG7_OFF;
> > +	reg8 = (tmp & PLL_SWCR1_REG8_MASK) >> PLL_SWCR1_REG8_OFF;
> > +
> > +	ccu_read(swcr3, common, &tmp);
> > +	div_int = (tmp & PLL_SWCR3_DIV_INT_MASK) >> PLL_SWCR3_DIV_INT_OFF;
> > +	div_frc = (tmp & PLL_SWCR3_DIV_FRC_MASK) >> PLL_SWCR3_DIV_FRC_OFF;
> > +
> > +	freq_pll_regs_table = p->pll.rate_tbl;
> > +	size = p->pll.tbl_size;
> > +
> > +	for (i = 0; i < size; i++)
> > +		if ((freq_pll_regs_table[i].reg5 == reg5) &&
> > +		    (freq_pll_regs_table[i].reg6 == reg6) &&
> > +		    (freq_pll_regs_table[i].reg7 == reg7) &&
> > +		    (freq_pll_regs_table[i].reg8 == reg8) &&
> > +		    (freq_pll_regs_table[i].div_int == div_int) &&
> > +		    (freq_pll_regs_table[i].div_frac == div_frc))
> > +			return freq_pll_regs_table[i].rate;
> > +
> > +	WARN_ON_ONCE(1);
> > +
> > +	return 0;
> > +}
> > +
> > +static int ccu_pll_enable(struct clk_hw *hw)
> > +{
> > +	struct ccu_pll *p = hw_to_ccu_pll(hw);
> > +	struct ccu_common *common = &p->common;
> > +	unsigned int tmp;
> > +	int ret;
> > +
> > +	if (ccu_pll_is_enabled(hw))
> > +		return 0;
> > +
> > +	ccu_update(swcr3, common, PLL_SWCR3_EN, PLL_SWCR3_EN);
> > +
> > +	/* check lock status */
> > +	ret = regmap_read_poll_timeout_atomic(common->lock_base,
> > +					      p->pll.reg_lock,
> > +					      tmp,
> > +					      tmp & p->pll.lock_enable_bit,
> > +					      5, PLL_DELAY_TIME);
> > +
> > +	return ret;
> > +}
> > +
> > +static void ccu_pll_disable(struct clk_hw *hw)
> > +{
> > +	struct ccu_pll *p = hw_to_ccu_pll(hw);
> > +	struct ccu_common *common = &p->common;
> > +
> > +	ccu_update(swcr3, common, PLL_SWCR3_EN, 0);
> > +}
> > +
> > +/*
> > + * pll rate change requires sequence:
> > + * clock off -> change rate setting -> clock on
> > + * This function doesn't really change rate, but cache the config
> > + */
> > +static int ccu_pll_set_rate(struct clk_hw *hw, unsigned long rate,
> > +			       unsigned long parent_rate)
> > +{
> > +	struct ccu_pll *p = hw_to_ccu_pll(hw);
> > +	struct ccu_common *common = &p->common;
> > +	struct ccu_pll_config *params = &p->pll;
> > +	struct ccu_pll_rate_tbl *entry;
> > +	unsigned long old_rate;
> > +	bool found = false;
> > +	u32 mask, val;
> > +	int i;
> > +
> > +	if (ccu_pll_is_enabled(hw)) {
> > +		pr_err("%s %s is enabled, ignore the setrate!\n",
> > +		       __func__, __clk_get_name(hw->clk));
> 
> Just use clk_hw_get_name.
> 
> > +		return 0;
> > +	}
> > +
> > +	old_rate = __get_vco_freq(hw);
> > +
> > +	for (i = 0; i < params->tbl_size; i++) {
> > +		if (rate == params->rate_tbl[i].rate) {
> > +			found = true;
> > +			entry = &params->rate_tbl[i];
> > +			break;
> > +		}
> > +	}
> > +	WARN_ON_ONCE(!found);
> > +
> > +	mask = PLL_SWCR1_REG5_MASK | PLL_SWCR1_REG6_MASK;
> > +	mask |= PLL_SWCR1_REG7_MASK | PLL_SWCR1_REG8_MASK;
> > +	val |= entry->reg5 << PLL_SWCR1_REG5_OFF;
> > +	val |= entry->reg6 << PLL_SWCR1_REG6_OFF;
> > +	val |= entry->reg7 << PLL_SWCR1_REG7_OFF;
> > +	val |= entry->reg8 << PLL_SWCR1_REG8_OFF;
> > +	ccu_update(swcr1, common, mask, val);
> > +
> > +	mask = PLL_SWCR3_DIV_INT_MASK | PLL_SWCR3_DIV_FRC_MASK;
> > +	val = entry->div_int << PLL_SWCR3_DIV_INT_OFF;
> > +	val |= entry->div_frac << PLL_SWCR3_DIV_FRC_OFF;
> > +	ccu_update(swcr3, common, mask, val);
> > +
> > +	return 0;
> > +}
> > +
> > +static unsigned long ccu_pll_recalc_rate(struct clk_hw *hw,
> > +					 unsigned long parent_rate)
> > +{
> > +	return __get_vco_freq(hw);
> > +}
> > +
> > +static long ccu_pll_round_rate(struct clk_hw *hw, unsigned long rate,
> > +			       unsigned long *prate)
> > +{
> > +	struct ccu_pll *p = hw_to_ccu_pll(hw);
> > +	struct ccu_pll_config *params = &p->pll;
> > +	unsigned long max_rate = 0;
> > +	unsigned int i;
> > +
> > +	for (i = 0; i < params->tbl_size; i++) {
> > +		if (params->rate_tbl[i].rate <= rate) {
> > +			if (max_rate < params->rate_tbl[i].rate)
> > +				max_rate = params->rate_tbl[i].rate;
> > +		}
> > +	}
> > +
> > +	return MAX(max_rate, PLL_MIN_FREQ);
> > +}
> > +
> > +const struct clk_ops spacemit_ccu_pll_ops = {
> > +	.enable		= ccu_pll_enable,
> > +	.disable	= ccu_pll_disable,
> > +	.set_rate	= ccu_pll_set_rate,
> > +	.recalc_rate	= ccu_pll_recalc_rate,
> > +	.round_rate	= ccu_pll_round_rate,
> > +	.is_enabled	= ccu_pll_is_enabled,
> > +};
> > +
> > diff --git a/drivers/clk/spacemit/ccu_pll.h b/drivers/clk/spacemit/ccu_pll.h
> > new file mode 100644
> > index 000000000000..a2252e79ff4a
> > --- /dev/null
> > +++ b/drivers/clk/spacemit/ccu_pll.h
> > @@ -0,0 +1,80 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Copyright (c) 2024 SpacemiT Technology Co. Ltd
> > + * Copyright (c) 2024 Haylen Chu <heylenay@outlook.com>
> > + */
> > +
> > +#ifndef _CCU_PLL_H_
> > +#define _CCU_PLL_H_
> > +
> > +#include <linux/clk-provider.h>
> > +
> > +#include "ccu_common.h"
> > +
> > +struct ccu_pll_rate_tbl {
> > +	unsigned long long rate;
> > +	u32 reg5;
> > +	u32 reg6;
> > +	u32 reg7;
> > +	u32 reg8;
> > +	unsigned int div_int;
> > +	unsigned int div_frac;
> > +};
> > +
> > +struct ccu_pll_config {
> > +	struct ccu_pll_rate_tbl *rate_tbl;
> > +	u32 tbl_size;
> > +	u32 reg_lock;
> > +	u32 lock_enable_bit;
> > +};
> > +
> > +#define CCU_PLL_RATE(_rate, _reg5, _reg6, _reg7, _reg8, _div_int, _div_frac) \
> > +	{									\
> > +		.rate		= (_rate),					\
> > +		.reg5		= (_reg5),					\
> > +		.reg6		= (_reg6),					\
> > +		.reg7		= (_reg7),					\
> > +		.reg8		= (_reg8),					\
> > +		.div_int	= (_div_int),				\
> > +		.div_frac	= (_div_frac),				\
> > +	}
> > +
> > +struct ccu_pll {
> > +	struct ccu_pll_config	pll;
> > +	struct ccu_common	common;
> > +};
> > +
> > +#define CCU_PLL_CONFIG(_table, _reg_lock, _lock_enable_bit) \
> > +	{									\
> > +		.rate_tbl	 = (struct ccu_pll_rate_tbl *)&(_table),	\
> > +		.tbl_size	 = ARRAY_SIZE(_table),				\
> > +		.reg_lock	 = (_reg_lock),					\
> > +		.lock_enable_bit = (_lock_enable_bit),				\
> > +	}
> > +
> > +#define CCU_PLL_HWINIT(_name, _flags) \
> > +	CLK_HW_INIT_NO_PARENT(_name, &spacemit_ccu_pll_ops, _flags)
> > +
> > +#define CCU_PLL_DEFINE(_struct, _name, _table, _reg_swcr1, _reg_swcr2,	\
> > +		       _reg_swcr3, _reg_lock, _lock_enable_bit, _flags)		\
> > +										\
> > +	struct ccu_pll _struct = {						\
> > +		.pll	= CCU_PLL_CONFIG(_table, _reg_lock, _lock_enable_bit),	\
> > +		.common = {							\
> > +			.reg_swcr1	= _reg_swcr1,				\
> > +			.reg_swcr2	= _reg_swcr2,				\
> > +			.reg_swcr3	= _reg_swcr3,				\
> > +			.hw.init	= CCU_PLL_HWINIT(_name, _flags)		\
> > +		}								\
> > +	}
> > +
> > +static inline struct ccu_pll *hw_to_ccu_pll(struct clk_hw *hw)
> > +{
> > +	struct ccu_common *common = hw_to_ccu_common(hw);
> > +
> > +	return container_of(common, struct ccu_pll, common);
> > +}
> > +
> > +extern const struct clk_ops spacemit_ccu_pll_ops;
> > +
> > +#endif
> > -- 
> > 2.47.0
> > 
> > 

-- 
Yixun Lan (dlan)
Gentoo Linux Developer
GPG Key ID AABEFD55

Re: [PATCH v3 3/3] clk: spacemit: Add clock support for Spacemit K1 SoC

[Inochi Amaoto]

On Wed, Dec 18, 2024 at 03:27:27PM +0800, Yixun Lan wrote:
> On 14:47 Sun 08 Dec     , Inochi Amaoto wrote:
> > On Tue, Nov 26, 2024 at 02:31:28PM +0000, Haylen Chu wrote:
> > > The clock tree of K1 SoC contains three main types of clock hardware
> > > (PLL/DDN/MIX) and is managed by several independent controllers in
> > > different SoC parts (APBC, APBS and etc.), thus different compatible
> > > strings are added to distinguish them.
> > > 
> > > Some controllers may share IO region with reset controller and other low
> > > speed peripherals like watchdog, so all register operations are done
> > > through regmap to avoid competition.
> > > 
> > > Signed-off-by: Haylen Chu <heylenay@4d2.org>
> > > ---
> > >  drivers/clk/Kconfig               |    1 +
> > >  drivers/clk/Makefile              |    1 +
> > >  drivers/clk/spacemit/Kconfig      |   20 +
> > >  drivers/clk/spacemit/Makefile     |    5 +
> > >  drivers/clk/spacemit/ccu-k1.c     | 1747 +++++++++++++++++++++++++++++
> > >  drivers/clk/spacemit/ccu_common.h |   62 +
> > >  drivers/clk/spacemit/ccu_ddn.c    |  146 +++
> > >  drivers/clk/spacemit/ccu_ddn.h    |   85 ++
> > >  drivers/clk/spacemit/ccu_mix.c    |  296 +++++
> > >  drivers/clk/spacemit/ccu_mix.h    |  336 ++++++
> > >  drivers/clk/spacemit/ccu_pll.c    |  198 ++++
> > >  drivers/clk/spacemit/ccu_pll.h    |   80 ++
> ....snip
> > > diff --git a/drivers/clk/spacemit/ccu_mix.c b/drivers/clk/spacemit/ccu_mix.c
> > > new file mode 100644
> > > index 000000000000..de343405fcc7
> > > --- /dev/null
> > > +++ b/drivers/clk/spacemit/ccu_mix.c
> > > @@ -0,0 +1,296 @@
> > > +// SPDX-License-Identifier: GPL-2.0-only
> > > +/*
> > > + * Spacemit clock type mix(div/mux/gate/factor)
> > > + *
> > > + * Copyright (c) 2024 SpacemiT Technology Co. Ltd
> > > + * Copyright (c) 2024 Haylen Chu <heylenay@outlook.com>
> > > + */
> > > +
> > > +#include <linux/clk-provider.h>
> > > +
> > > +#include "ccu_mix.h"
> > > +
> > > +#define MIX_TIMEOUT	10000
> > > +
> > > +#define mix_hwparam_in_sel(c) \
> > > +	((c)->reg_type == CLK_DIV_TYPE_2REG_NOFC_V3 || \
> > > +	 (c)->reg_type == CLK_DIV_TYPE_2REG_FC_V4)
> > > +
> > 
> > > +static void ccu_mix_disable(struct clk_hw *hw)
> > > +{
> > > +	struct ccu_mix *mix = hw_to_ccu_mix(hw);
> > > +	struct ccu_common *common = &mix->common;
> > > +	struct ccu_gate_config *gate = mix->gate;
> > > +
> > > +	if (!gate)
> > > +		return;
> > > +
> > > +	if (mix_hwparam_in_sel(common))
> > > +		ccu_update(sel, common, gate->gate_mask, gate->val_disable);
> > > +	else
> > > +		ccu_update(ctrl, common, gate->gate_mask, gate->val_disable);
> > > +}
> > > +
> > > +static int ccu_mix_enable(struct clk_hw *hw)
> > > +{
> > > +	struct ccu_mix *mix = hw_to_ccu_mix(hw);
> > > +	struct ccu_common *common = &mix->common;
> > > +	struct ccu_gate_config *gate = mix->gate;
> > > +	u32 val_enable, mask;
> > > +	u32 tmp;
> > > +
> > > +	if (!gate)
> > > +		return 0;
> > > +
> > > +	val_enable	= gate->val_enable;
> > > +	mask		= gate->gate_mask;
> > > +
> > > +	if (mix_hwparam_in_sel(common))
> > > +		ccu_update(sel, common, mask, val_enable);
> > > +	else
> > > +		ccu_update(ctrl, common, mask, val_enable);
> > > +
> > > +	if (common->reg_type == CLK_DIV_TYPE_2REG_NOFC_V3 ||
> > > +	    common->reg_type == CLK_DIV_TYPE_2REG_FC_V4)
> > > +		return ccu_poll(sel, common, tmp, (tmp & mask) == val_enable,
> > > +				10, MIX_TIMEOUT);
> > > +	else
> > > +		return ccu_poll(ctrl, common, tmp, (tmp & mask) == val_enable,
> > > +				10, MIX_TIMEOUT);
> > > +}
> > > +
> > > +static int ccu_mix_is_enabled(struct clk_hw *hw)
> > > +{
> > > +	struct ccu_mix *mix = hw_to_ccu_mix(hw);
> > > +	struct ccu_common *common = &mix->common;
> > > +	struct ccu_gate_config *gate = mix->gate;
> > > +	u32 tmp;
> > > +
> > > +	if (!gate)
> > > +		return 1;
> > > +
> > > +	if (mix_hwparam_in_sel(common))
> > > +		ccu_read(sel, common, &tmp);
> > > +	else
> > > +		ccu_read(ctrl, common, &tmp);
> > > +
> > > +	return (tmp & gate->gate_mask) == gate->val_enable;
> > > +}
> > > +
> > > +static unsigned long ccu_mix_recalc_rate(struct clk_hw *hw,
> > > +					unsigned long parent_rate)
> > > +{
> > > +	struct ccu_mix *mix = hw_to_ccu_mix(hw);
> > > +	struct ccu_common *common = &mix->common;
> > > +	struct ccu_div_config *div = mix->div;
> > > +	unsigned long val;
> > > +	u32 reg;
> > > +
> > > +	if (!div) {
> > > +		if (mix->factor)
> > > +			return parent_rate * mix->factor->mul / mix->factor->div;
> > > +
> > > +		return parent_rate;
> > > +	}
> > > +
> > > +	if (mix_hwparam_in_sel(common))
> > > +		ccu_read(sel, common, &reg);
> > > +	else
> > > +		ccu_read(ctrl, common, &reg);
> > > +
> > > +	val = reg >> div->shift;
> > > +	val &= (1 << div->width) - 1;
> > > +
> > > +	val = divider_recalc_rate(hw, parent_rate, val, div->table,
> > > +				  div->flags, div->width);
> > > +
> > > +	return val;
> > > +}
> > 
> > I think you should distinguish these muxs, it is not good to
> > use mix_hwparam_in_sel everywhere. There are two types of mux.
> > 
> > > +
> > > +
> > 
> > Double empty line here, you should run checkpatch.
> > 
> > > +static int ccu_mix_trigger_fc(struct clk_hw *hw)
> > > +{
> > > +	struct ccu_mix *mix = hw_to_ccu_mix(hw);
> > > +	struct ccu_common *common = &mix->common;
> > > +	unsigned int val = 0;
> > > +	int ret = 0;
> > > +
> > > +	if (common->reg_type == CLK_DIV_TYPE_1REG_FC_V2 ||
> > > +	    common->reg_type == CLK_DIV_TYPE_2REG_FC_V4 ||
> > > +	    common->reg_type == CLK_DIV_TYPE_1REG_FC_DIV_V5 ||
> > > +	    common->reg_type == CLK_DIV_TYPE_1REG_FC_MUX_V6) {
> > > +		ccu_update(ctrl, common, common->fc, common->fc);
> > > +
> > > +		ret = ccu_poll(ctrl, common, val, !(val & common->fc),
> > > +			       5, MIX_TIMEOUT);
> > > +	}
> > > +
> > > +	return ret;
> > > +}
> > > +
> > > +static int ccu_mix_determine_rate(struct clk_hw *hw,
> > > +				  struct clk_rate_request *req)
> > > +{
> > > +	return 0;
> > > +}
> > > +
> > 
> > Why a empty determine_rate function?
> > 
> > > +static unsigned long
> > > +ccu_mix_calc_best_rate(struct clk_hw *hw, unsigned long rate, u32 *mux_val,
> > > +		       u32 *div_val)
> > > +{
> > > +	struct ccu_mix *mix = hw_to_ccu_mix(hw);
> > > +	struct ccu_common *common = &mix->common;
> > > +	struct ccu_div_config *div = mix->div ? mix->div : NULL;
> > > +	struct clk_hw *parent;
> > > +	unsigned long parent_rate = 0, best_rate = 0;
> > > +	u32 i, j, div_max;
> > > +
> > > +	for (i = 0; i < common->num_parents; i++) {
> > > +		parent = clk_hw_get_parent_by_index(hw, i);
> > > +		if (!parent)
> > > +			continue;
> > > +
> > > +		parent_rate = clk_hw_get_rate(parent);
> > > +
> > > +		if (div)
> > > +			div_max = 1 << div->width;
> > > +		else
> > > +			div_max = 1;
> > > +
> > > +		for (j = 1; j <= div_max; j++) {
> > > +			if (abs(parent_rate/j - rate) < abs(best_rate - rate)) {
> > > +				best_rate = DIV_ROUND_UP_ULL(parent_rate, j);
> > > +				*mux_val = i;
> > > +				*div_val = j - 1;
> > > +			}
> > > +		}
> > > +	}
> > > +
> > > +	return best_rate;
> > > +}
> > > +
> > > +static int ccu_mix_set_rate(struct clk_hw *hw, unsigned long rate,
> > > +			   unsigned long parent_rate)
> > > +{
> > > +	struct ccu_mix *mix = hw_to_ccu_mix(hw);
> > > +	struct ccu_common *common = &mix->common;
> > > +	struct ccu_div_config *div = mix->div;
> > > +	struct ccu_mux_config *mux = mix->mux;
> > > +	u32 cur_mux, cur_div, mux_val = 0, div_val = 0;
> > > +	unsigned long best_rate = 0;
> > > +	int ret = 0, tmp = 0;
> > > +
> > > +	if (!div && !mux)
> > > +		return 0;
> > > +
> > > +	best_rate = ccu_mix_calc_best_rate(hw, rate, &mux_val, &div_val);
> > > +
> > > +	if (mix_hwparam_in_sel(common))
> > > +		ccu_read(sel, common, &tmp);
> > > +	else
> > > +		ccu_read(ctrl, common, &tmp);
> > > +
> > > +	if (mux) {
> > > +		cur_mux = tmp >> mux->shift;
> > > +		cur_mux &= (1 << mux->width) - 1;
> > > +
> > > +		if (cur_mux != mux_val)
> > > +			clk_hw_set_parent(hw, clk_hw_get_parent_by_index(hw, mux_val));
> > > +	}
> > > +
> > > +	if (div) {
> > > +		cur_div = tmp >> div->shift;
> > > +		cur_div &= (1 << div->width) - 1;
> > > +
> > > +		if (cur_div == div_val)
> > > +			return 0;
> > > +	} else {
> > > +		return 0;
> > > +	}
> > > +
> > > +	tmp = GENMASK(div->width + div->shift - 1, div->shift);
> > > +
> > > +	if (mix_hwparam_in_sel(common))
> > > +		ccu_update(sel, common, tmp, div_val << div->shift);
> > > +	else
> > > +		ccu_update(ctrl, common, tmp, div_val << div->shift);
> > > +
> > > +	if (common->reg_type == CLK_DIV_TYPE_1REG_FC_V2 ||
> > > +	    common->reg_type == CLK_DIV_TYPE_2REG_FC_V4 ||
> > > +	    common->reg_type == CLK_DIV_TYPE_1REG_FC_DIV_V5)
> > > +		ret = ccu_mix_trigger_fc(hw);
> > > +
> > > +	return ret;
> > > +}
> > > +
> > > +static u8 ccu_mix_get_parent(struct clk_hw *hw)
> > > +{
> > > +	struct ccu_mix *mix = hw_to_ccu_mix(hw);
> > > +	struct ccu_common *common = &mix->common;
> > > +	struct ccu_mux_config *mux = mix->mux;
> > > +	u32 reg;
> > > +	u8 parent;
> > > +
> > > +	if (!mux)
> > > +		return 0;
> > > +
> > > +	if (mix_hwparam_in_sel(common))
> > > +		ccu_read(sel, common, &reg);
> > > +	else
> > > +		ccu_read(ctrl, common, &reg);
> > > +
> > > +	parent = reg >> mux->shift;
> > > +	parent &= (1 << mux->width) - 1;
> > > +
> > > +	if (mux->table) {
> > > +		int num_parents = clk_hw_get_num_parents(&common->hw);
> > > +		int i;
> > > +
> > > +		for (i = 0; i < num_parents; i++)
> > > +			if (mux->table[i] == parent)
> > > +				return i;
> > > +	}
> > > +
> > > +	return parent;
> > > +}
> > > +
> > > +static int ccu_mix_set_parent(struct clk_hw *hw, u8 index)
> > > +{
> > > +	struct ccu_mix *mix = hw_to_ccu_mix(hw);
> > > +	struct ccu_common *common = &mix->common;
> > > +	struct ccu_mux_config *mux = mix->mux;
> > > +	int ret = 0;
> > > +	u32 mask;
> > > +
> > > +	if (!mux)
> > > +		return 0;
> > > +
> > > +	if (mux->table)
> > > +		index = mux->table[index];
> > > +
> > > +	mask = GENMASK(mux->width + mux->shift - 1, mux->shift);
> > > +
> > > +	if (mix_hwparam_in_sel(common))
> > > +		ccu_update(sel, common, mask, index << mux->shift);
> > > +	else
> > > +		ccu_update(ctrl, common, mask, index << mux->shift);
> > > +
> > > +	if (common->reg_type == CLK_DIV_TYPE_1REG_FC_V2 ||
> > > +	    common->reg_type == CLK_DIV_TYPE_2REG_FC_V4 ||
> > > +	    common->reg_type == CLK_DIV_TYPE_1REG_FC_MUX_V6)
> > > +		ret = ccu_mix_trigger_fc(hw);
> > > +
> > > +	return ret;
> > > +}
> > > +
> > > +const struct clk_ops spacemit_ccu_mix_ops = {
> > > +	.disable	 = ccu_mix_disable,
> > > +	.enable		 = ccu_mix_enable,
> > > +	.is_enabled	 = ccu_mix_is_enabled,
> > > +	.get_parent	 = ccu_mix_get_parent,
> > > +	.set_parent	 = ccu_mix_set_parent,
> > > +	.determine_rate  = ccu_mix_determine_rate,
> > > +	.recalc_rate	 = ccu_mix_recalc_rate,
> > > +	.set_rate	 = ccu_mix_set_rate,
> > > +};
> > 
> > I think you should separate the clock into different type and
> > use pre-defined function to simplify, but not use a unified,
> > complex and hard to read structure to represent all kinds of
> > clocks.
> > 
> agree
> 
> I'd not object to use composite clock, it simplify the implementation,
> but, in this version, there is lots of "if" conditions which make it
> hard to review and maintain..
> 
> would it possibile to use more basic clk prototype? or just the composite
> model[1] or something similar as owl-composite.c [2] which has more fine
> composite prototype (instead of bundling all in one)
> 
> drivers/clk/clk-composite.c [1]
> drivers/clk/actions/owl-composite.c [2]
> 

This depends on what you clock is. I guest this mix has a all in one
register to perform mix/div/gate. If so, it is better to provide multiple
clk_ops to adopt the real one. Otherwise, it will be better to use
different clk type to represent the real clock.

Regards,
Inochi

Re: [PATCH v3 3/3] clk: spacemit: Add clock support for Spacemit K1 SoC

[Haylen Chu]

On Sun, Dec 08, 2024 at 02:47:43PM +0800, Inochi Amaoto wrote:
> On Tue, Nov 26, 2024 at 02:31:28PM +0000, Haylen Chu wrote:
> > The clock tree of K1 SoC contains three main types of clock hardware
> > (PLL/DDN/MIX) and is managed by several independent controllers in
> > different SoC parts (APBC, APBS and etc.), thus different compatible
> > strings are added to distinguish them.
> > 
> > Some controllers may share IO region with reset controller and other low
> > speed peripherals like watchdog, so all register operations are done
> > through regmap to avoid competition.
> > 
> > Signed-off-by: Haylen Chu <heylenay@4d2.org>
> > ---
> >  drivers/clk/Kconfig               |    1 +
> >  drivers/clk/Makefile              |    1 +
> >  drivers/clk/spacemit/Kconfig      |   20 +
> >  drivers/clk/spacemit/Makefile     |    5 +
> >  drivers/clk/spacemit/ccu-k1.c     | 1747 +++++++++++++++++++++++++++++
> >  drivers/clk/spacemit/ccu_common.h |   62 +
> >  drivers/clk/spacemit/ccu_ddn.c    |  146 +++
> >  drivers/clk/spacemit/ccu_ddn.h    |   85 ++
> >  drivers/clk/spacemit/ccu_mix.c    |  296 +++++
> >  drivers/clk/spacemit/ccu_mix.h    |  336 ++++++
> >  drivers/clk/spacemit/ccu_pll.c    |  198 ++++
> >  drivers/clk/spacemit/ccu_pll.h    |   80 ++
> >  12 files changed, 2977 insertions(+)
> >  create mode 100644 drivers/clk/spacemit/Kconfig
> >  create mode 100644 drivers/clk/spacemit/Makefile
> >  create mode 100644 drivers/clk/spacemit/ccu-k1.c
> >  create mode 100644 drivers/clk/spacemit/ccu_common.h
> >  create mode 100644 drivers/clk/spacemit/ccu_ddn.c
> >  create mode 100644 drivers/clk/spacemit/ccu_ddn.h
> >  create mode 100644 drivers/clk/spacemit/ccu_mix.c
> >  create mode 100644 drivers/clk/spacemit/ccu_mix.h
> >  create mode 100644 drivers/clk/spacemit/ccu_pll.c
> >  create mode 100644 drivers/clk/spacemit/ccu_pll.h
> > 
> > diff --git a/drivers/clk/spacemit/ccu_common.h b/drivers/clk/spacemit/ccu_common.h
> > new file mode 100644
> > index 000000000000..9910fb69bc9e
> > --- /dev/null
> > +++ b/drivers/clk/spacemit/ccu_common.h
> > @@ -0,0 +1,62 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Copyright (c) 2024 SpacemiT Technology Co. Ltd
> > + * Copyright (c) 2024 Haylen Chu <heylenay@outlook.com>
> > + */
> > +
> > +#ifndef _CCU_COMMON_H_
> > +#define _CCU_COMMON_H_
> > +
> > +#include <linux/regmap.h>
> > +
> > +enum ccu_div_type {
> > +	CLK_DIV_TYPE_1REG_NOFC_V1 = 0,
> > +	CLK_DIV_TYPE_1REG_FC_V2,
> > +	CLK_DIV_TYPE_2REG_NOFC_V3,
> > +	CLK_DIV_TYPE_2REG_FC_V4,
> > +	CLK_DIV_TYPE_1REG_FC_DIV_V5,
> > +	CLK_DIV_TYPE_1REG_FC_MUX_V6,
> > +};
> > +
> > +struct ccu_common {
> > +	struct regmap *base;
> > +	struct regmap *lock_base;
> > +
> > +	enum ccu_div_type reg_type;
> > +
> > +	union {
> > +		struct {
> > +			u32 reg_ctrl;
> > +			u32 reg_sel;
> > +			u32 reg_xtc;
> > +			u32 fc;
> > +		};
> > +		struct {
> > +			u32 reg_swcr1;
> > +			u32 reg_swcr2;
> > +			u32 reg_swcr3;
> > +		};
> > +	};
> > +
> > +	unsigned long flags;
> > +	const char *name;
> > +	const char * const *parent_names;
> > +	int num_parents;
> > +
> > +	struct clk_hw hw;
> > +};
> > +
> > +static inline struct ccu_common *hw_to_ccu_common(struct clk_hw *hw)
> > +{
> > +	return container_of(hw, struct ccu_common, hw);
> > +}
> > +
> > +#define ccu_read(reg, c, val)	regmap_read((c)->base, (c)->reg_##reg, val)
> > +#define ccu_write(reg, c, val)	regmap_write((c)->base, (c)->reg_##reg, val)
> > +#define ccu_update(reg, c, mask, val) \
> > +	regmap_update_bits((c)->base, (c)->reg_##reg, mask, val)
> > +#define ccu_poll(reg, c, tmp, cond, sleep, timeout) \
> > +	regmap_read_poll_timeout_atomic((c)->base, (c)->reg_##reg,	\
> > +					tmp, cond, sleep, timeout)
> > +
> > +#endif /* _CCU_COMMON_H_ */
> > diff --git a/drivers/clk/spacemit/ccu_ddn.c b/drivers/clk/spacemit/ccu_ddn.c
> > new file mode 100644
> > index 000000000000..7a68652676ce
> > --- /dev/null
> > +++ b/drivers/clk/spacemit/ccu_ddn.c
> > @@ -0,0 +1,146 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Spacemit clock type ddn
> > + *
> > + * Copyright (c) 2024 SpacemiT Technology Co. Ltd
> > + * Copyright (c) 2024 Haylen Chu <heylenay@outlook.com>
> > + */
> > +
> > +#include <linux/clk-provider.h>
> > +
> > +#include "ccu_ddn.h"
> > +
> > +/*
> > + * It is M/N clock
> > + *
> > + * Fout from synthesizer can be given from two equations:
> > + * numerator/denominator = Fin / (Fout * factor)
> > + */
> > +static void ccu_ddn_disable(struct clk_hw *hw)
> > +{
> > +	struct ccu_ddn *ddn = hw_to_ccu_ddn(hw);
> > +	struct ccu_common *common = &ddn->common;
> > +
> > +	if (!ddn->gate)
> > +		return;
> 
> Use a new clk_ops to represent the gateable ddn clock and remove this
> check. This also applys to the following function.
> 
> > +
> > +	ccu_update(sel, common, ddn->gate, 0);
> > +}
> > +
> > +static int ccu_ddn_enable(struct clk_hw *hw)
> > +{
> > +	struct ccu_ddn *ddn = hw_to_ccu_ddn(hw);
> > +	struct ccu_common *common = &ddn->common;
> > +
> > +	if (!ddn->gate)
> > +		return 0;
> > +
> > +	ccu_update(sel, common, ddn->gate, ddn->gate);
> > +
> > +	return 0;
> > +}
> > +
> > +static int ccu_ddn_is_enabled(struct clk_hw *hw)
> > +{
> > +	struct ccu_ddn *ddn = hw_to_ccu_ddn(hw);
> > +	struct ccu_common *common = &ddn->common;
> > +	u32 tmp;
> > +
> > +	if (!ddn->gate)
> > +		return 1;
> > +
> > +	ccu_read(sel, common, &tmp);
> > +
> > +	return tmp & ddn->gate;
> > +}
> > +
> > +static long clk_ddn_round_rate(struct clk_hw *hw, unsigned long drate,
> > +			       unsigned long *prate)
> > +{
> > +	struct ccu_ddn *ddn = hw_to_ccu_ddn(hw);
> > +	struct ccu_ddn_config *params = &ddn->ddn;
> > +	unsigned long rate = 0, prev_rate;
> > +	unsigned long result;
> > +	int i;
> > +
> > +	for (i = 0; i < params->tbl_size; i++) {
> > +		prev_rate = rate;
> > +		rate = (((*prate / 10000) * params->tbl[i].den) /
> > +			(params->tbl[i].num * params->info->factor)) * 10000;
> > +		if (rate > drate)
> > +			break;
> > +	}
> > +
> > +	if ((i == 0) || (i == params->tbl_size)) {
> > +		result = rate;
> > +	} else {
> > +		if ((drate - prev_rate) > (rate - drate))
> > +			result = rate;
> > +		else
> > +			result = prev_rate;
> > +	}
> > +
> > +	return result;
> > +}
> > +
> > +static unsigned long clk_ddn_recalc_rate(struct clk_hw *hw,
> > +		unsigned long parent_rate)
> > +{
> > +	struct ccu_ddn *ddn = hw_to_ccu_ddn(hw);
> > +	struct ccu_ddn_config *params = &ddn->ddn;
> > +	unsigned int val, num, den;
> > +	unsigned long rate;
> > +
> > +	ccu_read(ctrl, &ddn->common, &val);
> > +
> > +	num = (val >> params->info->num_shift) & params->info->num_mask;
> > +	den = (val >> params->info->den_shift) & params->info->den_mask;
> > +
> > +	if (!den)
> > +		return 0;
> > +
> > +	rate = ((parent_rate / 10000)  * den) / (num * params->info->factor);
> > +	rate *= 10000;
> > +
> 
> It is pretty interested here. Why you need to divide the clock by 10000
> and multiple it? Is "(parent_rate * den) / (num * params->info->factor)"
> OK?

Basically this rounds the rate down to 10000 and the only affected clock
is slow_uart_1. I think it's some type of workaround for the vendor UART
driver.

Anyway, it is technically incorrect and not necessary anymore. I'll
remove it in v4. Same for the similar trick in clk_ddn_set_rate.

> > +	return rate;
> > +}
> > +
> > +/* Configures new clock rate*/
> > +static int clk_ddn_set_rate(struct clk_hw *hw, unsigned long drate,
> > +			    unsigned long prate)
> > +{
> > +	struct ccu_ddn *ddn = hw_to_ccu_ddn(hw);
> > +	struct ccu_ddn_config *params = &ddn->ddn;
> > +	struct ccu_ddn_info *info = params->info;
> > +	unsigned long prev_rate, rate = 0;
> > +	int i;
> > +
> > +	for (i = 0; i < params->tbl_size; i++) {
> > +		prev_rate = rate;
> > +		rate = ((prate / 10000) * params->tbl[i].den) /
> > +		       (params->tbl[i].num * info->factor);
> > +		rate *= 10000;
> > +
> > +		if (rate > drate)
> > +			break;
> > +	}
> > +
> > +	if (i > 0)
> > +		i--;
> > +
> > +	ccu_update(ctrl, &ddn->common,
> > +		   info->num_mask | info->den_mask,
> > +		   (params->tbl[i].num << info->num_shift) |
> > +		   (params->tbl[i].den << info->den_shift));
> > +
> > +	return 0;
> > +}
> > +
> > +const struct clk_ops spacemit_ccu_ddn_ops = {
> > +	.disable	= ccu_ddn_disable,
> > +	.enable		= ccu_ddn_enable,
> > +	.is_enabled	= ccu_ddn_is_enabled,
> > +	.recalc_rate	= clk_ddn_recalc_rate,
> > +	.round_rate	= clk_ddn_round_rate,
> > +	.set_rate	= clk_ddn_set_rate,
> > +};
> > diff --git a/drivers/clk/spacemit/ccu_ddn.h b/drivers/clk/spacemit/ccu_ddn.h
> > new file mode 100644
> > index 000000000000..4d369f41404c
> > --- /dev/null
> > +++ b/drivers/clk/spacemit/ccu_ddn.h
> > @@ -0,0 +1,85 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Copyright (c) 2024 SpacemiT Technology Co. Ltd
> > + * Copyright (c) 2024 Haylen Chu <heylenayy@outlook.com>
> > + */
> > +
> > +#ifndef _CCU_DDN_H_
> > +#define _CCU_DDN_H_
> > +
> > +#include <linux/clk-provider.h>
> > +
> > +#include "ccu_common.h"
> > +
> > +struct ccu_ddn_tbl {
> > +	unsigned int num;
> > +	unsigned int den;
> > +};
> > +
> > +struct ccu_ddn_info {
> > +	unsigned int factor;
> > +	unsigned int num_mask;
> > +	unsigned int den_mask;
> > +	unsigned int num_shift;
> > +	unsigned int den_shift;
> > +};
> > +
> > +struct ccu_ddn_config {
> > +	struct ccu_ddn_info *info;
> > +	struct ccu_ddn_tbl *tbl;
> > +	u32 tbl_size;
> > +};
> > +
> > +struct ccu_ddn {
> > +	struct ccu_ddn_config  ddn;
> > +	struct ccu_common	common;
> > +	u32 gate;
> > +};
> > +
> > +#define CCU_DDN_CONFIG(_info, _table)					\
> > +	{								\
> > +		.info		= (struct ccu_ddn_info *)_info,		\
> > +		.tbl		= (struct ccu_ddn_tbl *)&_table,	\
> > +		.tbl_size	= ARRAY_SIZE(_table),			\
> > +	}
> > +
> > +#define CCU_DDN_INIT(_name, _parent, _flags) \
> > +	CLK_HW_INIT_HW(_name, &_parent.common.hw,			\
> > +		       &spacemit_ccu_ddn_ops, _flags)
> > +
> > +#define CCU_DDN_DEFINE(_struct, _name, _parent, _info, _table,		\
> > +		       _reg_ctrl, _flags)				\
> > +	struct ccu_ddn _struct = {					\
> > +		.ddn	= CCU_DDN_CONFIG(_info, _table),		\
> > +		.common = {						\
> > +			.reg_ctrl = _reg_ctrl,				\
> > +			.hw.init  = CCU_DDN_INIT(_name, _parent,	\
> > +						 _flags),		\
> > +		}							\
> > +	}
> > +
> > +#define CCU_DDN_GATE_DEFINE(_struct, _name, _parent, _info, _table,	\
> > +			    _reg_ddn, _reg_gate, _gate_mask, _flags)	\
> > +	struct ccu_ddn _struct = {					\
> > +		.ddn	= CCU_DDN_CONFIG(_info, _table),		\
> > +		.common = {						\
> > +			.reg_ctrl	= _reg_ddn,			\
> > +			.reg_sel	= _reg_gate,			\
> > +			.hw.init = CLK_HW_INIT(_name, _parent,		\
> > +					       &spacemit_ccu_ddn_ops,	\
> > +					       _flags),			\
> > +		}							\
> > +		.gate	= _gate_mask,					\
> > +	}
> > +
> > +
> > +static inline struct ccu_ddn *hw_to_ccu_ddn(struct clk_hw *hw)
> > +{
> > +	struct ccu_common *common = hw_to_ccu_common(hw);
> > +
> > +	return container_of(common, struct ccu_ddn, common);
> > +}
> > +
> > +extern const struct clk_ops spacemit_ccu_ddn_ops;
> > +
> > +#endif
> > diff --git a/drivers/clk/spacemit/ccu_mix.c b/drivers/clk/spacemit/ccu_mix.c
> > new file mode 100644
> > index 000000000000..de343405fcc7
> > --- /dev/null
> > +++ b/drivers/clk/spacemit/ccu_mix.c
> > @@ -0,0 +1,296 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Spacemit clock type mix(div/mux/gate/factor)
> > + *
> > + * Copyright (c) 2024 SpacemiT Technology Co. Ltd
> > + * Copyright (c) 2024 Haylen Chu <heylenay@outlook.com>
> > + */
> > +
> > +#include <linux/clk-provider.h>
> > +
> > +#include "ccu_mix.h"
> > +
> > +#define MIX_TIMEOUT	10000
> > +
> > +#define mix_hwparam_in_sel(c) \
> > +	((c)->reg_type == CLK_DIV_TYPE_2REG_NOFC_V3 || \
> > +	 (c)->reg_type == CLK_DIV_TYPE_2REG_FC_V4)
> > +
> 
> > +static void ccu_mix_disable(struct clk_hw *hw)
> > +{
> > +	struct ccu_mix *mix = hw_to_ccu_mix(hw);
> > +	struct ccu_common *common = &mix->common;
> > +	struct ccu_gate_config *gate = mix->gate;
> > +
> > +	if (!gate)
> > +		return;
> > +
> > +	if (mix_hwparam_in_sel(common))
> > +		ccu_update(sel, common, gate->gate_mask, gate->val_disable);
> > +	else
> > +		ccu_update(ctrl, common, gate->gate_mask, gate->val_disable);
> > +}
> > +
> > +static int ccu_mix_enable(struct clk_hw *hw)
> > +{
> > +	struct ccu_mix *mix = hw_to_ccu_mix(hw);
> > +	struct ccu_common *common = &mix->common;
> > +	struct ccu_gate_config *gate = mix->gate;
> > +	u32 val_enable, mask;
> > +	u32 tmp;
> > +
> > +	if (!gate)
> > +		return 0;
> > +
> > +	val_enable	= gate->val_enable;
> > +	mask		= gate->gate_mask;
> > +
> > +	if (mix_hwparam_in_sel(common))
> > +		ccu_update(sel, common, mask, val_enable);
> > +	else
> > +		ccu_update(ctrl, common, mask, val_enable);
> > +
> > +	if (common->reg_type == CLK_DIV_TYPE_2REG_NOFC_V3 ||
> > +	    common->reg_type == CLK_DIV_TYPE_2REG_FC_V4)
> > +		return ccu_poll(sel, common, tmp, (tmp & mask) == val_enable,
> > +				10, MIX_TIMEOUT);
> > +	else
> > +		return ccu_poll(ctrl, common, tmp, (tmp & mask) == val_enable,
> > +				10, MIX_TIMEOUT);
> > +}
> > +
> > +static int ccu_mix_is_enabled(struct clk_hw *hw)
> > +{
> > +	struct ccu_mix *mix = hw_to_ccu_mix(hw);
> > +	struct ccu_common *common = &mix->common;
> > +	struct ccu_gate_config *gate = mix->gate;
> > +	u32 tmp;
> > +
> > +	if (!gate)
> > +		return 1;
> > +
> > +	if (mix_hwparam_in_sel(common))
> > +		ccu_read(sel, common, &tmp);
> > +	else
> > +		ccu_read(ctrl, common, &tmp);
> > +
> > +	return (tmp & gate->gate_mask) == gate->val_enable;
> > +}
> > +
> > +static unsigned long ccu_mix_recalc_rate(struct clk_hw *hw,
> > +					unsigned long parent_rate)
> > +{
> > +	struct ccu_mix *mix = hw_to_ccu_mix(hw);
> > +	struct ccu_common *common = &mix->common;
> > +	struct ccu_div_config *div = mix->div;
> > +	unsigned long val;
> > +	u32 reg;
> > +
> > +	if (!div) {
> > +		if (mix->factor)
> > +			return parent_rate * mix->factor->mul / mix->factor->div;
> > +
> > +		return parent_rate;
> > +	}
> > +
> > +	if (mix_hwparam_in_sel(common))
> > +		ccu_read(sel, common, &reg);
> > +	else
> > +		ccu_read(ctrl, common, &reg);
> > +
> > +	val = reg >> div->shift;
> > +	val &= (1 << div->width) - 1;
> > +
> > +	val = divider_recalc_rate(hw, parent_rate, val, div->table,
> > +				  div->flags, div->width);
> > +
> > +	return val;
> > +}
> 
> I think you should distinguish these muxs, it is not good to
> use mix_hwparam_in_sel everywhere. There are two types of mux.
> 
> > +
> > +
> 
> Double empty line here, you should run checkpatch.
> 
> > +static int ccu_mix_trigger_fc(struct clk_hw *hw)
> > +{
> > +	struct ccu_mix *mix = hw_to_ccu_mix(hw);
> > +	struct ccu_common *common = &mix->common;
> > +	unsigned int val = 0;
> > +	int ret = 0;
> > +
> > +	if (common->reg_type == CLK_DIV_TYPE_1REG_FC_V2 ||
> > +	    common->reg_type == CLK_DIV_TYPE_2REG_FC_V4 ||
> > +	    common->reg_type == CLK_DIV_TYPE_1REG_FC_DIV_V5 ||
> > +	    common->reg_type == CLK_DIV_TYPE_1REG_FC_MUX_V6) {
> > +		ccu_update(ctrl, common, common->fc, common->fc);
> > +
> > +		ret = ccu_poll(ctrl, common, val, !(val & common->fc),
> > +			       5, MIX_TIMEOUT);
> > +	}
> > +
> > +	return ret;
> > +}
> > +
> > +static int ccu_mix_determine_rate(struct clk_hw *hw,
> > +				  struct clk_rate_request *req)
> > +{
> > +	return 0;
> > +}
> > +
> 
> Why a empty determine_rate function?

It's a mistake and will be corrected in next version.

> > +static unsigned long
> > +ccu_mix_calc_best_rate(struct clk_hw *hw, unsigned long rate, u32 *mux_val,
> > +		       u32 *div_val)
> > +{
> > +	struct ccu_mix *mix = hw_to_ccu_mix(hw);
> > +	struct ccu_common *common = &mix->common;
> > +	struct ccu_div_config *div = mix->div ? mix->div : NULL;
> > +	struct clk_hw *parent;
> > +	unsigned long parent_rate = 0, best_rate = 0;
> > +	u32 i, j, div_max;
> > +
> > +	for (i = 0; i < common->num_parents; i++) {
> > +		parent = clk_hw_get_parent_by_index(hw, i);
> > +		if (!parent)
> > +			continue;
> > +
> > +		parent_rate = clk_hw_get_rate(parent);
> > +
> > +		if (div)
> > +			div_max = 1 << div->width;
> > +		else
> > +			div_max = 1;
> > +
> > +		for (j = 1; j <= div_max; j++) {
> > +			if (abs(parent_rate/j - rate) < abs(best_rate - rate)) {
> > +				best_rate = DIV_ROUND_UP_ULL(parent_rate, j);
> > +				*mux_val = i;
> > +				*div_val = j - 1;
> > +			}
> > +		}
> > +	}
> > +
> > +	return best_rate;
> > +}
> > +
> > +static int ccu_mix_set_rate(struct clk_hw *hw, unsigned long rate,
> > +			   unsigned long parent_rate)
> > +{
> > +	struct ccu_mix *mix = hw_to_ccu_mix(hw);
> > +	struct ccu_common *common = &mix->common;
> > +	struct ccu_div_config *div = mix->div;
> > +	struct ccu_mux_config *mux = mix->mux;
> > +	u32 cur_mux, cur_div, mux_val = 0, div_val = 0;
> > +	unsigned long best_rate = 0;
> > +	int ret = 0, tmp = 0;
> > +
> > +	if (!div && !mux)
> > +		return 0;
> > +
> > +	best_rate = ccu_mix_calc_best_rate(hw, rate, &mux_val, &div_val);
> > +
> > +	if (mix_hwparam_in_sel(common))
> > +		ccu_read(sel, common, &tmp);
> > +	else
> > +		ccu_read(ctrl, common, &tmp);
> > +
> > +	if (mux) {
> > +		cur_mux = tmp >> mux->shift;
> > +		cur_mux &= (1 << mux->width) - 1;
> > +
> > +		if (cur_mux != mux_val)
> > +			clk_hw_set_parent(hw, clk_hw_get_parent_by_index(hw, mux_val));
> > +	}
> > +
> > +	if (div) {
> > +		cur_div = tmp >> div->shift;
> > +		cur_div &= (1 << div->width) - 1;
> > +
> > +		if (cur_div == div_val)
> > +			return 0;
> > +	} else {
> > +		return 0;
> > +	}
> > +
> > +	tmp = GENMASK(div->width + div->shift - 1, div->shift);
> > +
> > +	if (mix_hwparam_in_sel(common))
> > +		ccu_update(sel, common, tmp, div_val << div->shift);
> > +	else
> > +		ccu_update(ctrl, common, tmp, div_val << div->shift);
> > +
> > +	if (common->reg_type == CLK_DIV_TYPE_1REG_FC_V2 ||
> > +	    common->reg_type == CLK_DIV_TYPE_2REG_FC_V4 ||
> > +	    common->reg_type == CLK_DIV_TYPE_1REG_FC_DIV_V5)
> > +		ret = ccu_mix_trigger_fc(hw);
> > +
> > +	return ret;
> > +}
> > +
> > +static u8 ccu_mix_get_parent(struct clk_hw *hw)
> > +{
> > +	struct ccu_mix *mix = hw_to_ccu_mix(hw);
> > +	struct ccu_common *common = &mix->common;
> > +	struct ccu_mux_config *mux = mix->mux;
> > +	u32 reg;
> > +	u8 parent;
> > +
> > +	if (!mux)
> > +		return 0;
> > +
> > +	if (mix_hwparam_in_sel(common))
> > +		ccu_read(sel, common, &reg);
> > +	else
> > +		ccu_read(ctrl, common, &reg);
> > +
> > +	parent = reg >> mux->shift;
> > +	parent &= (1 << mux->width) - 1;
> > +
> > +	if (mux->table) {
> > +		int num_parents = clk_hw_get_num_parents(&common->hw);
> > +		int i;
> > +
> > +		for (i = 0; i < num_parents; i++)
> > +			if (mux->table[i] == parent)
> > +				return i;
> > +	}
> > +
> > +	return parent;
> > +}
> > +
> > +static int ccu_mix_set_parent(struct clk_hw *hw, u8 index)
> > +{
> > +	struct ccu_mix *mix = hw_to_ccu_mix(hw);
> > +	struct ccu_common *common = &mix->common;
> > +	struct ccu_mux_config *mux = mix->mux;
> > +	int ret = 0;
> > +	u32 mask;
> > +
> > +	if (!mux)
> > +		return 0;
> > +
> > +	if (mux->table)
> > +		index = mux->table[index];
> > +
> > +	mask = GENMASK(mux->width + mux->shift - 1, mux->shift);
> > +
> > +	if (mix_hwparam_in_sel(common))
> > +		ccu_update(sel, common, mask, index << mux->shift);
> > +	else
> > +		ccu_update(ctrl, common, mask, index << mux->shift);
> > +
> > +	if (common->reg_type == CLK_DIV_TYPE_1REG_FC_V2 ||
> > +	    common->reg_type == CLK_DIV_TYPE_2REG_FC_V4 ||
> > +	    common->reg_type == CLK_DIV_TYPE_1REG_FC_MUX_V6)
> > +		ret = ccu_mix_trigger_fc(hw);
> > +
> > +	return ret;
> > +}
> > +
> > +const struct clk_ops spacemit_ccu_mix_ops = {
> > +	.disable	 = ccu_mix_disable,
> > +	.enable		 = ccu_mix_enable,
> > +	.is_enabled	 = ccu_mix_is_enabled,
> > +	.get_parent	 = ccu_mix_get_parent,
> > +	.set_parent	 = ccu_mix_set_parent,
> > +	.determine_rate  = ccu_mix_determine_rate,
> > +	.recalc_rate	 = ccu_mix_recalc_rate,
> > +	.set_rate	 = ccu_mix_set_rate,
> > +};
> 
> I think you should separate the clock into different type and
> use pre-defined function to simplify, but not use a unified,
> complex and hard to read structure to represent all kinds of
> clocks.

This makes sense.

As suggested by Yixun, we could split out several clk_ops and define
clocks with diffferent clk_ops, eliminating the ifs. I'd like to take
this scheme and clean up ddn/mix driver in v4.

> 
> > +
> > diff --git a/drivers/clk/spacemit/ccu_mix.h b/drivers/clk/spacemit/ccu_mix.h
> > new file mode 100644
> > index 000000000000..c7d91e1c03fd
> > --- /dev/null
> > +++ b/drivers/clk/spacemit/ccu_mix.h
> > @@ -0,0 +1,336 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Copyright (c) 2024 SpacemiT Technology Co. Ltd
> > + * Copyright (c) 2024 Haylen Chu <heylenay@outlook.com>
> > + */
> > +
> > +#ifndef _CCU_MIX_H_
> > +#define _CCU_MIX_H_
> > +
> > +#include <linux/clk-provider.h>
> > +
> > +#include "ccu_common.h"
> > +
> > +struct ccu_gate_config {
> > +	u32 gate_mask;
> > +	u32 val_enable;
> > +	u32 val_disable;
> > +	u32 flags;
> > +};
> > +
> > +struct ccu_factor_config {
> > +	u32 div;
> > +	u32 mul;
> > +};
> > +
> > +struct ccu_mux_config {
> > +	const u8 *table;
> > +	u32 flags;
> > +	u8 shift;
> > +	u8 width;
> > +};
> > +
> > +struct ccu_div_config {
> > +	struct clk_div_table *table;
> > +	u32 max;
> > +	u32 offset;
> > +	u32 flags;
> > +	u8 shift;
> > +	u8 width;
> > +};
> > +
> > +struct ccu_mix {
> > +	struct ccu_factor_config *factor;
> > +	struct ccu_gate_config *gate;
> > +	struct ccu_div_config *div;
> > +	struct ccu_mux_config *mux;
> > +	struct ccu_common common;
> > +};
> > +
> > +#define CCU_GATE_INIT(_gate_mask, _val_enable, _val_disable, _flags)		\
> > +	(&(struct ccu_gate_config) {						\
> > +		.gate_mask   = _gate_mask,					\
> > +		.val_enable  = _val_enable,					\
> > +		.val_disable = _val_disable,					\
> > +		.flags	     = _flags,						\
> > +	})
> > +
> > +#define CCU_FACTOR_INIT(_div, _mul)					\
> > +	(&(struct ccu_factor_config) {					\
> > +		.div = _div,						\
> > +		.mul = _mul,						\
> > +	})
> > +
> > +
> > +#define CCU_MUX_INIT(_shift, _width, _table, _flags)			\
> > +	(&(struct ccu_mux_config) {					\
> > +		.shift	= _shift,					\
> > +		.width	= _width,					\
> > +		.table	= _table,					\
> > +		.flags	= _flags,					\
> > +	})
> > +
> > +#define CCU_DIV_INIT(_shift, _width, _table, _flags)			\
> > +	(&(struct ccu_div_config) {					\
> > +		.shift	= _shift,					\
> > +		.width	= _width,					\
> > +		.flags	= _flags,					\
> > +		.table	= _table,					\
> > +	})
> > +
> > +#define CCU_PARENT_HW(_parent)		{ .hw = &_parent.common.hw }
> > +#define CCU_PARENT_NAME(_name)		{ .fw_name = #_name }
> > +
> > +#define CCU_MIX_INITHW(_name, _parent, _flags)				\
> > +	(&(struct clk_init_data) {					\
> > +		.flags		= _flags,				\
> > +		.name		= _name,				\
> > +		.parent_data	= (const struct clk_parent_data[])	\
> > +					{ _parent },			\
> > +		.num_parents	= 1,					\
> > +		.ops		= &spacemit_ccu_mix_ops,		\
> > +	})
> > +
> > +#define CCU_MIX_INITHW_PARENTS(_name, _parents, _flags)			\
> > +	CLK_HW_INIT_PARENTS_DATA(_name, _parents,			\
> > +				 &spacemit_ccu_mix_ops, _flags)
> > +
> > +#define CCU_GATE_DEFINE(_struct, _name, _parent, _reg, _gate_mask,	\
> > +			 _val_enable, _val_disable, _flags)		\
> > +struct ccu_mix _struct = {						\
> > +	.gate	= CCU_GATE_INIT(_gate_mask, _val_enable,		\
> > +				_val_disable, 0),			\
> > +	.common	= {							\
> > +		.reg_ctrl	= _reg,					\
> > +		.name		= _name,				\
> > +		.num_parents	= 1,					\
> > +		.hw.init	= CCU_MIX_INITHW(_name, _parent,	\
> > +						 _flags),		\
> > +	}								\
> > +}
> > +
> > +#define CCU_FACTOR_DEFINE(_struct, _name, _parent, _div, _mul)		\
> > +struct ccu_mix _struct = {						\
> > +	.factor	= CCU_FACTOR_INIT(_div, _mul),				\
> > +	.common = {							\
> > +		.name		= _name,				\
> > +		.num_parents	= 1,					\
> > +		.hw.init	= CCU_MIX_INITHW(_name, _parent, 0),	\
> > +	}								\
> > +}
> > +
> > +#define CCU_MUX_DEFINE(_struct, _name, _parents, _reg, _shift, _width,	\
> > +		       _flags)						\
> > +struct ccu_mix _struct = {						\
> > +	.mux	= CCU_MUX_INIT(_shift, _width, NULL, 0),		\
> > +	.common = {							\
> > +		.reg_ctrl	= _reg,					\
> > +		.name		= _name,				\
> > +		.num_parents	= ARRAY_SIZE(_parents),			\
> > +		.hw.init = CCU_MIX_INITHW_PARENTS(_name, _parents,	\
> > +						  _flags),		\
> > +	}								\
> > +}
> > +
> > +#define CCU_DIV_DEFINE(_struct, _name, _parent, _reg, _shift, _width,	\
> > +		       _flags)						\
> > +struct ccu_mix _struct = {						\
> > +	.div	= CCU_DIV_INIT(_shift, _width, NULL, 0),		\
> > +	.common = {							\
> > +		.reg_ctrl	= _reg,					\
> > +		.name		= _name,				\
> > +		.num_parents	= 1,					\
> > +		.hw.init = CCU_MIX_INITHW(_name, _parent, _flags)	\
> > +	}								\
> > +}
> > +
> > +#define CCU_GATE_FACTOR_DEFINE(_struct, _name, _parent, _reg,		\
> > +			       _gate_mask, _val_enable, _val_disable,	\
> > +			       _div, _mul, _flags)			\
> > +struct ccu_mix _struct = {						\
> > +	.gate	= CCU_GATE_INIT(_gate_mask, _val_enable,		\
> > +				_val_disable, 0),			\
> > +	.factor	= CCU_FACTOR_INIT(_div, _mul),				\
> > +	.common = {							\
> > +		.reg_ctrl	= _reg,					\
> > +		.name		= _name,				\
> > +		.num_parents	= 1,					\
> > +		.hw.init = CCU_MIX_INITHW(_name, _parent, _flags)	\
> > +	}								\
> > +}
> > +
> > +
> > +#define CCU_MUX_GATE_DEFINE(_struct, _name, _parents, _reg, _shift,	\
> > +			    _width, _gate_mask, _val_enable,		\
> > +			    _val_disable, _flags)			\
> > +struct ccu_mix _struct = {						\
> > +	.gate	= CCU_GATE_INIT(_gate_mask, _val_enable,		\
> > +				_val_disable, 0),			\
> > +	.mux	= CCU_MUX_INIT(_shift, _width, NULL, 0),		\
> > +	.common = {							\
> > +		.reg_ctrl	= _reg,					\
> > +		.name		= _name,				\
> > +		.num_parents	= ARRAY_SIZE(_parents),			\
> > +		.hw.init = CCU_MIX_INITHW_PARENTS(_name, _parents,	\
> > +						  _flags),		\
> > +	}								\
> > +}
> > +
> > +#define CCU_DIV_GATE_DEFINE(_struct, _name, _parent, _reg, _shift,	\
> > +			    _width, _gate_mask, _val_enable,		\
> > +			    _val_disable, _flags)			\
> > +struct ccu_mix _struct = {						\
> > +	.gate	= CCU_GATE_INIT(_gate_mask, _val_enable,		\
> > +				_val_disable, 0),			\
> > +	.div	= CCU_DIV_INIT(_shift, _width, NULL, 0),		\
> > +	.common = {							\
> > +		.reg_ctrl	= _reg,					\
> > +		.name		= _name,				\
> > +		.num_parents	= 1,					\
> > +		.hw.init	= CCU_MIX_INITHW(_name, _parent,	\
> > +						 _flags),		\
> > +	}								\
> > +}
> > +
> > +
> > +#define CCU_DIV_MUX_GATE_DEFINE(_struct, _name, _parents,  _reg_ctrl,	\
> > +				_mshift, _mwidth, _muxshift, _muxwidth,	\
> > +				_gate_mask, _val_enable, _val_disable,	\
> > +				_flags)					\
> > +struct ccu_mix _struct = {						\
> > +	.gate	= CCU_GATE_INIT(_gate_mask, _val_enable,		\
> > +				_val_disable, 0),			\
> > +	.div	= CCU_DIV_INIT(_mshift, _mwidth, NULL, 0),		\
> > +	.mux	= CCU_MUX_INIT(_muxshift, _muxwidth, NULL, 0),		\
> > +	.common	= {							\
> > +		.reg_ctrl	= _reg_ctrl,				\
> > +		.name		= _name,				\
> > +		.num_parents	= ARRAY_SIZE(_parents),			\
> > +		.hw.init = CCU_MIX_INITHW_PARENTS(_name, _parents,	\
> > +						  _flags),		\
> > +	},								\
> > +}
> > +
> > +#define CCU_DIV2_FC_MUX_GATE_DEFINE(_struct, _name, _parents,		\
> > +				    _reg_ctrl, _reg_sel, _mshift,	\
> > +				    _mwidth, _fc, _muxshift, _muxwidth,	\
> > +				    _gate_mask, _val_enable,		\
> > +				    _val_disable, _flags)		\
> > +struct ccu_mix _struct = {						\
> > +	.gate	= CCU_GATE_INIT(_gate_mask, _val_enable,		\
> > +				_val_disable, 0),			\
> > +	.div	= CCU_DIV_INIT(_mshift, _mwidth, NULL, 0),		\
> > +	.mux	= CCU_MUX_INIT(_muxshift, _muxwidth, NULL, 0),		\
> > +	.common = {							\
> > +	    .reg_type = CLK_DIV_TYPE_2REG_FC_V4,			\
> > +		.reg_ctrl	= _reg_ctrl,				\
> > +		.reg_sel	= _reg_sel,				\
> > +		.fc		= _fc,					\
> > +		.name		= _name,				\
> > +		.num_parents	= ARRAY_SIZE(_parents),			\
> > +		.hw.init = CCU_MIX_INITHW_PARENTS(_name, _parents,	\
> > +						  _flags),		\
> > +	},								\
> > +}
> > +
> > +
> > +#define CCU_DIV_FC_MUX_GATE_DEFINE(_struct, _name, _parents, _reg_ctrl,	\
> > +				   _mshift, _mwidth, _fc, _muxshift,	\
> > +				   _muxwidth, _gate_mask, _val_enable,	\
> > +				   _val_disable, _flags)		\
> > +struct ccu_mix _struct = {						\
> > +	.gate	= CCU_GATE_INIT(_gate_mask, _val_enable,		\
> > +				_val_disable, 0),			\
> > +	.div	= CCU_DIV_INIT(_mshift, _mwidth, NULL, 0),		\
> > +	.mux	= CCU_MUX_INIT(_muxshift, _muxwidth, NULL, 0),		\
> > +	.common = {							\
> > +		.reg_type	= CLK_DIV_TYPE_1REG_FC_V2,		\
> > +		.reg_ctrl	= _reg_ctrl,				\
> > +		.fc		= _fc,					\
> > +		.name		= _name,				\
> > +		.num_parents	= ARRAY_SIZE(_parents),			\
> > +		.hw.init = CCU_MIX_INITHW_PARENTS(_name, _parents,	\
> > +						  _flags),		\
> > +	},								\
> > +}
> > +
> > +#define CCU_DIV_MFC_MUX_GATE_DEFINE(_struct, _name, _parents,		\
> > +				    _reg_ctrl, _mshift, _mwidth, _fc,	\
> > +				    _muxshift, _muxwidth, _gate_mask,	\
> > +				    _val_enable, _val_disable, _flags)	\
> > +struct ccu_mix _struct = {						\
> > +	.gate	= CCU_GATE_INIT(_gate_mask, _val_enable,		\
> > +				_val_disable, 0),			\
> > +	.div	= CCU_DIV_INIT(_mshift, _mwidth, NULL, 0),		\
> > +	.mux	= CCU_MUX_INIT(_muxshift, _muxwidth, NULL, 0),		\
> > +	.common = {							\
> > +		.reg_type = CLK_DIV_TYPE_1REG_FC_MUX_V6,		\
> > +		.reg_ctrl	= _reg_ctrl,				\
> > +		.fc		= _fc,					\
> > +		.name		= _name,				\
> > +		.num_parents	= ARRAY_SIZE(_parents),			\
> > +		.hw.init = CCU_MIX_INITHW_PARENTS(_name, _parents,	\
> > +						  _flags),		\
> > +	},								\
> > +}
> > +
> > +#define CCU_DIV_FC_WITH_GATE_DEFINE(_struct, _name, _parent, _reg_ctrl,	\
> > +				    _mshift, _mwidth, _fc, _gate_mask,	\
> > +				    _val_enable, _val_disable, _flags)	\
> > +struct ccu_mix _struct = {						\
> > +	.gate	= CCU_GATE_INIT(_gate_mask, _val_enable,		\
> > +				_val_disable, 0),			\
> > +	.div	= CCU_DIV_INIT(_mshift, _mwidth, NULL, 0),		\
> > +	.common = {							\
> > +		.reg_type = CLK_DIV_TYPE_1REG_FC_V2,			\
> > +		.reg_ctrl	= _reg_ctrl,				\
> > +		.fc		= _fc,					\
> > +		.name		= _name,				\
> > +		.num_parents	= 1,					\
> > +		.hw.init	= CCU_MIXINITHW(_name, _parent,		\
> > +						_flags),		\
> > +	},								\
> > +}
> > +
> > +#define CCU_DIV_FC_MUX_DEFINE(_struct, _name, _parents, _reg_ctrl,	\
> > +			      _mshift, _mwidth, _fc, _muxshift,		\
> > +			      _muxwidth, _flags)			\
> > +struct ccu_mix _struct = {						\
> > +	.div	= CCU_DIV_INIT(_mshift, _mwidth, NULL, 0),		\
> > +	.mux	= CCU_MUX_INIT(_muxshift, _muxwidth, NULL, 0),		\
> > +	.common = {							\
> > +		.reg_type	= CLK_DIV_TYPE_1REG_FC_V2,		\
> > +		.reg_ctrl	= _reg_ctrl,				\
> > +		.fc		= _fc,					\
> > +		.name		= _name,				\
> > +		.num_parents	= ARRAY_SIZE(_parents),			\
> > +		.hw.init = CCU_MIX_INITHW_PARENTS(_name, _parents,	\
> > +						  _flags),		\
> > +	},								\
> > +}
> > +
> > +#define CCU_MUX_FC_DEFINE(_struct, _name, _parents, _reg_ctrl, _fc,	\
> > +			  _muxshift, _muxwidth, _flags)			\
> > +struct ccu_mix _struct = {						\
> > +	.mux	= CCU_MUX_INIT(_muxshift, _muxwidth, NULL, 0),		\
> > +	.common = {							\
> > +		.reg_type	= CLK_DIV_TYPE_1REG_FC_V2,		\
> > +		.reg_ctrl	= _reg_ctrl,				\
> > +		.fc		= _fc,					\
> > +		.name		= _name,				\
> > +		.num_parents	= ARRAY_SIZE(_parents),			\
> > +		.hw.init = CCU_MIX_INITHW_PARENTS(_name, _parents,	\
> > +						  _flags)		\
> > +	},								\
> > +}
> > +
> > +static inline struct ccu_mix *hw_to_ccu_mix(struct clk_hw *hw)
> > +{
> > +	struct ccu_common *common = hw_to_ccu_common(hw);
> > +
> > +	return container_of(common, struct ccu_mix, common);
> > +}
> > +
> > +extern const struct clk_ops spacemit_ccu_mix_ops;
> > +
> > +#endif /* _CCU_DIV_H_ */
> > diff --git a/drivers/clk/spacemit/ccu_pll.c b/drivers/clk/spacemit/ccu_pll.c
> > new file mode 100644
> > index 000000000000..cf6e547f073b
> > --- /dev/null
> > +++ b/drivers/clk/spacemit/ccu_pll.c
> > @@ -0,0 +1,198 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Spacemit clock type pll
> > + *
> > + * Copyright (c) 2024 SpacemiT Technology Co. Ltd
> > + * Copyright (c) 2024 Haylen Chu <heylenay@outlook.com>
> > + */
> > +
> > +#include <linux/clk-provider.h>
> > +#include <linux/regmap.h>
> > +
> > +#include "ccu_common.h"
> > +#include "ccu_pll.h"
> > +
> > +#define PLL_MIN_FREQ	600000000
> > +#define PLL_MAX_FREQ	3400000000
> > +#define PLL_DELAY_TIME	3000
> > +
> > +#define PLL_SWCR1_REG5_OFF	0
> > +#define PLL_SWCR1_REG5_MASK	GENMASK(7, 0)
> > +#define PLL_SWCR1_REG6_OFF	8
> > +#define PLL_SWCR1_REG6_MASK	GENMASK(15, 8)
> > +#define PLL_SWCR1_REG7_OFF	16
> > +#define PLL_SWCR1_REG7_MASK	GENMASK(23, 16)
> > +#define PLL_SWCR1_REG8_OFF	24
> > +#define PLL_SWCR1_REG8_MASK	GENMASK(31, 24)
> > +
> > +#define PLL_SWCR2_DIVn_EN(n)	BIT(n + 1)
> > +#define PLL_SWCR2_ATEST_EN	BIT(12)
> > +#define PLL_SWCR2_CKTEST_EN	BIT(13)
> > +#define PLL_SWCR2_DTEST_EN	BIT(14)
> > +
> > +#define PLL_SWCR3_DIV_FRC_OFF	0
> > +#define PLL_SWCR3_DIV_FRC_MASK	GENMASK(23, 0)
> > +#define PLL_SWCR3_DIV_INT_OFF	24
> > +#define PLL_SWCR3_DIV_INT_MASK	GENMASK(30, 24)
> > +#define PLL_SWCR3_EN		BIT(31)
> > +
> > +static int ccu_pll_is_enabled(struct clk_hw *hw)
> > +{
> > +	struct ccu_pll *p = hw_to_ccu_pll(hw);
> > +	u32 tmp;
> > +
> > +	ccu_read(swcr3, &p->common, &tmp);
> > +
> > +	return tmp & PLL_SWCR3_EN;
> > +}
> > +
> > +/* frequency unit Mhz, return pll vco freq */
> > +static unsigned long __get_vco_freq(struct clk_hw *hw)
> 
> It is better to use ccu_pll_get_vco_freq.

Okay.

> 
> > +{
> > +	unsigned int reg5, reg6, reg7, reg8, size, i;
> > +	unsigned int div_int, div_frc;
> > +	struct ccu_pll_rate_tbl *freq_pll_regs_table;
> > +	struct ccu_pll *p = hw_to_ccu_pll(hw);
> > +	struct ccu_common *common = &p->common;
> > +	u32 tmp;
> > +
> > +	ccu_read(swcr1, common, &tmp);
> > +	reg5 = (tmp & PLL_SWCR1_REG5_MASK) >> PLL_SWCR1_REG5_OFF;
> > +	reg6 = (tmp & PLL_SWCR1_REG6_MASK) >> PLL_SWCR1_REG6_OFF;
> > +	reg7 = (tmp & PLL_SWCR1_REG7_MASK) >> PLL_SWCR1_REG7_OFF;
> > +	reg8 = (tmp & PLL_SWCR1_REG8_MASK) >> PLL_SWCR1_REG8_OFF;
> > +
> > +	ccu_read(swcr3, common, &tmp);
> > +	div_int = (tmp & PLL_SWCR3_DIV_INT_MASK) >> PLL_SWCR3_DIV_INT_OFF;
> > +	div_frc = (tmp & PLL_SWCR3_DIV_FRC_MASK) >> PLL_SWCR3_DIV_FRC_OFF;
> > +
> > +	freq_pll_regs_table = p->pll.rate_tbl;
> > +	size = p->pll.tbl_size;
> > +
> > +	for (i = 0; i < size; i++)
> > +		if ((freq_pll_regs_table[i].reg5 == reg5) &&
> > +		    (freq_pll_regs_table[i].reg6 == reg6) &&
> > +		    (freq_pll_regs_table[i].reg7 == reg7) &&
> > +		    (freq_pll_regs_table[i].reg8 == reg8) &&
> > +		    (freq_pll_regs_table[i].div_int == div_int) &&
> > +		    (freq_pll_regs_table[i].div_frac == div_frc))
> > +			return freq_pll_regs_table[i].rate;
> > +
> > +	WARN_ON_ONCE(1);
> > +
> > +	return 0;
> > +}
> > +
> > +static int ccu_pll_enable(struct clk_hw *hw)
> > +{
> > +	struct ccu_pll *p = hw_to_ccu_pll(hw);
> > +	struct ccu_common *common = &p->common;
> > +	unsigned int tmp;
> > +	int ret;
> > +
> > +	if (ccu_pll_is_enabled(hw))
> > +		return 0;
> > +
> > +	ccu_update(swcr3, common, PLL_SWCR3_EN, PLL_SWCR3_EN);
> > +
> > +	/* check lock status */
> > +	ret = regmap_read_poll_timeout_atomic(common->lock_base,
> > +					      p->pll.reg_lock,
> > +					      tmp,
> > +					      tmp & p->pll.lock_enable_bit,
> > +					      5, PLL_DELAY_TIME);
> > +
> > +	return ret;
> > +}
> > +
> > +static void ccu_pll_disable(struct clk_hw *hw)
> > +{
> > +	struct ccu_pll *p = hw_to_ccu_pll(hw);
> > +	struct ccu_common *common = &p->common;
> > +
> > +	ccu_update(swcr3, common, PLL_SWCR3_EN, 0);
> > +}
> > +
> > +/*
> > + * pll rate change requires sequence:
> > + * clock off -> change rate setting -> clock on
> > + * This function doesn't really change rate, but cache the config
> > + */
> > +static int ccu_pll_set_rate(struct clk_hw *hw, unsigned long rate,
> > +			       unsigned long parent_rate)
> > +{
> > +	struct ccu_pll *p = hw_to_ccu_pll(hw);
> > +	struct ccu_common *common = &p->common;
> > +	struct ccu_pll_config *params = &p->pll;
> > +	struct ccu_pll_rate_tbl *entry;
> > +	unsigned long old_rate;
> > +	bool found = false;
> > +	u32 mask, val;
> > +	int i;
> > +
> > +	if (ccu_pll_is_enabled(hw)) {
> > +		pr_err("%s %s is enabled, ignore the setrate!\n",
> > +		       __func__, __clk_get_name(hw->clk));
> 
> Just use clk_hw_get_name.

Thanks, I recently found flag CLK_SET_RATE and think it's more
appropriate here, since it protects the clock from rate changes in the
framework.

> 
> > +		return 0;
> > +	}
> > +
> > +	old_rate = __get_vco_freq(hw);
> > +
> > +	for (i = 0; i < params->tbl_size; i++) {
> > +		if (rate == params->rate_tbl[i].rate) {
> > +			found = true;
> > +			entry = &params->rate_tbl[i];
> > +			break;
> > +		}
> > +	}
> > +	WARN_ON_ONCE(!found);
> > +
> > +	mask = PLL_SWCR1_REG5_MASK | PLL_SWCR1_REG6_MASK;
> > +	mask |= PLL_SWCR1_REG7_MASK | PLL_SWCR1_REG8_MASK;
> > +	val |= entry->reg5 << PLL_SWCR1_REG5_OFF;
> > +	val |= entry->reg6 << PLL_SWCR1_REG6_OFF;
> > +	val |= entry->reg7 << PLL_SWCR1_REG7_OFF;
> > +	val |= entry->reg8 << PLL_SWCR1_REG8_OFF;
> > +	ccu_update(swcr1, common, mask, val);
> > +
> > +	mask = PLL_SWCR3_DIV_INT_MASK | PLL_SWCR3_DIV_FRC_MASK;
> > +	val = entry->div_int << PLL_SWCR3_DIV_INT_OFF;
> > +	val |= entry->div_frac << PLL_SWCR3_DIV_FRC_OFF;
> > +	ccu_update(swcr3, common, mask, val);
> > +
> > +	return 0;
> > +}
> > +
> > +static unsigned long ccu_pll_recalc_rate(struct clk_hw *hw,
> > +					 unsigned long parent_rate)
> > +{
> > +	return __get_vco_freq(hw);
> > +}
> > +
> > +static long ccu_pll_round_rate(struct clk_hw *hw, unsigned long rate,
> > +			       unsigned long *prate)
> > +{
> > +	struct ccu_pll *p = hw_to_ccu_pll(hw);
> > +	struct ccu_pll_config *params = &p->pll;
> > +	unsigned long max_rate = 0;
> > +	unsigned int i;
> > +
> > +	for (i = 0; i < params->tbl_size; i++) {
> > +		if (params->rate_tbl[i].rate <= rate) {
> > +			if (max_rate < params->rate_tbl[i].rate)
> > +				max_rate = params->rate_tbl[i].rate;
> > +		}
> > +	}
> > +
> > +	return MAX(max_rate, PLL_MIN_FREQ);
> > +}
> > +
> > +const struct clk_ops spacemit_ccu_pll_ops = {
> > +	.enable		= ccu_pll_enable,
> > +	.disable	= ccu_pll_disable,
> > +	.set_rate	= ccu_pll_set_rate,
> > +	.recalc_rate	= ccu_pll_recalc_rate,
> > +	.round_rate	= ccu_pll_round_rate,
> > +	.is_enabled	= ccu_pll_is_enabled,
> > +};

Re: [PATCH v3 3/3] clk: spacemit: Add clock support for Spacemit K1 SoC

[Dan Carpenter]

Hi Haylen,

kernel test robot noticed the following build warnings:

url:    https://github.com/intel-lab-lkp/linux/commits/Haylen-Chu/dt-bindings-clock-spacemit-Add-clock-controllers-of-Spacemit-K1-SoC/20241128-101248
base:   2d5404caa8c7bb5c4e0435f94b28834ae5456623
patch link:    https://lore.kernel.org/r/20241126143125.9980-7-heylenay%404d2.org
patch subject: [PATCH v3 3/3] clk: spacemit: Add clock support for Spacemit K1 SoC
config: arm64-randconfig-r073-20241207 (https://download.01.org/0day-ci/archive/20241207/202412072123.ne7GnRyJ-lkp@intel.com/config)
compiler: aarch64-linux-gcc (GCC) 14.2.0

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Reported-by: Dan Carpenter <dan.carpenter@linaro.org>
| Closes: https://lore.kernel.org/r/202412072123.ne7GnRyJ-lkp@intel.com/

smatch warnings:
drivers/clk/spacemit/ccu-k1.c:1686 k1_ccu_probe() error: uninitialized symbol 'lock_map'.

vim +/lock_map +1686 drivers/clk/spacemit/ccu-k1.c

e71e4621b06cd42 Haylen Chu 2024-11-26  1651  static int k1_ccu_probe(struct platform_device *pdev)
e71e4621b06cd42 Haylen Chu 2024-11-26  1652  {
e71e4621b06cd42 Haylen Chu 2024-11-26  1653  	const struct spacemit_ccu_data *data;
e71e4621b06cd42 Haylen Chu 2024-11-26  1654  	struct regmap *base_map, *lock_map;
e71e4621b06cd42 Haylen Chu 2024-11-26  1655  	struct device *dev = &pdev->dev;
e71e4621b06cd42 Haylen Chu 2024-11-26  1656  	struct spacemit_ccu_priv *priv;
e71e4621b06cd42 Haylen Chu 2024-11-26  1657  	struct device_node *parent;
e71e4621b06cd42 Haylen Chu 2024-11-26  1658  	int ret;
e71e4621b06cd42 Haylen Chu 2024-11-26  1659  
e71e4621b06cd42 Haylen Chu 2024-11-26  1660  	data = of_device_get_match_data(dev);
e71e4621b06cd42 Haylen Chu 2024-11-26  1661  	if (WARN_ON(!data))
e71e4621b06cd42 Haylen Chu 2024-11-26  1662  		return -EINVAL;
e71e4621b06cd42 Haylen Chu 2024-11-26  1663  
e71e4621b06cd42 Haylen Chu 2024-11-26  1664  	parent   = of_get_parent(dev->of_node);
e71e4621b06cd42 Haylen Chu 2024-11-26  1665  	base_map = syscon_node_to_regmap(parent);
e71e4621b06cd42 Haylen Chu 2024-11-26  1666  	of_node_put(parent);
e71e4621b06cd42 Haylen Chu 2024-11-26  1667  
e71e4621b06cd42 Haylen Chu 2024-11-26  1668  	if (IS_ERR(base_map))
e71e4621b06cd42 Haylen Chu 2024-11-26  1669  		return dev_err_probe(dev, PTR_ERR(base_map),
e71e4621b06cd42 Haylen Chu 2024-11-26  1670  				     "failed to get regmap\n");
e71e4621b06cd42 Haylen Chu 2024-11-26  1671  
e71e4621b06cd42 Haylen Chu 2024-11-26  1672  	if (data->need_pll_lock) {
e71e4621b06cd42 Haylen Chu 2024-11-26  1673  		lock_map = syscon_regmap_lookup_by_phandle(dev->of_node,
e71e4621b06cd42 Haylen Chu 2024-11-26  1674  							   "spacemit,mpmu");
e71e4621b06cd42 Haylen Chu 2024-11-26  1675  		if (IS_ERR(lock_map))
e71e4621b06cd42 Haylen Chu 2024-11-26  1676  			return dev_err_probe(dev, PTR_ERR(lock_map),
e71e4621b06cd42 Haylen Chu 2024-11-26  1677  					     "failed to get lock regmap\n");
e71e4621b06cd42 Haylen Chu 2024-11-26  1678  	}

lock_map not initialized on else path.

e71e4621b06cd42 Haylen Chu 2024-11-26  1679  
e71e4621b06cd42 Haylen Chu 2024-11-26  1680  	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
e71e4621b06cd42 Haylen Chu 2024-11-26  1681  	if (!priv)
e71e4621b06cd42 Haylen Chu 2024-11-26  1682  		return -ENOMEM;
e71e4621b06cd42 Haylen Chu 2024-11-26  1683  
e71e4621b06cd42 Haylen Chu 2024-11-26  1684  	priv->data	= data;
e71e4621b06cd42 Haylen Chu 2024-11-26  1685  	priv->base	= base_map;
e71e4621b06cd42 Haylen Chu 2024-11-26 @1686  	priv->lock_base	= lock_map;
                                                                  ^^^^^^^^^

e71e4621b06cd42 Haylen Chu 2024-11-26  1687  
e71e4621b06cd42 Haylen Chu 2024-11-26  1688  	ret = spacemit_ccu_register(dev, priv);
e71e4621b06cd42 Haylen Chu 2024-11-26  1689  	if (ret)
e71e4621b06cd42 Haylen Chu 2024-11-26  1690  		return dev_err_probe(dev, ret, "failed to register clocks\n");
e71e4621b06cd42 Haylen Chu 2024-11-26  1691  
e71e4621b06cd42 Haylen Chu 2024-11-26  1692  	return 0;
e71e4621b06cd42 Haylen Chu 2024-11-26  1693  }

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [PATCH v3 0/3] Add clock controller support for Spacemit K1

[Krzysztof Kozlowski]

On 26/11/2024 15:31, Haylen Chu wrote:
> The clock tree of Spacemit K1 is managed by several independent
> controllers in different SoC parts. In this series, all clock hardwares
> in APBS, MPMU, APBC and APMU, are implemented. With some changes to UART
> driver, CPU cores and UARTs could be brought up (see below). More clocks
> will be implemented later soon.
> 
> No device tree changes are included since Spacemit K1 UART needs two
> clocks to operate, but for now the driver gets only one. I would like to
> defer the changes until this is resolved.
> 
> This driver has been tested on BananaPi-F3 board and successfully
> brought up I2C, RTC, mmc and ethernet controllers. A clock tree dump
> could be obtained here[1].
> 
> [1]: https://gist.github.com/heylenayy/ebc6316692dd3aff56575dbf0eb4f1a9
> 
> Link: https://developer.spacemit.com/documentation?token=LCrKwWDasiJuROkVNusc2pWTnEb
> 
> Changed from v2
> - dt-binding fixes
What fixes? Be specific, what did you change?

Best regards,
Krzysztof

Re: [PATCH v3 0/3] Add clock controller support for Spacemit K1

[Haylen Chu]

On Tue, Nov 26, 2024 at 03:44:20PM +0100, Krzysztof Kozlowski wrote:
> On 26/11/2024 15:31, Haylen Chu wrote:
> > The clock tree of Spacemit K1 is managed by several independent
> > controllers in different SoC parts. In this series, all clock hardwares
> > in APBS, MPMU, APBC and APMU, are implemented. With some changes to UART
> > driver, CPU cores and UARTs could be brought up (see below). More clocks
> > will be implemented later soon.
> > 
> > No device tree changes are included since Spacemit K1 UART needs two
> > clocks to operate, but for now the driver gets only one. I would like to
> > defer the changes until this is resolved.
> > 
> > This driver has been tested on BananaPi-F3 board and successfully
> > brought up I2C, RTC, mmc and ethernet controllers. A clock tree dump
> > could be obtained here[1].
> > 
> > [1]: https://gist.github.com/heylenayy/ebc6316692dd3aff56575dbf0eb4f1a9
> > 
> > Link: https://developer.spacemit.com/documentation?token=LCrKwWDasiJuROkVNusc2pWTnEb
> > 
> > Changed from v2
> > - dt-binding fixes
> What fixes? Be specific, what did you change?

Sorry for the vague changelog about dt-binding changes... I'm willing
to post a more precise one here,

- drop clocks marked as deprecated by the vendor (CLK_JPF_4KAFBC and
  CLK_JPF_2KAFBC)
- add binding of missing bus clocks
- change input clocks to use frequency-aware and more precise names
- mark input clocks and their names as required
- move the example to the (parent) syscon node and complete it
- misc style fixes

> 
> Best regards,
> Krzysztof

Thanks,
Haylen Chu

Re: [PATCH v3 0/3] Add clock controller support for Spacemit K1

[Emil Renner Berthing]

Haylen Chu wrote:
> The clock tree of Spacemit K1 is managed by several independent
> controllers in different SoC parts. In this series, all clock hardwares
> in APBS, MPMU, APBC and APMU, are implemented. With some changes to UART
> driver, CPU cores and UARTs could be brought up (see below). More clocks
> will be implemented later soon.
>
> No device tree changes are included since Spacemit K1 UART needs two
> clocks to operate, but for now the driver gets only one. I would like to
> defer the changes until this is resolved.

Hi,

Do you have a git tree with these dt changes though? It's impossible to test
this patchset without them.

/Emil

>
> This driver has been tested on BananaPi-F3 board and successfully
> brought up I2C, RTC, mmc and ethernet controllers. A clock tree dump
> could be obtained here[1].
>
> [1]: https://gist.github.com/heylenayy/ebc6316692dd3aff56575dbf0eb4f1a9
>
> Link: https://developer.spacemit.com/documentation?token=LCrKwWDasiJuROkVNusc2pWTnEb
>
> Changed from v2
> - dt-binding fixes
> - misc improvements in code
> - drop unnecessary spinlock in the driver
> - implement missing bus clocks
> - Link to v2: https://lore.kernel.org/all/SEYPR01MB4221829A2CD4D4C1704BABD7D7602@SEYPR01MB4221.apcprd01.prod.exchangelabs.com/
>
> Changed from v1
> - add SoC prefix (k1)
> - relicense dt-binding header
> - misc fixes and style improvements for dt-binding
> - document spacemit,k1-syscon
> - implement all APBS, MPMU, APBC and APMU clocks
> - code cleanup
> - Link to v1: https://lore.kernel.org/all/SEYPR01MB4221B3178F5233EAB5149E41D7902@SEYPR01MB4221.apcprd01.prod.exchangelabs.com/
>
> Haylen Chu (3):
>   dt-bindings: clock: spacemit: Add clock controllers of Spacemit K1 SoC
>   dt-bindings: soc: spacemit: Add spacemit,k1-syscon
>   clk: spacemit: Add clock support for Spacemit K1 SoC
>
>  .../bindings/clock/spacemit,k1-ccu.yaml       |   57 +
>  .../soc/spacemit/spacemit,k1-syscon.yaml      |   86 +
>  drivers/clk/Kconfig                           |    1 +
>  drivers/clk/Makefile                          |    1 +
>  drivers/clk/spacemit/Kconfig                  |   20 +
>  drivers/clk/spacemit/Makefile                 |    5 +
>  drivers/clk/spacemit/ccu-k1.c                 | 1747 +++++++++++++++++
>  drivers/clk/spacemit/ccu_common.h             |   62 +
>  drivers/clk/spacemit/ccu_ddn.c                |  146 ++
>  drivers/clk/spacemit/ccu_ddn.h                |   85 +
>  drivers/clk/spacemit/ccu_mix.c                |  296 +++
>  drivers/clk/spacemit/ccu_mix.h                |  336 ++++
>  drivers/clk/spacemit/ccu_pll.c                |  198 ++
>  drivers/clk/spacemit/ccu_pll.h                |   80 +
>  include/dt-bindings/clock/spacemit,k1-ccu.h   |  246 +++
>  15 files changed, 3366 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/spacemit,k1-ccu.yaml
>  create mode 100644 Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml
>  create mode 100644 drivers/clk/spacemit/Kconfig
>  create mode 100644 drivers/clk/spacemit/Makefile
>  create mode 100644 drivers/clk/spacemit/ccu-k1.c
>  create mode 100644 drivers/clk/spacemit/ccu_common.h
>  create mode 100644 drivers/clk/spacemit/ccu_ddn.c
>  create mode 100644 drivers/clk/spacemit/ccu_ddn.h
>  create mode 100644 drivers/clk/spacemit/ccu_mix.c
>  create mode 100644 drivers/clk/spacemit/ccu_mix.h
>  create mode 100644 drivers/clk/spacemit/ccu_pll.c
>  create mode 100644 drivers/clk/spacemit/ccu_pll.h
>  create mode 100644 include/dt-bindings/clock/spacemit,k1-ccu.h
>
>
> base-commit: 2d5404caa8c7bb5c4e0435f94b28834ae5456623
> prerequisite-patch-id: 47dcf6861f7d434d25855b379e6d7ef4ce369c9c
> prerequisite-patch-id: 77787fe82911923aff15ccf565e8fa451538c3a6
> prerequisite-patch-id: b0bdb1742d96c5738f05262c3b0059102761390b
> prerequisite-patch-id: 3927d39d8d77e35d5bfe53d9950da574ff8f2054
> prerequisite-patch-id: a98039136a4796252a6029e474f03906f2541643
> prerequisite-patch-id: c95f6dc0547a2a63a76e3cba0cf5c623b212b4e6
> prerequisite-patch-id: 66e750e438ee959ddc2a6f0650814a2d8c989139
> prerequisite-patch-id: 29a0fd8c36c1a4340f0d0b68a4c34d2b8abfb1ab
> prerequisite-patch-id: 0bdfff661c33c380d1cf00a6c68688e05f88c0b3
> prerequisite-patch-id: 99f15718e0bfbb7ed1a96dfa19f35841b004dae9
> --
> 2.47.0
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH v3 0/3] Add clock controller support for Spacemit K1

[Yixun Lan]

On 03:54 Wed 04 Dec     , Emil Renner Berthing wrote:
> Haylen Chu wrote:
> > The clock tree of Spacemit K1 is managed by several independent
> > controllers in different SoC parts. In this series, all clock hardwares
> > in APBS, MPMU, APBC and APMU, are implemented. With some changes to UART
> > driver, CPU cores and UARTs could be brought up (see below). More clocks
> > will be implemented later soon.
> >
> > No device tree changes are included since Spacemit K1 UART needs two
> > clocks to operate, but for now the driver gets only one. I would like to
> > defer the changes until this is resolved.
> 
> Hi,
> 
> Do you have a git tree with these dt changes though? It's impossible to test
> this patchset without them.
> 
> /Emil

I'd suggest to include the dts part patch when sending next version..

-- 
Yixun Lan (dlan)
Gentoo Linux Developer
GPG Key ID AABEFD55

Re: [PATCH v3 0/3] Add clock controller support for Spacemit K1

[Haylen Chu]

On Wed, Dec 04, 2024 at 03:54:25AM -0800, Emil Renner Berthing wrote:
> Haylen Chu wrote:
> > The clock tree of Spacemit K1 is managed by several independent
> > controllers in different SoC parts. In this series, all clock hardwares
> > in APBS, MPMU, APBC and APMU, are implemented. With some changes to UART
> > driver, CPU cores and UARTs could be brought up (see below). More clocks
> > will be implemented later soon.
> >
> > No device tree changes are included since Spacemit K1 UART needs two
> > clocks to operate, but for now the driver gets only one. I would like to
> > defer the changes until this is resolved.
> 
> Hi,
> 
> Do you have a git tree with these dt changes though? It's impossible to test
> this patchset without them.
> 
> /Emil

I'll send the dt changes together in v4, as suggested by Yixun.

Thanks,
Haylen