Re: [PATCH v2 5/6] arm64: dts: qcom: ipq5332: Add PCIe related nodes

Konrad Dybcio
2024-12-05T16:55:33Z

On 4.12.2024 12:33 PM, Varadarajan Narayanan wrote:
> From: Praveenkumar I <quic_ipkumar@quicinc.com>
>
> Add phy and controller nodes for pcie0_x1 and pcie1_x2.
>
> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> ---

[...]

> + pcie0: pcie@20000000 {
> + compatible = "qcom,pcie-ipq5332";
> + reg = <0x20000000 0xf1d>,
> + <0x20000F20 0xa8>,

Please use lowercase hex

> + <0x20001000 0x1000>,
> + <0x00080000 0x3000>,
> + <0x20100000 0x1000>;
> + reg-names = "dbi", "elbi", "atu", "parf", "config";

Please also add the MHI region
> + device_type = "pci";
> + linux,pci-domain = <0>;
> + bus-range = <0x00 0xff>;
> + num-lanes = <1>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> +
> + ranges = <0x01000000 0 0x20200000 0x20200000 0 0x00100000>, /* I/O */
> + <0x02000000 0 0x20300000 0x20300000 0 0x0fd00000>; /* MEM */

Please drop these comments
> +
> + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "msi0",
> + "msi1",
> + "msi2",
> + "msi3",
> + "msi4",
> + "msi5",
> + "msi6",
> + "msi7";
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0x7>;
> + interrupt-map = <0 0 0 1 &intc 0 0 35 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
> + <0 0 0 2 &intc 0 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
> + <0 0 0 3 &intc 0 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
> + <0 0 0 4 &intc 0 0 38 IRQ_TYPE_LEVEL_HIGH>; /* int_d */

And these too

> +
> + clocks = <&gcc GCC_PCIE3X1_0_AXI_M_CLK>,
> + <&gcc GCC_PCIE3X1_0_AXI_S_CLK>,
> + <&gcc GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK>,
> + <&gcc GCC_PCIE3X1_0_RCHG_CLK>,
> + <&gcc GCC_PCIE3X1_0_AHB_CLK>,
> + <&gcc GCC_PCIE3X1_0_AUX_CLK>;
> +
Stray newline

> + clock-names = "axi_m",
> + "axi_s",
> + "axi_bridge",
> + "rchng",
> + "ahb",
> + "aux";
> +
> + resets = <&gcc GCC_PCIE3X1_0_PIPE_ARES>,
> + <&gcc GCC_PCIE3X1_0_CORE_STICKY_ARES>,
> + <&gcc GCC_PCIE3X1_0_AXI_S_STICKY_ARES>,
> + <&gcc GCC_PCIE3X1_0_AXI_S_CLK_ARES>,
> + <&gcc GCC_PCIE3X1_0_AXI_M_STICKY_ARES>,
> + <&gcc GCC_PCIE3X1_0_AXI_M_CLK_ARES>,
> + <&gcc GCC_PCIE3X1_0_AUX_CLK_ARES>,
> + <&gcc GCC_PCIE3X1_0_AHB_CLK_ARES>;
> +
Ditto

> + reset-names = "pipe",
> + "sticky",
> + "axi_s_sticky",
> + "axi_s",
> + "axi_m_sticky",
> + "axi_m",
> + "aux",
> + "ahb";
> +
> + phys = <&pcie0_phy>;
> + phy-names = "pciephy";
> +
> + interconnects = <&gcc MASTER_SNOC_PCIE3_1_M &gcc SLAVE_SNOC_PCIE3_1_M>,
> + <&gcc MASTER_ANOC_PCIE3_1_S &gcc SLAVE_ANOC_PCIE3_1_S>;
> + interconnect-names = "pcie-mem", "cpu-pcie";
> +
> + msi-map = <0x0 &v2m0 0x0 0xffd>;
> + status = "disabled";
> + };
> +
> + pcie1: pcie@18000000 {

Same comments as pcie0

Konrad