[PATCH v2 1/6] dt-bindings: phy: qcom,uniphy-pcie: Document PCIe uniphy

Varadarajan Narayanan
2024-12-04T11:34:23Z

From: Nitheesh Sekar <quic_nsekar@quicinc.com>

Document the Qualcomm UNIPHY PCIe 28LP present in IPQ5332.

Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
v2: Rename the file to match the compatible
Drop 'driver' from title
Dropped 'clock-names'
Fixed 'reset-names'
--
.../bindings/phy/qcom,uniphy-pcie.yaml | 82 +++++++++++++++++++
1 file changed, 82 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/qcom,uniphy-pcie.yaml

diff --git a/Documentation/devicetree/bindings/phy/qcom,uniphy-pcie.yaml b/Documentation/devicetree/bindings/phy/qcom,uniphy-pcie.yaml
new file mode 100644
index 000000000000..e0ad98a9f324
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom,uniphy-pcie.yaml
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/qcom,uniphy-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm UNIPHY PCIe 28LP PHY
+
+maintainers:
+ - Nitheesh Sekar <quic_nsekar@quicinc.com>
+ - Varadarajan Narayanan <quic_varada@quicinc.com>
+
+description:
+ PCIe and USB combo PHY found in Qualcomm IPQ5332 SoC
+
+properties:
+ compatible:
+ enum:
+ - qcom,ipq5332-uniphy-pcie-gen3x1
+ - qcom,ipq5332-uniphy-pcie-gen3x2
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 2
+
+ resets:
+ minItems: 2
+ maxItems: 3
+
+ reset-names:
+ minItems: 2
+ items:
+ - const: phy
+ - const: phy_ahb
+ - const: phy_cfg
+
+ "#phy-cells":
+ const: 0
+
+ "#clock-cells":
+ const: 0
+
+ clock-output-names:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - resets
+ - reset-names
+ - clocks
+ - "#phy-cells"
+ - "#clock-cells"
+ - clock-output-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,ipq5332-gcc.h>
+
+ pcie0_phy: phy@4b0000 {
+ compatible = "qcom,ipq5332-uniphy-pcie-gen3x1";
+ reg = <0x004b0000 0x800>;
+
+ clocks = <&gcc GCC_PCIE3X1_0_PIPE_CLK>,
+ <&gcc GCC_PCIE3X1_PHY_AHB_CLK>;
+
+ resets = <&gcc GCC_PCIE3X1_0_PHY_BCR>,
+ <&gcc GCC_PCIE3X1_PHY_AHB_CLK_ARES>,
+ <&gcc GCC_PCIE3X1_0_PHY_PHY_BCR>;
+ reset-names = "phy",
+ "phy_ahb",
+ "phy_cfg";
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie0_pipe_clk_src";
+
+ #phy-cells = <0>;
+ };
--
2.34.1