Re: [PATCH v3 2/2] regulator: pf9453: add PMIC PF9453 support

[Frank Li <Frank.li@nxp.com>]

On Sat, Dec 14, 2024 at 11:57:59AM +0100, Christophe JAILLET wrote:
> Le 13/12/2024 à 21:46, Frank Li a écrit :
> > From: Joy Zou <joy.zou-3arQi8VN3Tc@public.gmane.org>
> >
> > Support new PMIC PF9453, which is totally difference with PCA9450. So
> > create new file for it.
> >
> > The PF9453 is a single chip Power Management IC (PMIC) specifically
> > designed for i.MX 91 processor. It provides power supply solutions for IoT
> > (Internet of Things), smart appliance, and portable applications where size
> > and efficiency are critical. The device provides four high efficiency
> > step-down regulators, three LDOs, one 400 mA load switch and 32.768 kHz
> > crystal oscillator driver.
>
> ...
>
> > +/* PF9453_REG_BUCK2_CTRL bits */
> > +#define BUCK2_RAMP_MASK			GENMASK(7, 4)
>
> This was 0xC0 in previous patch, so GENMASK(7, 6) if I'm correct.
> Which one is the good one?
>
> (the datasheet I've found does not give any details, so I can't check)

Good capture! It should be GENMASK(7, 6)

Frank

>
> > +#define BUCK2_RAMP_25MV			0x0
> > +#define BUCK2_RAMP_12P5MV		0x1
> > +#define BUCK2_RAMP_6P25MV		0x2
> > +#define BUCK2_RAMP_3P125MV		0x3
>
> ...
>
> > +/* PF9453_REG_LDO2_VOLT bits */
> > +#define LDO2_EN_MASK			GENMASK(1, 0)
> > +#define LDO2OUT_MASK			GENMASK(6, 0)
> > +
> > +/* PF9453_REG_LDOSNVS_VOLT bits */
> > +#define LDOSNVS_EN_MASK			0x1
>
> GENMASK(0, 0) to be consistent?
>
> > +#define LDOSNVSCFG1_MASK		GENMASK(6, 0)
> > +
> > +/* PF9453_REG_IRQ bits */
> > +#define IRQ_RSVD			0x80
> > +#define IRQ_RSTB			0x40
> > +#define IRQ_ONKEY			0x20
> > +#define IRQ_RESETKEY			0x10
> > +#define IRQ_VR_FLT1			0x08
> > +#define IRQ_LOWVSYS			0x04
> > +#define IRQ_THERM_100			0x02
> > +#define IRQ_THERM_80			0x01
> > +
> > +/* PF9453_REG_RESET_CTRL bits */
> > +#define WDOG_B_CFG_MASK			GENMASK(7, 4)
>
> This was 0xC0 in previous patch, so GENMASK(7, 6) if I'm correct.
> Which one is the good one?
>
> > +#define WDOG_B_CFG_NONE			0x00
> > +#define WDOG_B_CFG_WARM			0x40
> > +#define WDOG_B_CFG_COLD			0x80
>
> ...
>
> CJ