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Thu, 09 Jan 2025 13:37:09 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 509Db8oW002112 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 9 Jan 2025 13:37:08 GMT Received: from hu-wasimn-hyd.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 9 Jan 2025 05:37:01 -0800 Date: Thu, 9 Jan 2025 19:06:53 +0530 From: Wasim Nazir To: Bjorn Andersson CC: Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Subject: Re: [PATCH v5 5/6] arm64: dts: qcom: Add support for QCS9075 Ride & Ride-r3 Message-ID: References: <20241229152332.3068172-1-quic_wasimn@quicinc.com> <20241229152332.3068172-6-quic_wasimn@quicinc.com> <44tjbxjrigbfu4dfrlbvdprablyhf3i5u4fvg3iwucfvmvljqv@t43py5mb4rg3> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <44tjbxjrigbfu4dfrlbvdprablyhf3i5u4fvg3iwucfvmvljqv@t43py5mb4rg3> X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: kMUdYNEfErYuff4I370RGf5BOYEZ5Hzc X-Proofpoint-GUID: kMUdYNEfErYuff4I370RGf5BOYEZ5Hzc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 malwarescore=0 mlxlogscore=999 spamscore=0 impostorscore=0 priorityscore=1501 clxscore=1015 adultscore=0 phishscore=0 bulkscore=0 lowpriorityscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501090109 On Mon, Jan 06, 2025 at 05:59:01PM -0600, Bjorn Andersson wrote: > On Sun, Dec 29, 2024 at 08:53:31PM +0530, Wasim Nazir wrote: > > Add device tree support for QCS9075 Ride & Ride-r3 boards. > > > > QCS9075 lacks the safety monitoring features of Safety-Island (SAIL) > > subsystem which is available in QCS9100, and it affects thermal > > management. > > > > Also, between ride and ride-r3 ethernet phy is different. > > Ride uses 1G ethernet phy while ride-r3 uses 2.5G ethernet phy. > > > > This commit message is written under the assumption that the reader > first reads the patch, to determine what QCS9075 subtracts features > from. > > Please describe what the QCS9075 Ride and Ride R3 are, if it's just a > variant of QCS9100 without SAIL, write that - and if that is all the > difference, then Dmitry's request makes total sense. > 9075 is not derived from 9100 but from 8775, though difference between 9075 & 9100 is only SAIL. And in commit message I have tried to add details to differentiate between 9075 & 9100 and most importantly to highlight why we need sperate DT for 9075. Will add more details in commit message instead of adding it in cover-letter. Also, I am convinced to proceed with Dmitry's approach to structure the DT. > > Also, subject prefix doesn't match upstream style. Prefix with the > subsystem/platform/device and avoid "for XYZ". See "git log" on a few > of the other files to see how it should look like. Sure will change this accordingly. > > Thanks, > Bjorn > > > Signed-off-by: Wasim Nazir > > --- > > arch/arm64/boot/dts/qcom/Makefile | 2 + > > arch/arm64/boot/dts/qcom/qcs9075-ride-r3.dts | 46 ++++++++++++++++++++ > > arch/arm64/boot/dts/qcom/qcs9075-ride.dts | 46 ++++++++++++++++++++ > > 3 files changed, 94 insertions(+) > > create mode 100644 arch/arm64/boot/dts/qcom/qcs9075-ride-r3.dts > > create mode 100644 arch/arm64/boot/dts/qcom/qcs9075-ride.dts > > > > diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile > > index 78613a1bd34a..41cb2bbd3472 100644 > > --- a/arch/arm64/boot/dts/qcom/Makefile > > +++ b/arch/arm64/boot/dts/qcom/Makefile > > @@ -118,6 +118,8 @@ dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb > > dtb-$(CONFIG_ARCH_QCOM) += qcs8300-ride.dtb > > dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb > > dtb-$(CONFIG_ARCH_QCOM) += qcs9075-rb8.dtb > > +dtb-$(CONFIG_ARCH_QCOM) += qcs9075-ride.dtb > > +dtb-$(CONFIG_ARCH_QCOM) += qcs9075-ride-r3.dtb > > dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride.dtb > > dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride-r3.dtb > > dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb > > diff --git a/arch/arm64/boot/dts/qcom/qcs9075-ride-r3.dts b/arch/arm64/boot/dts/qcom/qcs9075-ride-r3.dts > > new file mode 100644 > > index 000000000000..d9a8956d3a76 > > --- /dev/null > > +++ b/arch/arm64/boot/dts/qcom/qcs9075-ride-r3.dts > > @@ -0,0 +1,46 @@ > > +// SPDX-License-Identifier: BSD-3-Clause > > +/* > > + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. > > + */ > > +/dts-v1/; > > + > > +#include "sa8775p-ride.dtsi" > > + > > +/ { > > + model = "Qualcomm Technologies, Inc. QCS9075 Ride Rev3"; > > + compatible = "qcom,qcs9075-ride-r3", "qcom,qcs9075", "qcom,sa8775p"; > > +}; > > + > > +ðernet0 { > > + phy-mode = "2500base-x"; > > +}; > > + > > +ðernet1 { > > + phy-mode = "2500base-x"; > > +}; > > + > > +&mdio { > > + compatible = "snps,dwmac-mdio"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + sgmii_phy0: phy@8 { > > + compatible = "ethernet-phy-id31c3.1c33"; > > + reg = <0x8>; > > + device_type = "ethernet-phy"; > > + interrupts-extended = <&tlmm 7 IRQ_TYPE_EDGE_FALLING>; > > + reset-gpios = <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>; > > + reset-assert-us = <11000>; > > + reset-deassert-us = <70000>; > > + }; > > + > > + sgmii_phy1: phy@0 { > > + compatible = "ethernet-phy-id31c3.1c33"; > > + reg = <0x0>; > > + device_type = "ethernet-phy"; > > + interrupts-extended = <&tlmm 26 IRQ_TYPE_EDGE_FALLING>; > > + reset-gpios = <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>; > > + reset-assert-us = <11000>; > > + reset-deassert-us = <70000>; > > + }; > > +}; > > diff --git a/arch/arm64/boot/dts/qcom/qcs9075-ride.dts b/arch/arm64/boot/dts/qcom/qcs9075-ride.dts > > new file mode 100644 > > index 000000000000..3b524359a72d > > --- /dev/null > > +++ b/arch/arm64/boot/dts/qcom/qcs9075-ride.dts > > @@ -0,0 +1,46 @@ > > +// SPDX-License-Identifier: BSD-3-Clause > > +/* > > + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. > > + */ > > +/dts-v1/; > > + > > +#include "sa8775p-ride.dtsi" > > + > > +/ { > > + model = "Qualcomm Technologies, Inc. QCS9075 Ride"; > > + compatible = "qcom,qcs9075-ride", "qcom,qcs9075", "qcom,sa8775p"; > > +}; > > + > > +ðernet0 { > > + phy-mode = "sgmii"; > > +}; > > + > > +ðernet1 { > > + phy-mode = "sgmii"; > > +}; > > + > > +&mdio { > > + compatible = "snps,dwmac-mdio"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + sgmii_phy0: phy@8 { > > + compatible = "ethernet-phy-id0141.0dd4"; > > + reg = <0x8>; > > + device_type = "ethernet-phy"; > > + interrupts-extended = <&tlmm 7 IRQ_TYPE_EDGE_FALLING>; > > + reset-gpios = <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>; > > + reset-assert-us = <11000>; > > + reset-deassert-us = <70000>; > > + }; > > + > > + sgmii_phy1: phy@a { > > + compatible = "ethernet-phy-id0141.0dd4"; > > + reg = <0xa>; > > + device_type = "ethernet-phy"; > > + interrupts-extended = <&tlmm 26 IRQ_TYPE_EDGE_FALLING>; > > + reset-gpios = <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>; > > + reset-assert-us = <11000>; > > + reset-deassert-us = <70000>; > > + }; > > +}; > > -- > > 2.47.0 > > Thanks & Regards, Wasim