* [PATCH 00/11] Add Support for RZ/G3E ICU
@ 2025-01-20 9:46 Biju Das
2025-01-20 9:46 ` [PATCH 01/11] dt-bindings: interrupt-controller: renesas,rzv2h-icu: Document RZ/G3E SoC Biju Das
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Biju Das @ 2025-01-20 9:46 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, Fabrizio Castro,
devicetree, linux-renesas-soc, Prabhakar Mahadev Lad, Biju Das
The ICU block on the RZ/G3E SoC is almost identical to the one found on
the RZ/V2H SoC, with the following differences:
- The TINT register offset is 0x830 compared to ox30 on RZ/V2H.
- The number of supported GPIO interrupts for TINT selection is 141
instead of 86.
- The pin index and TINT selection index are not in the 1:1 map
- The number of TSSR registers is 15 instead of 8
- Each TSSR register can program 2 TINTs instead of 4 TINTs
Add support for the RZ/G3E ICU driver.
Biju Das (11):
dt-bindings: interrupt-controller: renesas,rzv2h-icu: Document RZ/G3E
SoC
clk: renesas: r9a09g047: Add ICU clock/reset
irqchip/renesas-rzv2h: Drop irqchip from struct rzv2h_icu_priv
irqchip/renesas-rzv2h: Simplify rzv2h_icu_init()
irqchip/renesas-rzv2h: Add struct rzv2h_hw_info with t_offs variable
irqchip/renesas-rzv2h: Add max_tssel variable to struct rzv2h_hw_info
irqchip/renesas-rzv2h: Add tssr_k variable to struct rzv2h_hw_info
irqchip/renesas-rzv2h: Add tssel_mask and tssel_shift variables to
struct rzv2h_hw_info
irqchip/renesas-rzv2h: Add tien variable to struct rzv2h_hw_info
irqchip/renesas-rzv2h: Add RZ/G3E support
arm64: dts: renesas: r9a09g047: Add icu node
.../renesas,rzv2h-icu.yaml | 6 +-
arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 108 ++++++++++++
drivers/clk/renesas/r9a09g047-cpg.c | 3 +
drivers/irqchip/irq-renesas-rzv2h.c | 159 +++++++++++++-----
4 files changed, 229 insertions(+), 47 deletions(-)
--
2.43.0
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH 01/11] dt-bindings: interrupt-controller: renesas,rzv2h-icu: Document RZ/G3E SoC 2025-01-20 9:46 [PATCH 00/11] Add Support for RZ/G3E ICU Biju Das @ 2025-01-20 9:46 ` Biju Das 2025-01-23 9:41 ` Fabrizio Castro 2025-01-23 22:53 ` Rob Herring (Arm) 2025-01-20 9:47 ` [PATCH 11/11] arm64: dts: renesas: r9a09g047: Add icu node Biju Das 2025-01-21 17:32 ` [PATCH 00/11] Add Support for RZ/G3E ICU Tommaso Merciai 2 siblings, 2 replies; 7+ messages in thread From: Biju Das @ 2025-01-20 9:46 UTC (permalink / raw) To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, Fabrizio Castro, devicetree, linux-renesas-soc, Prabhakar Mahadev Lad, Biju Das Document RZ/G3E (R9A09G047) ICU bindings. The ICU block on the RZ/G3E SoC is almost identical to the one found on the RZ/V2H SoC, with the following differences: - The TINT register offset is 0x830 compared to ox30 on RZ/V2H. - The number of supported GPIO interrupts for TINT selection is 141 instead of 86. - The pin index and TINT selection index are not in the 1:1 map - The number of TSSR registers is 15 instead of 8 - Each TSSR register can program 2 TINTs instead of 4 TINTs Hence new compatible string "renesas,r9a09g047-icu" is added for RZ/G3E SoC. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- .../bindings/interrupt-controller/renesas,rzv2h-icu.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml index d7ef4f1323a7..3f99c8645767 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/interrupt-controller/renesas,rzv2h-icu.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Renesas RZ/V2H(P) Interrupt Control Unit +title: Renesas RZ/{G3E,V2H(P)} Interrupt Control Unit maintainers: - Fabrizio Castro <fabrizio.castro.jz@renesas.com> @@ -20,7 +20,9 @@ description: properties: compatible: - const: renesas,r9a09g057-icu # RZ/V2H(P) + enum: + - renesas,r9a09g047-icu # RZ/G3E + - renesas,r9a09g057-icu # RZ/V2H(P) '#interrupt-cells': description: The first cell is the SPI number of the NMI or the -- 2.43.0 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* RE: [PATCH 01/11] dt-bindings: interrupt-controller: renesas,rzv2h-icu: Document RZ/G3E SoC 2025-01-20 9:46 ` [PATCH 01/11] dt-bindings: interrupt-controller: renesas,rzv2h-icu: Document RZ/G3E SoC Biju Das @ 2025-01-23 9:41 ` Fabrizio Castro 2025-01-23 22:53 ` Rob Herring (Arm) 1 sibling, 0 replies; 7+ messages in thread From: Fabrizio Castro @ 2025-01-23 9:41 UTC (permalink / raw) To: Biju Das, Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar Mahadev Lad, biju.das.au Hi Biju, Thanks for your patch! > From: Biju Das <biju.das.jz@bp.renesas.com> > Sent: 20 January 2025 09:47 > Subject: [PATCH 01/11] dt-bindings: interrupt-controller: renesas,rzv2h-icu: Document RZ/G3E SoC > > Document RZ/G3E (R9A09G047) ICU bindings. The ICU block on the RZ/G3E > SoC is almost identical to the one found on the RZ/V2H SoC, with the > following differences: > - The TINT register offset is 0x830 compared to ox30 on RZ/V2H. > - The number of supported GPIO interrupts for TINT selection is 141 > instead of 86. > - The pin index and TINT selection index are not in the 1:1 map > - The number of TSSR registers is 15 instead of 8 > - Each TSSR register can program 2 TINTs instead of 4 TINTs > > Hence new compatible string "renesas,r9a09g047-icu" is added for RZ/G3E > SoC. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Cheers, Fab > --- > .../bindings/interrupt-controller/renesas,rzv2h-icu.yaml | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml > b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml > index d7ef4f1323a7..3f99c8645767 100644 > --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml > +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml > @@ -4,7 +4,7 @@ > $id: http://devicetree.org/schemas/interrupt-controller/renesas,rzv2h-icu.yaml# > $schema: http://devicetree.org/meta-schemas/core.yaml# > > -title: Renesas RZ/V2H(P) Interrupt Control Unit > +title: Renesas RZ/{G3E,V2H(P)} Interrupt Control Unit > > maintainers: > - Fabrizio Castro <fabrizio.castro.jz@renesas.com> > @@ -20,7 +20,9 @@ description: > > properties: > compatible: > - const: renesas,r9a09g057-icu # RZ/V2H(P) > + enum: > + - renesas,r9a09g047-icu # RZ/G3E > + - renesas,r9a09g057-icu # RZ/V2H(P) > > '#interrupt-cells': > description: The first cell is the SPI number of the NMI or the > -- > 2.43.0 ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 01/11] dt-bindings: interrupt-controller: renesas,rzv2h-icu: Document RZ/G3E SoC 2025-01-20 9:46 ` [PATCH 01/11] dt-bindings: interrupt-controller: renesas,rzv2h-icu: Document RZ/G3E SoC Biju Das 2025-01-23 9:41 ` Fabrizio Castro @ 2025-01-23 22:53 ` Rob Herring (Arm) 1 sibling, 0 replies; 7+ messages in thread From: Rob Herring (Arm) @ 2025-01-23 22:53 UTC (permalink / raw) To: Biju Das Cc: Krzysztof Kozlowski, Conor Dooley, Biju Das, Magnus Damm, Geert Uytterhoeven, Prabhakar Mahadev Lad, Thomas Gleixner, devicetree, linux-renesas-soc, Fabrizio Castro On Mon, 20 Jan 2025 09:46:57 +0000, Biju Das wrote: > Document RZ/G3E (R9A09G047) ICU bindings. The ICU block on the RZ/G3E > SoC is almost identical to the one found on the RZ/V2H SoC, with the > following differences: > - The TINT register offset is 0x830 compared to ox30 on RZ/V2H. > - The number of supported GPIO interrupts for TINT selection is 141 > instead of 86. > - The pin index and TINT selection index are not in the 1:1 map > - The number of TSSR registers is 15 instead of 8 > - Each TSSR register can program 2 TINTs instead of 4 TINTs > > Hence new compatible string "renesas,r9a09g047-icu" is added for RZ/G3E > SoC. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > --- > .../bindings/interrupt-controller/renesas,rzv2h-icu.yaml | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > Acked-by: Rob Herring (Arm) <robh@kernel.org> ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 11/11] arm64: dts: renesas: r9a09g047: Add icu node 2025-01-20 9:46 [PATCH 00/11] Add Support for RZ/G3E ICU Biju Das 2025-01-20 9:46 ` [PATCH 01/11] dt-bindings: interrupt-controller: renesas,rzv2h-icu: Document RZ/G3E SoC Biju Das @ 2025-01-20 9:47 ` Biju Das 2025-01-23 9:47 ` Fabrizio Castro 2025-01-21 17:32 ` [PATCH 00/11] Add Support for RZ/G3E ICU Tommaso Merciai 2 siblings, 1 reply; 7+ messages in thread From: Biju Das @ 2025-01-20 9:47 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, linux-renesas-soc, devicetree, Prabhakar Mahadev Lad, Biju Das Add interrupt control node to RZ/G3E ("R9A09G047") SoC DTSI and add icu as interrupt-parent of pincontrol. Also, define the ICU IRQs for board DT users. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 108 +++++++++++++++++++++ 1 file changed, 108 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index 133aa3272d3a..0beac052f208 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -8,6 +8,24 @@ #include <dt-bindings/clock/renesas,r9a09g047-cpg.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#define RZG3E_NMI 0 +#define RZG3E_IRQ0 1 +#define RZG3E_IRQ1 2 +#define RZG3E_IRQ2 3 +#define RZG3E_IRQ3 4 +#define RZG3E_IRQ4 5 +#define RZG3E_IRQ5 6 +#define RZG3E_IRQ6 7 +#define RZG3E_IRQ7 8 +#define RZG3E_IRQ8 9 +#define RZG3E_IRQ9 10 +#define RZG3E_IRQ10 11 +#define RZG3E_IRQ11 12 +#define RZG3E_IRQ12 13 +#define RZG3E_IRQ13 14 +#define RZG3E_IRQ14 15 +#define RZG3E_IRQ15 16 + / { compatible = "renesas,r9a09g047"; #address-cells = <2>; @@ -131,6 +149,95 @@ soc: soc { #size-cells = <2>; ranges; + icu: interrupt-controller@10400000 { + compatible = "renesas,r9a09g047-icu"; + reg = <0 0x10400000 0 0x10000>; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "nmi", + "port_irq0", "port_irq1", "port_irq2", + "port_irq3", "port_irq4", "port_irq5", + "port_irq6", "port_irq7", "port_irq8", + "port_irq9", "port_irq10", "port_irq11", + "port_irq12", "port_irq13", "port_irq14", + "port_irq15", + "tint0", "tint1", "tint2", "tint3", + "tint4", "tint5", "tint6", "tint7", + "tint8", "tint9", "tint10", "tint11", + "tint12", "tint13", "tint14", "tint15", + "tint16", "tint17", "tint18", "tint19", + "tint20", "tint21", "tint22", "tint23", + "tint24", "tint25", "tint26", "tint27", + "tint28", "tint29", "tint30", "tint31", + "int-ca55-0", "int-ca55-1", + "int-ca55-2", "int-ca55-3", + "icu-error-ca55", + "gpt-u0-gtciada", "gpt-u0-gtciadb", + "gpt-u1-gtciada", "gpt-u1-gtciadb"; + clocks = <&cpg CPG_MOD 0x5>; + power-domains = <&cpg>; + resets = <&cpg 0x36>; + }; + pinctrl: pinctrl@10410000 { compatible = "renesas,r9a09g047-pinctrl"; reg = <0 0x10410000 0 0x10000>; @@ -140,6 +247,7 @@ pinctrl: pinctrl@10410000 { gpio-ranges = <&pinctrl 0 0 232>; #interrupt-cells = <2>; interrupt-controller; + interrupt-parent = <&icu>; power-domains = <&cpg>; resets = <&cpg 0xa5>, <&cpg 0xa6>; }; -- 2.43.0 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* RE: [PATCH 11/11] arm64: dts: renesas: r9a09g047: Add icu node 2025-01-20 9:47 ` [PATCH 11/11] arm64: dts: renesas: r9a09g047: Add icu node Biju Das @ 2025-01-23 9:47 ` Fabrizio Castro 0 siblings, 0 replies; 7+ messages in thread From: Fabrizio Castro @ 2025-01-23 9:47 UTC (permalink / raw) To: Biju Das, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar Mahadev Lad, biju.das.au Hi Biju, Thanks for your patch! > From: Biju Das <biju.das.jz@bp.renesas.com> > Sent: 20 January 2025 09:47 > Subject: [PATCH 11/11] arm64: dts: renesas: r9a09g047: Add icu node > > Add interrupt control node to RZ/G3E ("R9A09G047") SoC DTSI > and add icu as interrupt-parent of pincontrol. > > Also, define the ICU IRQs for board DT users. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Cheers, Fab > --- > arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 108 +++++++++++++++++++++ > 1 file changed, 108 insertions(+) > > diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi > index 133aa3272d3a..0beac052f208 100644 > --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi > +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi > @@ -8,6 +8,24 @@ > #include <dt-bindings/clock/renesas,r9a09g047-cpg.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > > +#define RZG3E_NMI 0 > +#define RZG3E_IRQ0 1 > +#define RZG3E_IRQ1 2 > +#define RZG3E_IRQ2 3 > +#define RZG3E_IRQ3 4 > +#define RZG3E_IRQ4 5 > +#define RZG3E_IRQ5 6 > +#define RZG3E_IRQ6 7 > +#define RZG3E_IRQ7 8 > +#define RZG3E_IRQ8 9 > +#define RZG3E_IRQ9 10 > +#define RZG3E_IRQ10 11 > +#define RZG3E_IRQ11 12 > +#define RZG3E_IRQ12 13 > +#define RZG3E_IRQ13 14 > +#define RZG3E_IRQ14 15 > +#define RZG3E_IRQ15 16 > + > / { > compatible = "renesas,r9a09g047"; > #address-cells = <2>; > @@ -131,6 +149,95 @@ soc: soc { > #size-cells = <2>; > ranges; > > + icu: interrupt-controller@10400000 { > + compatible = "renesas,r9a09g047-icu"; > + reg = <0 0x10400000 0 0x10000>; > + #interrupt-cells = <2>; > + #address-cells = <0>; > + interrupt-controller; > + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "nmi", > + "port_irq0", "port_irq1", "port_irq2", > + "port_irq3", "port_irq4", "port_irq5", > + "port_irq6", "port_irq7", "port_irq8", > + "port_irq9", "port_irq10", "port_irq11", > + "port_irq12", "port_irq13", "port_irq14", > + "port_irq15", > + "tint0", "tint1", "tint2", "tint3", > + "tint4", "tint5", "tint6", "tint7", > + "tint8", "tint9", "tint10", "tint11", > + "tint12", "tint13", "tint14", "tint15", > + "tint16", "tint17", "tint18", "tint19", > + "tint20", "tint21", "tint22", "tint23", > + "tint24", "tint25", "tint26", "tint27", > + "tint28", "tint29", "tint30", "tint31", > + "int-ca55-0", "int-ca55-1", > + "int-ca55-2", "int-ca55-3", > + "icu-error-ca55", > + "gpt-u0-gtciada", "gpt-u0-gtciadb", > + "gpt-u1-gtciada", "gpt-u1-gtciadb"; > + clocks = <&cpg CPG_MOD 0x5>; > + power-domains = <&cpg>; > + resets = <&cpg 0x36>; > + }; > + > pinctrl: pinctrl@10410000 { > compatible = "renesas,r9a09g047-pinctrl"; > reg = <0 0x10410000 0 0x10000>; > @@ -140,6 +247,7 @@ pinctrl: pinctrl@10410000 { > gpio-ranges = <&pinctrl 0 0 232>; > #interrupt-cells = <2>; > interrupt-controller; > + interrupt-parent = <&icu>; > power-domains = <&cpg>; > resets = <&cpg 0xa5>, <&cpg 0xa6>; > }; > -- > 2.43.0 > ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 00/11] Add Support for RZ/G3E ICU 2025-01-20 9:46 [PATCH 00/11] Add Support for RZ/G3E ICU Biju Das 2025-01-20 9:46 ` [PATCH 01/11] dt-bindings: interrupt-controller: renesas,rzv2h-icu: Document RZ/G3E SoC Biju Das 2025-01-20 9:47 ` [PATCH 11/11] arm64: dts: renesas: r9a09g047: Add icu node Biju Das @ 2025-01-21 17:32 ` Tommaso Merciai 2 siblings, 0 replies; 7+ messages in thread From: Tommaso Merciai @ 2025-01-21 17:32 UTC (permalink / raw) To: Biju Das Cc: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Geert Uytterhoeven, Magnus Damm, Fabrizio Castro, devicetree, linux-renesas-soc, Prabhakar Mahadev Lad, Biju Das Hi Biju, On Mon, Jan 20, 2025 at 09:46:56AM +0000, Biju Das wrote: > The ICU block on the RZ/G3E SoC is almost identical to the one found on > the RZ/V2H SoC, with the following differences: > - The TINT register offset is 0x830 compared to ox30 on RZ/V2H. > - The number of supported GPIO interrupts for TINT selection is 141 > instead of 86. > - The pin index and TINT selection index are not in the 1:1 map > - The number of TSSR registers is 15 instead of 8 > - Each TSSR register can program 2 TINTs instead of 4 TINTs > > Add support for the RZ/G3E ICU driver. > > Biju Das (11): > dt-bindings: interrupt-controller: renesas,rzv2h-icu: Document RZ/G3E > SoC > clk: renesas: r9a09g047: Add ICU clock/reset > irqchip/renesas-rzv2h: Drop irqchip from struct rzv2h_icu_priv > irqchip/renesas-rzv2h: Simplify rzv2h_icu_init() > irqchip/renesas-rzv2h: Add struct rzv2h_hw_info with t_offs variable > irqchip/renesas-rzv2h: Add max_tssel variable to struct rzv2h_hw_info > irqchip/renesas-rzv2h: Add tssr_k variable to struct rzv2h_hw_info > irqchip/renesas-rzv2h: Add tssel_mask and tssel_shift variables to > struct rzv2h_hw_info > irqchip/renesas-rzv2h: Add tien variable to struct rzv2h_hw_info > irqchip/renesas-rzv2h: Add RZ/G3E support > arm64: dts: renesas: r9a09g047: Add icu node > > .../renesas,rzv2h-icu.yaml | 6 +- > arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 108 ++++++++++++ > drivers/clk/renesas/r9a09g047-cpg.c | 3 + > drivers/irqchip/irq-renesas-rzv2h.c | 159 +++++++++++++----- > 4 files changed, 229 insertions(+), 47 deletions(-) > > -- > 2.43.0 For all the series: Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Thanks & Regards, Tommaso ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2025-01-23 22:53 UTC | newest] Thread overview: 7+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-01-20 9:46 [PATCH 00/11] Add Support for RZ/G3E ICU Biju Das 2025-01-20 9:46 ` [PATCH 01/11] dt-bindings: interrupt-controller: renesas,rzv2h-icu: Document RZ/G3E SoC Biju Das 2025-01-23 9:41 ` Fabrizio Castro 2025-01-23 22:53 ` Rob Herring (Arm) 2025-01-20 9:47 ` [PATCH 11/11] arm64: dts: renesas: r9a09g047: Add icu node Biju Das 2025-01-23 9:47 ` Fabrizio Castro 2025-01-21 17:32 ` [PATCH 00/11] Add Support for RZ/G3E ICU Tommaso Merciai
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