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Wed, 22 Jan 2025 05:05:52 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 50M55oUB014124 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 22 Jan 2025 05:05:50 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 21 Jan 2025 21:05:44 -0800 Date: Wed, 22 Jan 2025 10:35:40 +0530 From: Varadarajan Narayanan To: Manivannan Sadhasivam CC: , , , , , , , , , , , , , , , , , , Praveenkumar I , Konrad Dybcio Subject: Re: [PATCH v5 4/5] arm64: dts: qcom: ipq5332: Add PCIe related nodes Message-ID: References: <20250102113019.1347068-1-quic_varada@quicinc.com> <20250102113019.1347068-5-quic_varada@quicinc.com> <20250108132235.gh6p5d6t7wklzpm7@thinkpad> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 0AXiHTq6cbtqOThPNwBcaD_A5SDBYw5C X-Proofpoint-GUID: 0AXiHTq6cbtqOThPNwBcaD_A5SDBYw5C X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-22_01,2025-01-21_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 impostorscore=0 spamscore=0 mlxscore=0 malwarescore=0 mlxlogscore=733 priorityscore=1501 phishscore=0 adultscore=0 suspectscore=0 bulkscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501220035 Manivannan, [ . . . ] > > > + phys = <&pcie1_phy>; > > > + phy-names = "pciephy"; > > > + > > > + interconnects = <&gcc MASTER_SNOC_PCIE3_2_M &gcc SLAVE_SNOC_PCIE3_2_M>, > > > + <&gcc MASTER_ANOC_PCIE3_2_S &gcc SLAVE_ANOC_PCIE3_2_S>; > > > + interconnect-names = "pcie-mem", "cpu-pcie"; > > > > Can you check if the controller supports cache coherency? If so, you need to add > > 'dma-coherent'. > > Ok. Confirmed with h/w person. The controller doesn't support cache coherance. Thanks Varada