* [PATCH 1/9] dt-bindings: powerpc: Add binding for Freescale/NXP MPC83xx SoCs
2025-01-26 18:58 [PATCH 0/9] YAML conversion of several Freescale/PowerPC DT bindings J. Neuschäfer via B4 Relay
@ 2025-01-26 18:58 ` J. Neuschäfer via B4 Relay
2025-01-27 4:23 ` Rob Herring (Arm)
2025-01-26 18:58 ` [PATCH 2/9] dt-bindings: ata: Convert fsl,pq-sata binding to YAML J. Neuschäfer via B4 Relay
` (8 subsequent siblings)
9 siblings, 1 reply; 41+ messages in thread
From: J. Neuschäfer via B4 Relay @ 2025-01-26 18:58 UTC (permalink / raw)
To: devicetree, linuxppc-dev
Cc: Scott Wood, Madhavan Srinivasan, Michael Ellerman,
Nicholas Piggin, Christophe Leroy, Naveen N Rao, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Damien Le Moal, Niklas Cassel,
Herbert Xu, David S. Miller, Lee Jones, Vinod Koul,
Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Bjorn Helgaas, J. Neuschäfer,
Wim Van Sebroeck, Guenter Roeck, Mark Brown, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-kernel, linux-ide,
linux-crypto, dmaengine, linux-pci, linux-watchdog, linux-spi,
linux-mtd, J. Neuschäfer
From: "J. Neuschäfer" <j.ne@posteo.net>
Add a new binding for MPC83xx platforms, describing the board compatible
strings used in currently existing device trees.
Note that the SoC bus is called immr@... in many existing devicetrees,
but this contradicts the simple-bus binding.
Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
---
.../bindings/powerpc/fsl/fsl,mpc83xx.yaml | 67 ++++++++++++++++++++++
1 file changed, 67 insertions(+)
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/fsl,mpc83xx.yaml b/Documentation/devicetree/bindings/powerpc/fsl/fsl,mpc83xx.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..d51c85b505b0dec3a25d50e2bdc980cd2ee04b7c
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/fsl,mpc83xx.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/powerpc/fsl/fsl,mpc83xx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale PowerQUICC II Pro (MPC83xx) platforms
+
+maintainers:
+ - J. Neuschäfer <j.ne@posteo.net>
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+ - description: MPC83xx Reference Design Boards
+ items:
+ - enum:
+ - fsl,mpc8308rdb
+ - fsl,mpc8315erdb
+ - fsl,mpc8360rdk
+ - fsl,mpc8377rdb
+ - fsl,mpc8377wlan
+ - fsl,mpc8378rdb
+ - fsl,mpc8379rdb
+
+patternProperties:
+ "^soc@.*$":
+ type: object
+ properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - fsl,mpc8315-immr
+ - fsl,mpc8308-immr
+ - const: simple-bus
+ - items:
+ - const: fsl,mpc8360-immr
+ - const: fsl,immr
+ - const: fsl,soc
+ - const: simple-bus
+ - const: simple-bus
+
+additionalProperties: true
+
+examples:
+ - |
+ / {
+ compatible = "fsl,mpc8315erdb";
+ model = "MPC8315E-RDB";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ soc@e0000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "fsl,mpc8315-immr", "simple-bus";
+ ranges = <0 0xe0000000 0x00100000>;
+ reg = <0xe0000000 0x00000200>;
+ bus-frequency = <0>;
+ };
+ };
+
+...
--
2.48.0.rc1.219.gb6b6757d772
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [PATCH 1/9] dt-bindings: powerpc: Add binding for Freescale/NXP MPC83xx SoCs
2025-01-26 18:58 ` [PATCH 1/9] dt-bindings: powerpc: Add binding for Freescale/NXP MPC83xx SoCs J. Neuschäfer via B4 Relay
@ 2025-01-27 4:23 ` Rob Herring (Arm)
0 siblings, 0 replies; 41+ messages in thread
From: Rob Herring (Arm) @ 2025-01-27 4:23 UTC (permalink / raw)
To: J. Neuschäfer
Cc: linux-spi, Krzysztof Wilczyński, devicetree, Vinod Koul,
Manivannan Sadhasivam, Miquel Raynal, Scott Wood,
Wim Van Sebroeck, Naveen N Rao, linuxppc-dev, Conor Dooley,
Herbert Xu, Michael Ellerman, linux-crypto, Niklas Cassel,
Richard Weinberger, David S. Miller, linux-ide, linux-kernel,
Guenter Roeck, linux-watchdog, Lee Jones, Lorenzo Pieralisi,
Bjorn Helgaas, J. Neuschäfer, Krzysztof Kozlowski, linux-mtd,
dmaengine, Madhavan Srinivasan, Mark Brown, linux-pci,
Vignesh Raghavendra, Nicholas Piggin, Christophe Leroy,
Damien Le Moal
On Sun, 26 Jan 2025 19:58:56 +0100, J. Neuschäfer wrote:
> Add a new binding for MPC83xx platforms, describing the board compatible
> strings used in currently existing device trees.
>
> Note that the SoC bus is called immr@... in many existing devicetrees,
> but this contradicts the simple-bus binding.
>
> Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
> ---
> .../bindings/powerpc/fsl/fsl,mpc83xx.yaml | 67 ++++++++++++++++++++++
> 1 file changed, 67 insertions(+)
>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH 2/9] dt-bindings: ata: Convert fsl,pq-sata binding to YAML
2025-01-26 18:58 [PATCH 0/9] YAML conversion of several Freescale/PowerPC DT bindings J. Neuschäfer via B4 Relay
2025-01-26 18:58 ` [PATCH 1/9] dt-bindings: powerpc: Add binding for Freescale/NXP MPC83xx SoCs J. Neuschäfer via B4 Relay
@ 2025-01-26 18:58 ` J. Neuschäfer via B4 Relay
2025-01-26 23:22 ` Damien Le Moal
2025-01-27 4:37 ` Rob Herring
2025-01-26 18:58 ` [PATCH 3/9] dt-bindings: crypto: Convert fsl,sec-2.0 " J. Neuschäfer via B4 Relay
` (7 subsequent siblings)
9 siblings, 2 replies; 41+ messages in thread
From: J. Neuschäfer via B4 Relay @ 2025-01-26 18:58 UTC (permalink / raw)
To: devicetree, linuxppc-dev
Cc: Scott Wood, Madhavan Srinivasan, Michael Ellerman,
Nicholas Piggin, Christophe Leroy, Naveen N Rao, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Damien Le Moal, Niklas Cassel,
Herbert Xu, David S. Miller, Lee Jones, Vinod Koul,
Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Bjorn Helgaas, J. Neuschäfer,
Wim Van Sebroeck, Guenter Roeck, Mark Brown, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-kernel, linux-ide,
linux-crypto, dmaengine, linux-pci, linux-watchdog, linux-spi,
linux-mtd, J. Neuschäfer
From: "J. Neuschäfer" <j.ne@posteo.net>
Convert the Freescale PowerQUICC SATA controller binding from text form
to YAML. The list of compatible strings reflects current usage.
Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
---
.../devicetree/bindings/ata/fsl,pq-sata.yaml | 59 ++++++++++++++++++++++
Documentation/devicetree/bindings/ata/fsl-sata.txt | 28 ----------
2 files changed, 59 insertions(+), 28 deletions(-)
diff --git a/Documentation/devicetree/bindings/ata/fsl,pq-sata.yaml b/Documentation/devicetree/bindings/ata/fsl,pq-sata.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..6af31ffbcad5e9cc83118a0bd8eaf45351a2823f
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/fsl,pq-sata.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ata/fsl,pq-sata.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale 8xxx/3.0 Gb/s SATA nodes
+
+maintainers:
+ - J. Neuschäfer <j.ne@posteo.net>
+
+description: |
+ SATA nodes are defined to describe on-chip Serial ATA controllers.
+ Each SATA port should have its own node.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - fsl,mpc8377-sata
+ - fsl,mpc8536-sata
+ - fsl,mpc8315-sata
+ - fsl,mpc8379-sata
+ - const: fsl,pq-sata
+ - const: fsl,pq-sata-v2
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ cell-index:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [1, 2, 3, 4]
+ description: |
+ 1 for controller @ 0x18000
+ 2 for controller @ 0x19000
+ 3 for controller @ 0x1a000
+ 4 for controller @ 0x1b000
+
+required:
+ - compatible
+ - interrupts
+ - cell-index
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ sata@18000 {
+ compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
+ reg = <0x18000 0x1000>;
+ cell-index = <1>;
+ interrupts = <44 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&ipic>;
+ };
diff --git a/Documentation/devicetree/bindings/ata/fsl-sata.txt b/Documentation/devicetree/bindings/ata/fsl-sata.txt
deleted file mode 100644
index fd63bb3becc9363c520a8fd06629fdc52c4d4299..0000000000000000000000000000000000000000
--- a/Documentation/devicetree/bindings/ata/fsl-sata.txt
+++ /dev/null
@@ -1,28 +0,0 @@
-* Freescale 8xxx/3.0 Gb/s SATA nodes
-
-SATA nodes are defined to describe on-chip Serial ATA controllers.
-Each SATA port should have its own node.
-
-Required properties:
-- compatible : compatible list, contains 2 entries, first is
- "fsl,CHIP-sata", where CHIP is the processor
- (mpc8315, mpc8379, etc.) and the second is
- "fsl,pq-sata"
-- interrupts : <interrupt mapping for SATA IRQ>
-- cell-index : controller index.
- 1 for controller @ 0x18000
- 2 for controller @ 0x19000
- 3 for controller @ 0x1a000
- 4 for controller @ 0x1b000
-
-Optional properties:
-- reg : <registers mapping>
-
-Example:
- sata@18000 {
- compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
- reg = <0x18000 0x1000>;
- cell-index = <1>;
- interrupts = <2c 8>;
- interrupt-parent = < &ipic >;
- };
--
2.48.0.rc1.219.gb6b6757d772
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [PATCH 2/9] dt-bindings: ata: Convert fsl,pq-sata binding to YAML
2025-01-26 18:58 ` [PATCH 2/9] dt-bindings: ata: Convert fsl,pq-sata binding to YAML J. Neuschäfer via B4 Relay
@ 2025-01-26 23:22 ` Damien Le Moal
2025-01-31 12:23 ` J. Neuschäfer
2025-01-27 4:37 ` Rob Herring
1 sibling, 1 reply; 41+ messages in thread
From: Damien Le Moal @ 2025-01-26 23:22 UTC (permalink / raw)
To: j.ne, devicetree, linuxppc-dev
Cc: Scott Wood, Madhavan Srinivasan, Michael Ellerman,
Nicholas Piggin, Christophe Leroy, Naveen N Rao, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Niklas Cassel, Herbert Xu,
David S. Miller, Lee Jones, Vinod Koul, Lorenzo Pieralisi,
Krzysztof Wilczyński, Manivannan Sadhasivam, Bjorn Helgaas,
J. Neuschäfer, Wim Van Sebroeck, Guenter Roeck, Mark Brown,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-kernel, linux-ide, linux-crypto, dmaengine, linux-pci,
linux-watchdog, linux-spi, linux-mtd
On 1/27/25 03:58, J. Neuschäfer via B4 Relay wrote:
> From: "J. Neuschäfer" <j.ne@posteo.net>
>
> Convert the Freescale PowerQUICC SATA controller binding from text form
> to YAML. The list of compatible strings reflects current usage.
>
> Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
> ---
> .../devicetree/bindings/ata/fsl,pq-sata.yaml | 59 ++++++++++++++++++++++
> Documentation/devicetree/bindings/ata/fsl-sata.txt | 28 ----------
> 2 files changed, 59 insertions(+), 28 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/ata/fsl,pq-sata.yaml b/Documentation/devicetree/bindings/ata/fsl,pq-sata.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..6af31ffbcad5e9cc83118a0bd8eaf45351a2823f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/ata/fsl,pq-sata.yaml
> @@ -0,0 +1,59 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/ata/fsl,pq-sata.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale 8xxx/3.0 Gb/s SATA nodes
> +
> +maintainers:
> + - J. Neuschäfer <j.ne@posteo.net>
> +
> +description: |
> + SATA nodes are defined to describe on-chip Serial ATA controllers.
> + Each SATA port should have its own node.
Very unclear. The SATA nodes define ports or controllers ? Normally, a single
controller can have multiple ports, so the distinction is important.
> +
> +properties:
> + compatible:
> + oneOf:
> + - items:
> + - enum:
> + - fsl,mpc8377-sata
> + - fsl,mpc8536-sata
> + - fsl,mpc8315-sata
> + - fsl,mpc8379-sata
> + - const: fsl,pq-sata
> + - const: fsl,pq-sata-v2
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + cell-index:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [1, 2, 3, 4]
> + description: |
> + 1 for controller @ 0x18000
> + 2 for controller @ 0x19000
> + 3 for controller @ 0x1a000
> + 4 for controller @ 0x1b000
Are you sure these are different controllers ? Are they not different ports of
the same controller ? Given that the previous text description define this as
"controller index", I suspect these are the port offsets and you SATA nodes
define ports, and not controllers.
> +
> +required:
> + - compatible
> + - interrupts
> + - cell-index
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/irq.h>
> + sata@18000 {
> + compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
> + reg = <0x18000 0x1000>;
> + cell-index = <1>;
> + interrupts = <44 IRQ_TYPE_LEVEL_LOW>;
> + interrupt-parent = <&ipic>;
> + };
> diff --git a/Documentation/devicetree/bindings/ata/fsl-sata.txt b/Documentation/devicetree/bindings/ata/fsl-sata.txt
> deleted file mode 100644
> index fd63bb3becc9363c520a8fd06629fdc52c4d4299..0000000000000000000000000000000000000000
> --- a/Documentation/devicetree/bindings/ata/fsl-sata.txt
> +++ /dev/null
> @@ -1,28 +0,0 @@
> -* Freescale 8xxx/3.0 Gb/s SATA nodes
> -
> -SATA nodes are defined to describe on-chip Serial ATA controllers.
> -Each SATA port should have its own node.
> -
> -Required properties:
> -- compatible : compatible list, contains 2 entries, first is
> - "fsl,CHIP-sata", where CHIP is the processor
> - (mpc8315, mpc8379, etc.) and the second is
> - "fsl,pq-sata"
> -- interrupts : <interrupt mapping for SATA IRQ>
> -- cell-index : controller index.
> - 1 for controller @ 0x18000
> - 2 for controller @ 0x19000
> - 3 for controller @ 0x1a000
> - 4 for controller @ 0x1b000
> -
> -Optional properties:
> -- reg : <registers mapping>
> -
> -Example:
> - sata@18000 {
> - compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
> - reg = <0x18000 0x1000>;
> - cell-index = <1>;
> - interrupts = <2c 8>;
> - interrupt-parent = < &ipic >;
> - };
>
--
Damien Le Moal
Western Digital Research
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH 2/9] dt-bindings: ata: Convert fsl,pq-sata binding to YAML
2025-01-26 23:22 ` Damien Le Moal
@ 2025-01-31 12:23 ` J. Neuschäfer
0 siblings, 0 replies; 41+ messages in thread
From: J. Neuschäfer @ 2025-01-31 12:23 UTC (permalink / raw)
To: Damien Le Moal
Cc: j.ne, devicetree, linuxppc-dev, Scott Wood, Madhavan Srinivasan,
Michael Ellerman, Nicholas Piggin, Christophe Leroy, Naveen N Rao,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Niklas Cassel,
Herbert Xu, David S. Miller, Lee Jones, Vinod Koul,
Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Bjorn Helgaas, J. Neuschäfer,
Wim Van Sebroeck, Guenter Roeck, Mark Brown, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-kernel, linux-ide,
linux-crypto, dmaengine, linux-pci, linux-watchdog, linux-spi,
linux-mtd
On Mon, Jan 27, 2025 at 08:22:55AM +0900, Damien Le Moal wrote:
> On 1/27/25 03:58, J. Neuschäfer via B4 Relay wrote:
> > From: "J. Neuschäfer" <j.ne@posteo.net>
> >
> > Convert the Freescale PowerQUICC SATA controller binding from text form
> > to YAML. The list of compatible strings reflects current usage.
> >
> > Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
> > ---
> > .../devicetree/bindings/ata/fsl,pq-sata.yaml | 59 ++++++++++++++++++++++
[...]
> > +description: |
> > + SATA nodes are defined to describe on-chip Serial ATA controllers.
> > + Each SATA port should have its own node.
>
> Very unclear. The SATA nodes define ports or controllers ? Normally, a single
> controller can have multiple ports, so the distinction is important.
I'll change it to "Each SATA controller ...", see below.
> > + cell-index:
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + enum: [1, 2, 3, 4]
> > + description: |
> > + 1 for controller @ 0x18000
> > + 2 for controller @ 0x19000
> > + 3 for controller @ 0x1a000
> > + 4 for controller @ 0x1b000
>
> Are you sure these are different controllers ? Are they not different ports of
> the same controller ? Given that the previous text description define this as
> "controller index", I suspect these are the port offsets and you SATA nodes
> define ports, and not controllers.
They have no shared registers, and each instance has the same register
set (at a different base address).
The MPC8315E reference manual (for example) documents them as:
SATA 1 Controller—Block Base Address 0x1_8000
SATA 2 Controller—Block Base Address 0x1_9000
(table A.24 Serial ATA (SATA) Controller)
Section 15.2 Command Operation implies that each SATA controller
supports a single port:
The SATA controller maintains a queue consisting of up to 16
commands. These commands can be distributed to a single attached
device or, if the system contains a port multiplier, over each
of the attached devices.
So, in conclusion, I'm fairly sure "controller" is the right description.
Best regards,
J. Neuschäfer
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 2/9] dt-bindings: ata: Convert fsl,pq-sata binding to YAML
2025-01-26 18:58 ` [PATCH 2/9] dt-bindings: ata: Convert fsl,pq-sata binding to YAML J. Neuschäfer via B4 Relay
2025-01-26 23:22 ` Damien Le Moal
@ 2025-01-27 4:37 ` Rob Herring
1 sibling, 0 replies; 41+ messages in thread
From: Rob Herring @ 2025-01-27 4:37 UTC (permalink / raw)
To: J. Neuschäfer
Cc: devicetree, linuxppc-dev, Scott Wood, Madhavan Srinivasan,
Michael Ellerman, Nicholas Piggin, Christophe Leroy, Naveen N Rao,
Krzysztof Kozlowski, Conor Dooley, Damien Le Moal, Niklas Cassel,
Herbert Xu, David S. Miller, Lee Jones, Vinod Koul,
Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Bjorn Helgaas, J. Neuschäfer,
Wim Van Sebroeck, Guenter Roeck, Mark Brown, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-kernel, linux-ide,
linux-crypto, dmaengine, linux-pci, linux-watchdog, linux-spi,
linux-mtd
On Sun, Jan 26, 2025 at 07:58:57PM +0100, J. Neuschäfer wrote:
> Convert the Freescale PowerQUICC SATA controller binding from text form
> to YAML. The list of compatible strings reflects current usage.
>
> Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
> ---
> .../devicetree/bindings/ata/fsl,pq-sata.yaml | 59 ++++++++++++++++++++++
> Documentation/devicetree/bindings/ata/fsl-sata.txt | 28 ----------
> 2 files changed, 59 insertions(+), 28 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/ata/fsl,pq-sata.yaml b/Documentation/devicetree/bindings/ata/fsl,pq-sata.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..6af31ffbcad5e9cc83118a0bd8eaf45351a2823f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/ata/fsl,pq-sata.yaml
> @@ -0,0 +1,59 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/ata/fsl,pq-sata.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale 8xxx/3.0 Gb/s SATA nodes
> +
> +maintainers:
> + - J. Neuschäfer <j.ne@posteo.net>
> +
> +description: |
Don't need '|'
Otherwise,
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
> + SATA nodes are defined to describe on-chip Serial ATA controllers.
> + Each SATA port should have its own node.
> +
> +properties:
> + compatible:
> + oneOf:
> + - items:
> + - enum:
> + - fsl,mpc8377-sata
> + - fsl,mpc8536-sata
> + - fsl,mpc8315-sata
> + - fsl,mpc8379-sata
> + - const: fsl,pq-sata
> + - const: fsl,pq-sata-v2
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + cell-index:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [1, 2, 3, 4]
> + description: |
> + 1 for controller @ 0x18000
> + 2 for controller @ 0x19000
> + 3 for controller @ 0x1a000
> + 4 for controller @ 0x1b000
> +
> +required:
> + - compatible
> + - interrupts
> + - cell-index
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/irq.h>
> + sata@18000 {
> + compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
> + reg = <0x18000 0x1000>;
> + cell-index = <1>;
> + interrupts = <44 IRQ_TYPE_LEVEL_LOW>;
> + interrupt-parent = <&ipic>;
> + };
> diff --git a/Documentation/devicetree/bindings/ata/fsl-sata.txt b/Documentation/devicetree/bindings/ata/fsl-sata.txt
> deleted file mode 100644
> index fd63bb3becc9363c520a8fd06629fdc52c4d4299..0000000000000000000000000000000000000000
> --- a/Documentation/devicetree/bindings/ata/fsl-sata.txt
> +++ /dev/null
> @@ -1,28 +0,0 @@
> -* Freescale 8xxx/3.0 Gb/s SATA nodes
> -
> -SATA nodes are defined to describe on-chip Serial ATA controllers.
> -Each SATA port should have its own node.
> -
> -Required properties:
> -- compatible : compatible list, contains 2 entries, first is
> - "fsl,CHIP-sata", where CHIP is the processor
> - (mpc8315, mpc8379, etc.) and the second is
> - "fsl,pq-sata"
> -- interrupts : <interrupt mapping for SATA IRQ>
> -- cell-index : controller index.
> - 1 for controller @ 0x18000
> - 2 for controller @ 0x19000
> - 3 for controller @ 0x1a000
> - 4 for controller @ 0x1b000
> -
> -Optional properties:
> -- reg : <registers mapping>
> -
> -Example:
> - sata@18000 {
> - compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
> - reg = <0x18000 0x1000>;
> - cell-index = <1>;
> - interrupts = <2c 8>;
> - interrupt-parent = < &ipic >;
> - };
>
> --
> 2.48.0.rc1.219.gb6b6757d772
>
^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH 3/9] dt-bindings: crypto: Convert fsl,sec-2.0 binding to YAML
2025-01-26 18:58 [PATCH 0/9] YAML conversion of several Freescale/PowerPC DT bindings J. Neuschäfer via B4 Relay
2025-01-26 18:58 ` [PATCH 1/9] dt-bindings: powerpc: Add binding for Freescale/NXP MPC83xx SoCs J. Neuschäfer via B4 Relay
2025-01-26 18:58 ` [PATCH 2/9] dt-bindings: ata: Convert fsl,pq-sata binding to YAML J. Neuschäfer via B4 Relay
@ 2025-01-26 18:58 ` J. Neuschäfer via B4 Relay
2025-01-27 4:41 ` Rob Herring
2025-01-26 18:58 ` [PATCH 4/9] dt-bindings: mfd: Convert fsl,mcu-mpc8349emitx " J. Neuschäfer via B4 Relay
` (6 subsequent siblings)
9 siblings, 1 reply; 41+ messages in thread
From: J. Neuschäfer via B4 Relay @ 2025-01-26 18:58 UTC (permalink / raw)
To: devicetree, linuxppc-dev
Cc: Scott Wood, Madhavan Srinivasan, Michael Ellerman,
Nicholas Piggin, Christophe Leroy, Naveen N Rao, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Damien Le Moal, Niklas Cassel,
Herbert Xu, David S. Miller, Lee Jones, Vinod Koul,
Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Bjorn Helgaas, J. Neuschäfer,
Wim Van Sebroeck, Guenter Roeck, Mark Brown, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-kernel, linux-ide,
linux-crypto, dmaengine, linux-pci, linux-watchdog, linux-spi,
linux-mtd, J. Neuschäfer
From: "J. Neuschäfer" <j.ne@posteo.net>
Convert the Freescale security engine (crypto accelerator) binding from
text form to YAML. The list of compatible strings reflects what was
previously described in prose; not all combinations occur in existing
devicetrees.
Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
---
.../devicetree/bindings/crypto/fsl,sec2.0.yaml | 139 +++++++++++++++++++++
.../devicetree/bindings/crypto/fsl-sec2.txt | 65 ----------
2 files changed, 139 insertions(+), 65 deletions(-)
diff --git a/Documentation/devicetree/bindings/crypto/fsl,sec2.0.yaml b/Documentation/devicetree/bindings/crypto/fsl,sec2.0.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..5ae593e60987e175413c3a082c9466f09f642bc4
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/fsl,sec2.0.yaml
@@ -0,0 +1,139 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/crypto/fsl,sec2.0.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale SoC SEC Security Engines versions 1.x-2.x-3.x
+
+maintainers:
+ - J. Neuschäfer <j.ne@posteo.net.
+
+properties:
+ compatible:
+ description: |
+ Should contain entries for this and backward compatible SEC versions,
+ high to low. Warning: SEC1 and SEC2 are mutually exclusive.
+ oneOf:
+ - items:
+ - const: fsl,sec3.3
+ - const: fsl,sec3.1
+ - const: fsl,sec3.0
+ - const: fsl,sec2.4
+ - const: fsl,sec2.2
+ - const: fsl,sec2.1
+ - const: fsl,sec2.0
+ - items:
+ - const: fsl,sec3.1
+ - const: fsl,sec3.0
+ - const: fsl,sec2.4
+ - const: fsl,sec2.2
+ - const: fsl,sec2.1
+ - const: fsl,sec2.0
+ - items:
+ - const: fsl,sec3.0
+ - const: fsl,sec2.4
+ - const: fsl,sec2.2
+ - const: fsl,sec2.1
+ - const: fsl,sec2.0
+ - items:
+ - const: fsl,sec2.4
+ - const: fsl,sec2.2
+ - const: fsl,sec2.1
+ - const: fsl,sec2.0
+ - items:
+ - const: fsl,sec2.2
+ - const: fsl,sec2.1
+ - const: fsl,sec2.0
+ - items:
+ - const: fsl,sec2.1
+ - const: fsl,sec2.0
+ - items:
+ - const: fsl,sec2.0
+ - items:
+ - const: fsl,sec1.2
+ - const: fsl,sec1.0
+ - items:
+ - const: fsl,sec1.0
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ fsl,num-channels:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: An integer representing the number of channels available.
+
+ fsl,channel-fifo-len:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ An integer representing the number of descriptor pointers each channel
+ fetch fifo can hold.
+
+ fsl,exec-units-mask:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ The bitmask representing what execution units (EUs) are available.
+ EU information should be encoded following the SEC's Descriptor Header
+ Dword EU_SEL0 field documentation, i.e. as follows:
+
+ bit 0 = reserved - should be 0
+ bit 1 = set if SEC has the ARC4 EU (AFEU)
+ bit 2 = set if SEC has the DES/3DES EU (DEU)
+ bit 3 = set if SEC has the message digest EU (MDEU/MDEU-A)
+ bit 4 = set if SEC has the random number generator EU (RNG)
+ bit 5 = set if SEC has the public key EU (PKEU)
+ bit 6 = set if SEC has the AES EU (AESU)
+ bit 7 = set if SEC has the Kasumi EU (KEU)
+ bit 8 = set if SEC has the CRC EU (CRCU)
+ bit 11 = set if SEC has the message digest EU extended alg set (MDEU-B)
+
+ remaining bits are reserved for future SEC EUs.
+
+ fsl,descriptor-types-mask:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ The bitmask representing what descriptors are available. Descriptor type
+ information should be encoded following the SEC's Descriptor Header Dword
+ DESC_TYPE field documentation, i.e. as follows:
+
+ bit 0 = set if SEC supports the aesu_ctr_nonsnoop desc. type
+ bit 1 = set if SEC supports the ipsec_esp descriptor type
+ bit 2 = set if SEC supports the common_nonsnoop desc. type
+ bit 3 = set if SEC supports the 802.11i AES ccmp desc. type
+ bit 4 = set if SEC supports the hmac_snoop_no_afeu desc. type
+ bit 5 = set if SEC supports the srtp descriptor type
+ bit 6 = set if SEC supports the non_hmac_snoop_no_afeu desc.type
+ bit 7 = set if SEC supports the pkeu_assemble descriptor type
+ bit 8 = set if SEC supports the aesu_key_expand_output desc.type
+ bit 9 = set if SEC supports the pkeu_ptmul descriptor type
+ bit 10 = set if SEC supports the common_nonsnoop_afeu desc. type
+ bit 11 = set if SEC supports the pkeu_ptadd_dbl descriptor type
+
+ ..and so on and so forth.
+
+required:
+ - compatible
+ - reg
+ - fsl,num-channels
+ - fsl,channel-fifo-len
+ - fsl,exec-units-mask
+ - fsl,descriptor-types-mask
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ /* MPC8548E */
+ crypto@30000 {
+ compatible = "fsl,sec2.1", "fsl,sec2.0";
+ reg = <0x30000 0x10000>;
+ interrupts = <29 2>;
+ interrupt-parent = <&mpic>;
+ fsl,num-channels = <4>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0xfe>;
+ fsl,descriptor-types-mask = <0x12b0ebf>;
+ };
diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec2.txt b/Documentation/devicetree/bindings/crypto/fsl-sec2.txt
deleted file mode 100644
index 125f155d00d052eec7d5093b5c5076cbe720417f..0000000000000000000000000000000000000000
--- a/Documentation/devicetree/bindings/crypto/fsl-sec2.txt
+++ /dev/null
@@ -1,65 +0,0 @@
-Freescale SoC SEC Security Engines versions 1.x-2.x-3.x
-
-Required properties:
-
-- compatible : Should contain entries for this and backward compatible
- SEC versions, high to low, e.g., "fsl,sec2.1", "fsl,sec2.0" (SEC2/3)
- e.g., "fsl,sec1.2", "fsl,sec1.0" (SEC1)
- warning: SEC1 and SEC2 are mutually exclusive
-- reg : Offset and length of the register set for the device
-- interrupts : the SEC's interrupt number
-- fsl,num-channels : An integer representing the number of channels
- available.
-- fsl,channel-fifo-len : An integer representing the number of
- descriptor pointers each channel fetch fifo can hold.
-- fsl,exec-units-mask : The bitmask representing what execution units
- (EUs) are available. It's a single 32-bit cell. EU information
- should be encoded following the SEC's Descriptor Header Dword
- EU_SEL0 field documentation, i.e. as follows:
-
- bit 0 = reserved - should be 0
- bit 1 = set if SEC has the ARC4 EU (AFEU)
- bit 2 = set if SEC has the DES/3DES EU (DEU)
- bit 3 = set if SEC has the message digest EU (MDEU/MDEU-A)
- bit 4 = set if SEC has the random number generator EU (RNG)
- bit 5 = set if SEC has the public key EU (PKEU)
- bit 6 = set if SEC has the AES EU (AESU)
- bit 7 = set if SEC has the Kasumi EU (KEU)
- bit 8 = set if SEC has the CRC EU (CRCU)
- bit 11 = set if SEC has the message digest EU extended alg set (MDEU-B)
-
-remaining bits are reserved for future SEC EUs.
-
-- fsl,descriptor-types-mask : The bitmask representing what descriptors
- are available. It's a single 32-bit cell. Descriptor type information
- should be encoded following the SEC's Descriptor Header Dword DESC_TYPE
- field documentation, i.e. as follows:
-
- bit 0 = set if SEC supports the aesu_ctr_nonsnoop desc. type
- bit 1 = set if SEC supports the ipsec_esp descriptor type
- bit 2 = set if SEC supports the common_nonsnoop desc. type
- bit 3 = set if SEC supports the 802.11i AES ccmp desc. type
- bit 4 = set if SEC supports the hmac_snoop_no_afeu desc. type
- bit 5 = set if SEC supports the srtp descriptor type
- bit 6 = set if SEC supports the non_hmac_snoop_no_afeu desc.type
- bit 7 = set if SEC supports the pkeu_assemble descriptor type
- bit 8 = set if SEC supports the aesu_key_expand_output desc.type
- bit 9 = set if SEC supports the pkeu_ptmul descriptor type
- bit 10 = set if SEC supports the common_nonsnoop_afeu desc. type
- bit 11 = set if SEC supports the pkeu_ptadd_dbl descriptor type
-
- ..and so on and so forth.
-
-Example:
-
- /* MPC8548E */
- crypto@30000 {
- compatible = "fsl,sec2.1", "fsl,sec2.0";
- reg = <0x30000 0x10000>;
- interrupts = <29 2>;
- interrupt-parent = <&mpic>;
- fsl,num-channels = <4>;
- fsl,channel-fifo-len = <24>;
- fsl,exec-units-mask = <0xfe>;
- fsl,descriptor-types-mask = <0x12b0ebf>;
- };
--
2.48.0.rc1.219.gb6b6757d772
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [PATCH 3/9] dt-bindings: crypto: Convert fsl,sec-2.0 binding to YAML
2025-01-26 18:58 ` [PATCH 3/9] dt-bindings: crypto: Convert fsl,sec-2.0 " J. Neuschäfer via B4 Relay
@ 2025-01-27 4:41 ` Rob Herring
2025-01-29 15:41 ` J. Neuschäfer
0 siblings, 1 reply; 41+ messages in thread
From: Rob Herring @ 2025-01-27 4:41 UTC (permalink / raw)
To: J. Neuschäfer
Cc: devicetree, linuxppc-dev, Scott Wood, Madhavan Srinivasan,
Michael Ellerman, Nicholas Piggin, Christophe Leroy, Naveen N Rao,
Krzysztof Kozlowski, Conor Dooley, Damien Le Moal, Niklas Cassel,
Herbert Xu, David S. Miller, Lee Jones, Vinod Koul,
Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Bjorn Helgaas, J. Neuschäfer,
Wim Van Sebroeck, Guenter Roeck, Mark Brown, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-kernel, linux-ide,
linux-crypto, dmaengine, linux-pci, linux-watchdog, linux-spi,
linux-mtd
On Sun, Jan 26, 2025 at 07:58:58PM +0100, J. Neuschäfer wrote:
> Convert the Freescale security engine (crypto accelerator) binding from
> text form to YAML. The list of compatible strings reflects what was
> previously described in prose; not all combinations occur in existing
> devicetrees.
>
> Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
> ---
> .../devicetree/bindings/crypto/fsl,sec2.0.yaml | 139 +++++++++++++++++++++
> .../devicetree/bindings/crypto/fsl-sec2.txt | 65 ----------
> 2 files changed, 139 insertions(+), 65 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/crypto/fsl,sec2.0.yaml b/Documentation/devicetree/bindings/crypto/fsl,sec2.0.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..5ae593e60987e175413c3a082c9466f09f642bc4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/crypto/fsl,sec2.0.yaml
> @@ -0,0 +1,139 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/crypto/fsl,sec2.0.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale SoC SEC Security Engines versions 1.x-2.x-3.x
> +
> +maintainers:
> + - J. Neuschäfer <j.ne@posteo.net.
> +
> +properties:
> + compatible:
> + description: |
Don't need '|'. I imagine there are more in the series, but will let you
find the rest.
> + Should contain entries for this and backward compatible SEC versions,
> + high to low. Warning: SEC1 and SEC2 are mutually exclusive.
> + oneOf:
> + - items:
> + - const: fsl,sec3.3
> + - const: fsl,sec3.1
> + - const: fsl,sec3.0
> + - const: fsl,sec2.4
> + - const: fsl,sec2.2
> + - const: fsl,sec2.1
> + - const: fsl,sec2.0
> + - items:
> + - const: fsl,sec3.1
> + - const: fsl,sec3.0
> + - const: fsl,sec2.4
> + - const: fsl,sec2.2
> + - const: fsl,sec2.1
> + - const: fsl,sec2.0
> + - items:
> + - const: fsl,sec3.0
> + - const: fsl,sec2.4
> + - const: fsl,sec2.2
> + - const: fsl,sec2.1
> + - const: fsl,sec2.0
> + - items:
> + - const: fsl,sec2.4
> + - const: fsl,sec2.2
> + - const: fsl,sec2.1
> + - const: fsl,sec2.0
> + - items:
> + - const: fsl,sec2.2
> + - const: fsl,sec2.1
> + - const: fsl,sec2.0
> + - items:
> + - const: fsl,sec2.1
> + - const: fsl,sec2.0
> + - items:
> + - const: fsl,sec2.0
> + - items:
> + - const: fsl,sec1.2
> + - const: fsl,sec1.0
> + - items:
> + - const: fsl,sec1.0
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + fsl,num-channels:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: An integer representing the number of channels available.
minimum: 1
maximum: ?
> +
> + fsl,channel-fifo-len:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: |
> + An integer representing the number of descriptor pointers each channel
> + fetch fifo can hold.
Constraints?
> +
> + fsl,exec-units-mask:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: |
> + The bitmask representing what execution units (EUs) are available.
> + EU information should be encoded following the SEC's Descriptor Header
> + Dword EU_SEL0 field documentation, i.e. as follows:
> +
> + bit 0 = reserved - should be 0
> + bit 1 = set if SEC has the ARC4 EU (AFEU)
> + bit 2 = set if SEC has the DES/3DES EU (DEU)
> + bit 3 = set if SEC has the message digest EU (MDEU/MDEU-A)
> + bit 4 = set if SEC has the random number generator EU (RNG)
> + bit 5 = set if SEC has the public key EU (PKEU)
> + bit 6 = set if SEC has the AES EU (AESU)
> + bit 7 = set if SEC has the Kasumi EU (KEU)
> + bit 8 = set if SEC has the CRC EU (CRCU)
> + bit 11 = set if SEC has the message digest EU extended alg set (MDEU-B)
> +
> + remaining bits are reserved for future SEC EUs.
So:
maximum: 0xfff
> +
> + fsl,descriptor-types-mask:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: |
> + The bitmask representing what descriptors are available. Descriptor type
> + information should be encoded following the SEC's Descriptor Header Dword
> + DESC_TYPE field documentation, i.e. as follows:
> +
> + bit 0 = set if SEC supports the aesu_ctr_nonsnoop desc. type
> + bit 1 = set if SEC supports the ipsec_esp descriptor type
> + bit 2 = set if SEC supports the common_nonsnoop desc. type
> + bit 3 = set if SEC supports the 802.11i AES ccmp desc. type
> + bit 4 = set if SEC supports the hmac_snoop_no_afeu desc. type
> + bit 5 = set if SEC supports the srtp descriptor type
> + bit 6 = set if SEC supports the non_hmac_snoop_no_afeu desc.type
> + bit 7 = set if SEC supports the pkeu_assemble descriptor type
> + bit 8 = set if SEC supports the aesu_key_expand_output desc.type
> + bit 9 = set if SEC supports the pkeu_ptmul descriptor type
> + bit 10 = set if SEC supports the common_nonsnoop_afeu desc. type
> + bit 11 = set if SEC supports the pkeu_ptadd_dbl descriptor type
> +
> + ..and so on and so forth.
> +
> +required:
> + - compatible
> + - reg
> + - fsl,num-channels
> + - fsl,channel-fifo-len
> + - fsl,exec-units-mask
> + - fsl,descriptor-types-mask
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + /* MPC8548E */
> + crypto@30000 {
> + compatible = "fsl,sec2.1", "fsl,sec2.0";
> + reg = <0x30000 0x10000>;
> + interrupts = <29 2>;
> + interrupt-parent = <&mpic>;
> + fsl,num-channels = <4>;
> + fsl,channel-fifo-len = <24>;
> + fsl,exec-units-mask = <0xfe>;
> + fsl,descriptor-types-mask = <0x12b0ebf>;
> + };
> diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec2.txt b/Documentation/devicetree/bindings/crypto/fsl-sec2.txt
> deleted file mode 100644
> index 125f155d00d052eec7d5093b5c5076cbe720417f..0000000000000000000000000000000000000000
> --- a/Documentation/devicetree/bindings/crypto/fsl-sec2.txt
> +++ /dev/null
> @@ -1,65 +0,0 @@
> -Freescale SoC SEC Security Engines versions 1.x-2.x-3.x
> -
> -Required properties:
> -
> -- compatible : Should contain entries for this and backward compatible
> - SEC versions, high to low, e.g., "fsl,sec2.1", "fsl,sec2.0" (SEC2/3)
> - e.g., "fsl,sec1.2", "fsl,sec1.0" (SEC1)
> - warning: SEC1 and SEC2 are mutually exclusive
> -- reg : Offset and length of the register set for the device
> -- interrupts : the SEC's interrupt number
> -- fsl,num-channels : An integer representing the number of channels
> - available.
> -- fsl,channel-fifo-len : An integer representing the number of
> - descriptor pointers each channel fetch fifo can hold.
> -- fsl,exec-units-mask : The bitmask representing what execution units
> - (EUs) are available. It's a single 32-bit cell. EU information
> - should be encoded following the SEC's Descriptor Header Dword
> - EU_SEL0 field documentation, i.e. as follows:
> -
> - bit 0 = reserved - should be 0
> - bit 1 = set if SEC has the ARC4 EU (AFEU)
> - bit 2 = set if SEC has the DES/3DES EU (DEU)
> - bit 3 = set if SEC has the message digest EU (MDEU/MDEU-A)
> - bit 4 = set if SEC has the random number generator EU (RNG)
> - bit 5 = set if SEC has the public key EU (PKEU)
> - bit 6 = set if SEC has the AES EU (AESU)
> - bit 7 = set if SEC has the Kasumi EU (KEU)
> - bit 8 = set if SEC has the CRC EU (CRCU)
> - bit 11 = set if SEC has the message digest EU extended alg set (MDEU-B)
> -
> -remaining bits are reserved for future SEC EUs.
> -
> -- fsl,descriptor-types-mask : The bitmask representing what descriptors
> - are available. It's a single 32-bit cell. Descriptor type information
> - should be encoded following the SEC's Descriptor Header Dword DESC_TYPE
> - field documentation, i.e. as follows:
> -
> - bit 0 = set if SEC supports the aesu_ctr_nonsnoop desc. type
> - bit 1 = set if SEC supports the ipsec_esp descriptor type
> - bit 2 = set if SEC supports the common_nonsnoop desc. type
> - bit 3 = set if SEC supports the 802.11i AES ccmp desc. type
> - bit 4 = set if SEC supports the hmac_snoop_no_afeu desc. type
> - bit 5 = set if SEC supports the srtp descriptor type
> - bit 6 = set if SEC supports the non_hmac_snoop_no_afeu desc.type
> - bit 7 = set if SEC supports the pkeu_assemble descriptor type
> - bit 8 = set if SEC supports the aesu_key_expand_output desc.type
> - bit 9 = set if SEC supports the pkeu_ptmul descriptor type
> - bit 10 = set if SEC supports the common_nonsnoop_afeu desc. type
> - bit 11 = set if SEC supports the pkeu_ptadd_dbl descriptor type
> -
> - ..and so on and so forth.
> -
> -Example:
> -
> - /* MPC8548E */
> - crypto@30000 {
> - compatible = "fsl,sec2.1", "fsl,sec2.0";
> - reg = <0x30000 0x10000>;
> - interrupts = <29 2>;
> - interrupt-parent = <&mpic>;
> - fsl,num-channels = <4>;
> - fsl,channel-fifo-len = <24>;
> - fsl,exec-units-mask = <0xfe>;
> - fsl,descriptor-types-mask = <0x12b0ebf>;
> - };
>
> --
> 2.48.0.rc1.219.gb6b6757d772
>
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH 3/9] dt-bindings: crypto: Convert fsl,sec-2.0 binding to YAML
2025-01-27 4:41 ` Rob Herring
@ 2025-01-29 15:41 ` J. Neuschäfer
0 siblings, 0 replies; 41+ messages in thread
From: J. Neuschäfer @ 2025-01-29 15:41 UTC (permalink / raw)
To: Rob Herring
Cc: J. Neuschäfer, devicetree, linuxppc-dev, Scott Wood,
Madhavan Srinivasan, Michael Ellerman, Nicholas Piggin,
Christophe Leroy, Naveen N Rao, Krzysztof Kozlowski, Conor Dooley,
Damien Le Moal, Niklas Cassel, Herbert Xu, David S. Miller,
Lee Jones, Vinod Koul, Lorenzo Pieralisi,
Krzysztof Wilczyński, Manivannan Sadhasivam, Bjorn Helgaas,
J. Neuschäfer, Wim Van Sebroeck, Guenter Roeck, Mark Brown,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-kernel, linux-ide, linux-crypto, dmaengine, linux-pci,
linux-watchdog, linux-spi, linux-mtd
On Sun, Jan 26, 2025 at 10:41:28PM -0600, Rob Herring wrote:
> On Sun, Jan 26, 2025 at 07:58:58PM +0100, J. Neuschäfer wrote:
> > Convert the Freescale security engine (crypto accelerator) binding from
> > text form to YAML. The list of compatible strings reflects what was
> > previously described in prose; not all combinations occur in existing
> > devicetrees.
> >
> > Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
> > ---
> > .../devicetree/bindings/crypto/fsl,sec2.0.yaml | 139 +++++++++++++++++++++
> > .../devicetree/bindings/crypto/fsl-sec2.txt | 65 ----------
> > 2 files changed, 139 insertions(+), 65 deletions(-)
[...]
> > +properties:
> > + compatible:
> > + description: |
>
> Don't need '|'. I imagine there are more in the series, but will let you
> find the rest.
Yes
> > + fsl,num-channels:
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + description: An integer representing the number of channels available.
>
> minimum: 1
> maximum: ?
According to existing usage (and a cursory study of datasheets),
possible values are 1 or 4.
>
> > +
> > + fsl,channel-fifo-len:
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + description: |
> > + An integer representing the number of descriptor pointers each channel
> > + fetch fifo can hold.
>
> Constraints?
Current usage shows a typical value of 24, although I wasn't able to
find any information in the datasheets. I'll add plausible limits.
>
> > +
> > + fsl,exec-units-mask:
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + description: |
> > + The bitmask representing what execution units (EUs) are available.
> > + EU information should be encoded following the SEC's Descriptor Header
> > + Dword EU_SEL0 field documentation, i.e. as follows:
> > +
> > + bit 0 = reserved - should be 0
> > + bit 1 = set if SEC has the ARC4 EU (AFEU)
> > + bit 2 = set if SEC has the DES/3DES EU (DEU)
> > + bit 3 = set if SEC has the message digest EU (MDEU/MDEU-A)
> > + bit 4 = set if SEC has the random number generator EU (RNG)
> > + bit 5 = set if SEC has the public key EU (PKEU)
> > + bit 6 = set if SEC has the AES EU (AESU)
> > + bit 7 = set if SEC has the Kasumi EU (KEU)
> > + bit 8 = set if SEC has the CRC EU (CRCU)
> > + bit 11 = set if SEC has the message digest EU extended alg set (MDEU-B)
> > +
> > + remaining bits are reserved for future SEC EUs.
>
> So:
>
> maximum: 0xfff
Will add.
Thank you for your reviews.
Best regards,
J. Neuschäfer
^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH 4/9] dt-bindings: mfd: Convert fsl,mcu-mpc8349emitx binding to YAML
2025-01-26 18:58 [PATCH 0/9] YAML conversion of several Freescale/PowerPC DT bindings J. Neuschäfer via B4 Relay
` (2 preceding siblings ...)
2025-01-26 18:58 ` [PATCH 3/9] dt-bindings: crypto: Convert fsl,sec-2.0 " J. Neuschäfer via B4 Relay
@ 2025-01-26 18:58 ` J. Neuschäfer via B4 Relay
2025-01-27 4:42 ` Rob Herring
2025-02-11 14:13 ` (subset) " Lee Jones
2025-01-26 18:59 ` [PATCH 5/9] dt-bindings: dma: Convert fsl,elo*-dma bindings " J. Neuschäfer via B4 Relay
` (5 subsequent siblings)
9 siblings, 2 replies; 41+ messages in thread
From: J. Neuschäfer via B4 Relay @ 2025-01-26 18:58 UTC (permalink / raw)
To: devicetree, linuxppc-dev
Cc: Scott Wood, Madhavan Srinivasan, Michael Ellerman,
Nicholas Piggin, Christophe Leroy, Naveen N Rao, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Damien Le Moal, Niklas Cassel,
Herbert Xu, David S. Miller, Lee Jones, Vinod Koul,
Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Bjorn Helgaas, J. Neuschäfer,
Wim Van Sebroeck, Guenter Roeck, Mark Brown, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-kernel, linux-ide,
linux-crypto, dmaengine, linux-pci, linux-watchdog, linux-spi,
linux-mtd, J. Neuschäfer
From: "J. Neuschäfer" <j.ne@posteo.net>
Convert mcu-mpc8349emitx.txt to YAML and list the compatible strings
currently in use.
Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
---
.../bindings/mfd/fsl,mcu-mpc8349emitx.yaml | 53 ++++++++++++++++++++++
.../bindings/powerpc/fsl/mcu-mpc8349emitx.txt | 17 -------
2 files changed, 53 insertions(+), 17 deletions(-)
diff --git a/Documentation/devicetree/bindings/mfd/fsl,mcu-mpc8349emitx.yaml b/Documentation/devicetree/bindings/mfd/fsl,mcu-mpc8349emitx.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..8beb2ed9edb745f513deb5755d6802309b069f46
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/fsl,mcu-mpc8349emitx.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/fsl,mcu-mpc8349emitx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale MPC8349E-mITX-compatible Power Management Micro Controller Unit (MCU)
+
+maintainers:
+ - J. Neuschäfer <j.ne@posteo.net>
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - fsl,mc9s08qg8-mpc8315erdb
+ - fsl,mc9s08qg8-mpc8349emitx
+ - fsl,mc9s08qg8-mpc8377erdb
+ - fsl,mc9s08qg8-mpc8378erdb
+ - fsl,mc9s08qg8-mpc8379erdb
+ - const: fsl,mcu-mpc8349emitx
+
+ reg:
+ maxItems: 1
+
+ "#gpio-cells":
+ const: 2
+
+ gpio-controller: true
+
+required:
+ - compatible
+ - reg
+ - "#gpio-cells"
+ - gpio-controller
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mcu@a {
+ #gpio-cells = <2>;
+ compatible = "fsl,mc9s08qg8-mpc8349emitx",
+ "fsl,mcu-mpc8349emitx";
+ reg = <0x0a>;
+ gpio-controller;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mcu-mpc8349emitx.txt b/Documentation/devicetree/bindings/powerpc/fsl/mcu-mpc8349emitx.txt
deleted file mode 100644
index 37f91fa576545aa245d893c24248bdbb2c0fcc07..0000000000000000000000000000000000000000
--- a/Documentation/devicetree/bindings/powerpc/fsl/mcu-mpc8349emitx.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-Freescale MPC8349E-mITX-compatible Power Management Micro Controller Unit (MCU)
-
-Required properties:
-- compatible : "fsl,<mcu-chip>-<board>", "fsl,mcu-mpc8349emitx".
-- reg : should specify I2C address (0x0a).
-- #gpio-cells : should be 2.
-- gpio-controller : should be present.
-
-Example:
-
-mcu@a {
- #gpio-cells = <2>;
- compatible = "fsl,mc9s08qg8-mpc8349emitx",
- "fsl,mcu-mpc8349emitx";
- reg = <0x0a>;
- gpio-controller;
-};
--
2.48.0.rc1.219.gb6b6757d772
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [PATCH 4/9] dt-bindings: mfd: Convert fsl,mcu-mpc8349emitx binding to YAML
2025-01-26 18:58 ` [PATCH 4/9] dt-bindings: mfd: Convert fsl,mcu-mpc8349emitx " J. Neuschäfer via B4 Relay
@ 2025-01-27 4:42 ` Rob Herring
2025-02-11 14:13 ` (subset) " Lee Jones
1 sibling, 0 replies; 41+ messages in thread
From: Rob Herring @ 2025-01-27 4:42 UTC (permalink / raw)
To: J. Neuschäfer
Cc: devicetree, linuxppc-dev, Scott Wood, Madhavan Srinivasan,
Michael Ellerman, Nicholas Piggin, Christophe Leroy, Naveen N Rao,
Krzysztof Kozlowski, Conor Dooley, Damien Le Moal, Niklas Cassel,
Herbert Xu, David S. Miller, Lee Jones, Vinod Koul,
Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Bjorn Helgaas, J. Neuschäfer,
Wim Van Sebroeck, Guenter Roeck, Mark Brown, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-kernel, linux-ide,
linux-crypto, dmaengine, linux-pci, linux-watchdog, linux-spi,
linux-mtd
On Sun, Jan 26, 2025 at 07:58:59PM +0100, J. Neuschäfer wrote:
> Convert mcu-mpc8349emitx.txt to YAML and list the compatible strings
> currently in use.
>
> Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
> ---
> .../bindings/mfd/fsl,mcu-mpc8349emitx.yaml | 53 ++++++++++++++++++++++
> .../bindings/powerpc/fsl/mcu-mpc8349emitx.txt | 17 -------
> 2 files changed, 53 insertions(+), 17 deletions(-)
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: (subset) [PATCH 4/9] dt-bindings: mfd: Convert fsl,mcu-mpc8349emitx binding to YAML
2025-01-26 18:58 ` [PATCH 4/9] dt-bindings: mfd: Convert fsl,mcu-mpc8349emitx " J. Neuschäfer via B4 Relay
2025-01-27 4:42 ` Rob Herring
@ 2025-02-11 14:13 ` Lee Jones
1 sibling, 0 replies; 41+ messages in thread
From: Lee Jones @ 2025-02-11 14:13 UTC (permalink / raw)
To: devicetree, linuxppc-dev, J. Neuschäfer
Cc: Scott Wood, Madhavan Srinivasan, Michael Ellerman,
Nicholas Piggin, Christophe Leroy, Naveen N Rao, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Damien Le Moal, Niklas Cassel,
Herbert Xu, David S. Miller, Lee Jones, Vinod Koul,
Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Bjorn Helgaas, J. Neuschäfer,
Wim Van Sebroeck, Guenter Roeck, Mark Brown, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-kernel, linux-ide,
linux-crypto, dmaengine, linux-pci, linux-watchdog, linux-spi,
linux-mtd
On Sun, 26 Jan 2025 19:58:59 +0100, J. Neuschäfer wrote:
> Convert mcu-mpc8349emitx.txt to YAML and list the compatible strings
> currently in use.
>
>
Applied, thanks!
[4/9] dt-bindings: mfd: Convert fsl,mcu-mpc8349emitx binding to YAML
commit: 252c95ec3802a5f447df58253575b52aa741c1a1
--
Lee Jones [李琼斯]
^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH 5/9] dt-bindings: dma: Convert fsl,elo*-dma bindings to YAML
2025-01-26 18:58 [PATCH 0/9] YAML conversion of several Freescale/PowerPC DT bindings J. Neuschäfer via B4 Relay
` (3 preceding siblings ...)
2025-01-26 18:58 ` [PATCH 4/9] dt-bindings: mfd: Convert fsl,mcu-mpc8349emitx " J. Neuschäfer via B4 Relay
@ 2025-01-26 18:59 ` J. Neuschäfer via B4 Relay
2025-01-27 4:47 ` Rob Herring
2025-01-29 22:52 ` Frank Li
2025-01-26 18:59 ` [PATCH 6/9] dt-bindings: pci: Add fsl,mpc83xx-pcie bindings J. Neuschäfer via B4 Relay
` (4 subsequent siblings)
9 siblings, 2 replies; 41+ messages in thread
From: J. Neuschäfer via B4 Relay @ 2025-01-26 18:59 UTC (permalink / raw)
To: devicetree, linuxppc-dev
Cc: Scott Wood, Madhavan Srinivasan, Michael Ellerman,
Nicholas Piggin, Christophe Leroy, Naveen N Rao, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Damien Le Moal, Niklas Cassel,
Herbert Xu, David S. Miller, Lee Jones, Vinod Koul,
Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Bjorn Helgaas, J. Neuschäfer,
Wim Van Sebroeck, Guenter Roeck, Mark Brown, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-kernel, linux-ide,
linux-crypto, dmaengine, linux-pci, linux-watchdog, linux-spi,
linux-mtd, J. Neuschäfer
From: "J. Neuschäfer" <j.ne@posteo.net>
The devicetree bindings for Freescale DMA engines have so far existed as
a text file. This patch converts them to YAML, and specifies all the
compatible strings currently in use in arch/powerpc/boot/dts.
Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
---
.../devicetree/bindings/dma/fsl,elo-dma.yaml | 129 +++++++++++++
.../devicetree/bindings/dma/fsl,elo3-dma.yaml | 105 +++++++++++
.../devicetree/bindings/dma/fsl,eloplus-dma.yaml | 120 ++++++++++++
.../devicetree/bindings/powerpc/fsl/dma.txt | 204 ---------------------
4 files changed, 354 insertions(+), 204 deletions(-)
diff --git a/Documentation/devicetree/bindings/dma/fsl,elo-dma.yaml b/Documentation/devicetree/bindings/dma/fsl,elo-dma.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..d1f4978a672c1217c322c27f243470b2de8c99d4
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/fsl,elo-dma.yaml
@@ -0,0 +1,129 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/fsl,elo-dma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale Elo DMA Controller
+
+maintainers:
+ - J. Neuschäfer <j.ne@posteo.net>
+
+description: |
+ This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
+ series chips such as mpc8315, mpc8349, mpc8379 etc.
+
+ Note on DMA channel compatible properties: The compatible property must say
+ "fsl,elo-dma-channel" or "fsl,eloplus-dma-channel" to be used by the Elo DMA
+ driver (fsldma). Any DMA channel used by fsldma cannot be used by another
+ DMA driver, such as the SSI sound drivers for the MPC8610. Therefore, any
+ DMA channel that should be used for another driver should not use
+ "fsl,elo-dma-channel" or "fsl,eloplus-dma-channel". For the SSI drivers, for
+ example, the compatible property should be "fsl,ssi-dma-channel". See
+ ssi.txt for more information.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - fsl,mpc8313-dma
+ - fsl,mpc8315-dma
+ - fsl,mpc8323-dma
+ - fsl,mpc8347-dma
+ - fsl,mpc8349-dma
+ - fsl,mpc8360-dma
+ - fsl,mpc8377-dma
+ - fsl,mpc8378-dma
+ - fsl,mpc8379-dma
+ - const: fsl,elo-dma
+
+ reg:
+ maxItems: 1
+ description:
+ DMA General Status Register, i.e. DGSR which contains status for
+ all the 4 DMA channels.
+
+ ranges: true
+
+ cell-index:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Controller index. 0 for controller @ 0x8100.
+
+ interrupts:
+ maxItems: 1
+
+patternProperties:
+ "^dma-channel@.*$":
+ type: object
+
+ properties:
+ compatible:
+ items:
+ - enum:
+ - fsl,mpc8315-dma-channel
+ - fsl,mpc8323-dma-channel
+ - fsl,mpc8347-dma-channel
+ - fsl,mpc8349-dma-channel
+ - fsl,mpc8360-dma-channel
+ - fsl,mpc8377-dma-channel
+ - fsl,mpc8378-dma-channel
+ - fsl,mpc8379-dma-channel
+ - const: fsl,elo-dma-channel
+
+ reg:
+ maxItems: 1
+
+ cell-index:
+ description: DMA channel index starts at 0.
+
+ interrupts: true
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: true
+
+examples:
+ - |
+ dma@82a8 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
+ reg = <0x82a8 4>;
+ ranges = <0 0x8100 0x1a4>;
+ interrupt-parent = <&ipic>;
+ interrupts = <71 8>;
+ cell-index = <0>;
+ dma-channel@0 {
+ compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
+ cell-index = <0>;
+ reg = <0 0x80>;
+ interrupt-parent = <&ipic>;
+ interrupts = <71 8>;
+ };
+ dma-channel@80 {
+ compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
+ cell-index = <1>;
+ reg = <0x80 0x80>;
+ interrupt-parent = <&ipic>;
+ interrupts = <71 8>;
+ };
+ dma-channel@100 {
+ compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
+ cell-index = <2>;
+ reg = <0x100 0x80>;
+ interrupt-parent = <&ipic>;
+ interrupts = <71 8>;
+ };
+ dma-channel@180 {
+ compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
+ cell-index = <3>;
+ reg = <0x180 0x80>;
+ interrupt-parent = <&ipic>;
+ interrupts = <71 8>;
+ };
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/dma/fsl,elo3-dma.yaml b/Documentation/devicetree/bindings/dma/fsl,elo3-dma.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..d4853ffd40dc75c7fcdc0dfb15e497ec56f3e1ba
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/fsl,elo3-dma.yaml
@@ -0,0 +1,105 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/fsl,elo3-dma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale Elo3 DMA Controller
+
+maintainers:
+ - J. Neuschäfer <j.ne@posteo.net>
+
+description: |
+ DMA controller which has same function as EloPlus except that Elo3 has 8
+ channels while EloPlus has only 4, it is used in Freescale Txxx and Bxxx
+ series chips, such as t1040, t4240, b4860.
+
+ Note on DMA channel compatible properties: The compatible property must say
+ "fsl,elo-dma-channel" or "fsl,eloplus-dma-channel" to be used by the Elo DMA
+ driver (fsldma). Any DMA channel used by fsldma cannot be used by another
+ DMA driver, such as the SSI sound drivers for the MPC8610. Therefore, any DMA
+ channel that should be used for another driver should not use
+ "fsl,elo-dma-channel" or "fsl,eloplus-dma-channel". For the SSI drivers, for
+ example, the compatible property should be "fsl,ssi-dma-channel". See ssi.txt
+ for more information.
+
+properties:
+ compatible:
+ const: fsl,elo3-dma
+
+ reg:
+ maxItems: 2
+ description: |
+ contains two entries for DMA General Status Registers, i.e. DGSR0 which
+ includes status for channel 1~4, and DGSR1 for channel 5~8
+
+ interrupts:
+ maxItems: 1
+
+patternProperties:
+ "^dma-channel@.*$":
+ type: object
+
+ properties:
+ compatible:
+ const: fsl,eloplus-dma-channel
+
+ reg:
+ maxItems: 1
+
+ interrupts: true
+
+examples:
+ - |
+ dma@100300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,elo3-dma";
+ reg = <0x100300 0x4>,
+ <0x100600 0x4>;
+ ranges = <0x0 0x100100 0x500>;
+ dma-channel@0 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ interrupts = <28 2 0 0>;
+ };
+ dma-channel@80 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ interrupts = <29 2 0 0>;
+ };
+ dma-channel@100 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ interrupts = <30 2 0 0>;
+ };
+ dma-channel@180 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ interrupts = <31 2 0 0>;
+ };
+ dma-channel@300 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x300 0x80>;
+ interrupts = <76 2 0 0>;
+ };
+ dma-channel@380 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x380 0x80>;
+ interrupts = <77 2 0 0>;
+ };
+ dma-channel@400 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x400 0x80>;
+ interrupts = <78 2 0 0>;
+ };
+ dma-channel@480 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x480 0x80>;
+ interrupts = <79 2 0 0>;
+ };
+ };
+
+additionalProperties: true
+
+...
diff --git a/Documentation/devicetree/bindings/dma/fsl,eloplus-dma.yaml b/Documentation/devicetree/bindings/dma/fsl,eloplus-dma.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..680d64332ddf4d6d68ee8c607ac71211a7e19e6e
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/fsl,eloplus-dma.yaml
@@ -0,0 +1,120 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/fsl,eloplus-dma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale EloPlus DMA Controller
+
+maintainers:
+ - J. Neuschäfer <j.ne@posteo.net>
+
+description: |
+ This is a 4-channel DMA controller with extended addresses and chaining,
+ mainly used in Freescale mpc85xx/86xx, Pxxx and BSC series chips, such as
+ mpc8540, mpc8641 p4080, bsc9131 etc.
+
+ Note on DMA channel compatible properties: The compatible property must say
+ "fsl,elo-dma-channel" or "fsl,eloplus-dma-channel" to be used by the Elo DMA
+ driver (fsldma). Any DMA channel used by fsldma cannot be used by another
+ DMA driver, such as the SSI sound drivers for the MPC8610. Therefore, any DMA
+ channel that should be used for another driver should not use
+ "fsl,elo-dma-channel" or "fsl,eloplus-dma-channel". For the SSI drivers, for
+ example, the compatible property should be "fsl,ssi-dma-channel". See ssi.txt
+ for more information.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - fsl,mpc8540-dma
+ - fsl,mpc8541-dma
+ - fsl,mpc8548-dma
+ - fsl,mpc8555-dma
+ - fsl,mpc8560-dma
+ - fsl,mpc8572-dma
+ - fsl,mpc8641-dma
+ - const: fsl,eloplus-dma
+ - const: fsl,eloplus-dma
+
+ reg:
+ maxItems: 1
+ description:
+ DMA General Status Register, i.e. DGSR which contains
+ status for all the 4 DMA channels
+
+ cell-index:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ controller index. 0 for controller @ 0x21000, 1 for controller @ 0xc000
+
+ interrupts:
+ maxItems: 1
+
+patternProperties:
+ "^dma-channel@.*$":
+ type: object
+
+ properties:
+ compatible:
+ items:
+ - enum:
+ - fsl,mpc8540-dma-channel
+ - fsl,mpc8541-dma-channel
+ - fsl,mpc8548-dma-channel
+ - fsl,mpc8555-dma-channel
+ - fsl,mpc8560-dma-channel
+ - fsl,mpc8572-dma-channel
+ - const: fsl,eloplus-dma-channel
+
+ reg:
+ maxItems: 1
+
+ cell-index:
+ description: DMA channel index starts at 0.
+
+ interrupts: true
+
+examples:
+ - |
+ dma@21300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
+ reg = <0x21300 4>;
+ ranges = <0 0x21100 0x200>;
+ cell-index = <0>;
+ dma-channel@0 {
+ compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
+ reg = <0 0x80>;
+ cell-index = <0>;
+ interrupt-parent = <&mpic>;
+ interrupts = <20 2>;
+ };
+ dma-channel@80 {
+ compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ cell-index = <1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <21 2>;
+ };
+ dma-channel@100 {
+ compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ cell-index = <2>;
+ interrupt-parent = <&mpic>;
+ interrupts = <22 2>;
+ };
+ dma-channel@180 {
+ compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ cell-index = <3>;
+ interrupt-parent = <&mpic>;
+ interrupts = <23 2>;
+ };
+ };
+
+additionalProperties: true
+
+...
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/dma.txt b/Documentation/devicetree/bindings/powerpc/fsl/dma.txt
deleted file mode 100644
index c11ad5c6db2190bf38c160632d9997122e169945..0000000000000000000000000000000000000000
--- a/Documentation/devicetree/bindings/powerpc/fsl/dma.txt
+++ /dev/null
@@ -1,204 +0,0 @@
-* Freescale DMA Controllers
-
-** Freescale Elo DMA Controller
- This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
- series chips such as mpc8315, mpc8349, mpc8379 etc.
-
-Required properties:
-
-- compatible : must include "fsl,elo-dma"
-- reg : DMA General Status Register, i.e. DGSR which contains
- status for all the 4 DMA channels
-- ranges : describes the mapping between the address space of the
- DMA channels and the address space of the DMA controller
-- cell-index : controller index. 0 for controller @ 0x8100
-- interrupts : interrupt specifier for DMA IRQ
-
-- DMA channel nodes:
- - compatible : must include "fsl,elo-dma-channel"
- However, see note below.
- - reg : DMA channel specific registers
- - cell-index : DMA channel index starts at 0.
-
-Optional properties:
- - interrupts : interrupt specifier for DMA channel IRQ
- (on 83xx this is expected to be identical to
- the interrupts property of the parent node)
-
-Example:
- dma@82a8 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
- reg = <0x82a8 4>;
- ranges = <0 0x8100 0x1a4>;
- interrupt-parent = <&ipic>;
- interrupts = <71 8>;
- cell-index = <0>;
- dma-channel@0 {
- compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
- cell-index = <0>;
- reg = <0 0x80>;
- interrupt-parent = <&ipic>;
- interrupts = <71 8>;
- };
- dma-channel@80 {
- compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
- cell-index = <1>;
- reg = <0x80 0x80>;
- interrupt-parent = <&ipic>;
- interrupts = <71 8>;
- };
- dma-channel@100 {
- compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
- cell-index = <2>;
- reg = <0x100 0x80>;
- interrupt-parent = <&ipic>;
- interrupts = <71 8>;
- };
- dma-channel@180 {
- compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
- cell-index = <3>;
- reg = <0x180 0x80>;
- interrupt-parent = <&ipic>;
- interrupts = <71 8>;
- };
- };
-
-** Freescale EloPlus DMA Controller
- This is a 4-channel DMA controller with extended addresses and chaining,
- mainly used in Freescale mpc85xx/86xx, Pxxx and BSC series chips, such as
- mpc8540, mpc8641 p4080, bsc9131 etc.
-
-Required properties:
-
-- compatible : must include "fsl,eloplus-dma"
-- reg : DMA General Status Register, i.e. DGSR which contains
- status for all the 4 DMA channels
-- cell-index : controller index. 0 for controller @ 0x21000,
- 1 for controller @ 0xc000
-- ranges : describes the mapping between the address space of the
- DMA channels and the address space of the DMA controller
-
-- DMA channel nodes:
- - compatible : must include "fsl,eloplus-dma-channel"
- However, see note below.
- - cell-index : DMA channel index starts at 0.
- - reg : DMA channel specific registers
- - interrupts : interrupt specifier for DMA channel IRQ
-
-Example:
- dma@21300 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
- reg = <0x21300 4>;
- ranges = <0 0x21100 0x200>;
- cell-index = <0>;
- dma-channel@0 {
- compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
- reg = <0 0x80>;
- cell-index = <0>;
- interrupt-parent = <&mpic>;
- interrupts = <20 2>;
- };
- dma-channel@80 {
- compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
- reg = <0x80 0x80>;
- cell-index = <1>;
- interrupt-parent = <&mpic>;
- interrupts = <21 2>;
- };
- dma-channel@100 {
- compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
- reg = <0x100 0x80>;
- cell-index = <2>;
- interrupt-parent = <&mpic>;
- interrupts = <22 2>;
- };
- dma-channel@180 {
- compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
- reg = <0x180 0x80>;
- cell-index = <3>;
- interrupt-parent = <&mpic>;
- interrupts = <23 2>;
- };
- };
-
-** Freescale Elo3 DMA Controller
- DMA controller which has same function as EloPlus except that Elo3 has 8
- channels while EloPlus has only 4, it is used in Freescale Txxx and Bxxx
- series chips, such as t1040, t4240, b4860.
-
-Required properties:
-
-- compatible : must include "fsl,elo3-dma"
-- reg : contains two entries for DMA General Status Registers,
- i.e. DGSR0 which includes status for channel 1~4, and
- DGSR1 for channel 5~8
-- ranges : describes the mapping between the address space of the
- DMA channels and the address space of the DMA controller
-
-- DMA channel nodes:
- - compatible : must include "fsl,eloplus-dma-channel"
- - reg : DMA channel specific registers
- - interrupts : interrupt specifier for DMA channel IRQ
-
-Example:
-dma@100300 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "fsl,elo3-dma";
- reg = <0x100300 0x4>,
- <0x100600 0x4>;
- ranges = <0x0 0x100100 0x500>;
- dma-channel@0 {
- compatible = "fsl,eloplus-dma-channel";
- reg = <0x0 0x80>;
- interrupts = <28 2 0 0>;
- };
- dma-channel@80 {
- compatible = "fsl,eloplus-dma-channel";
- reg = <0x80 0x80>;
- interrupts = <29 2 0 0>;
- };
- dma-channel@100 {
- compatible = "fsl,eloplus-dma-channel";
- reg = <0x100 0x80>;
- interrupts = <30 2 0 0>;
- };
- dma-channel@180 {
- compatible = "fsl,eloplus-dma-channel";
- reg = <0x180 0x80>;
- interrupts = <31 2 0 0>;
- };
- dma-channel@300 {
- compatible = "fsl,eloplus-dma-channel";
- reg = <0x300 0x80>;
- interrupts = <76 2 0 0>;
- };
- dma-channel@380 {
- compatible = "fsl,eloplus-dma-channel";
- reg = <0x380 0x80>;
- interrupts = <77 2 0 0>;
- };
- dma-channel@400 {
- compatible = "fsl,eloplus-dma-channel";
- reg = <0x400 0x80>;
- interrupts = <78 2 0 0>;
- };
- dma-channel@480 {
- compatible = "fsl,eloplus-dma-channel";
- reg = <0x480 0x80>;
- interrupts = <79 2 0 0>;
- };
-};
-
-Note on DMA channel compatible properties: The compatible property must say
-"fsl,elo-dma-channel" or "fsl,eloplus-dma-channel" to be used by the Elo DMA
-driver (fsldma). Any DMA channel used by fsldma cannot be used by another
-DMA driver, such as the SSI sound drivers for the MPC8610. Therefore, any DMA
-channel that should be used for another driver should not use
-"fsl,elo-dma-channel" or "fsl,eloplus-dma-channel". For the SSI drivers, for
-example, the compatible property should be "fsl,ssi-dma-channel". See ssi.txt
-for more information.
--
2.48.0.rc1.219.gb6b6757d772
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [PATCH 5/9] dt-bindings: dma: Convert fsl,elo*-dma bindings to YAML
2025-01-26 18:59 ` [PATCH 5/9] dt-bindings: dma: Convert fsl,elo*-dma bindings " J. Neuschäfer via B4 Relay
@ 2025-01-27 4:47 ` Rob Herring
2025-01-31 14:03 ` J. Neuschäfer
2025-01-29 22:52 ` Frank Li
1 sibling, 1 reply; 41+ messages in thread
From: Rob Herring @ 2025-01-27 4:47 UTC (permalink / raw)
To: J. Neuschäfer
Cc: devicetree, linuxppc-dev, Scott Wood, Madhavan Srinivasan,
Michael Ellerman, Nicholas Piggin, Christophe Leroy, Naveen N Rao,
Krzysztof Kozlowski, Conor Dooley, Damien Le Moal, Niklas Cassel,
Herbert Xu, David S. Miller, Lee Jones, Vinod Koul,
Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Bjorn Helgaas, J. Neuschäfer,
Wim Van Sebroeck, Guenter Roeck, Mark Brown, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-kernel, linux-ide,
linux-crypto, dmaengine, linux-pci, linux-watchdog, linux-spi,
linux-mtd
On Sun, Jan 26, 2025 at 07:59:00PM +0100, J. Neuschäfer wrote:
> The devicetree bindings for Freescale DMA engines have so far existed as
> a text file. This patch converts them to YAML, and specifies all the
> compatible strings currently in use in arch/powerpc/boot/dts.
>
> Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
> ---
> .../devicetree/bindings/dma/fsl,elo-dma.yaml | 129 +++++++++++++
> .../devicetree/bindings/dma/fsl,elo3-dma.yaml | 105 +++++++++++
> .../devicetree/bindings/dma/fsl,eloplus-dma.yaml | 120 ++++++++++++
> .../devicetree/bindings/powerpc/fsl/dma.txt | 204 ---------------------
> 4 files changed, 354 insertions(+), 204 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/dma/fsl,elo-dma.yaml b/Documentation/devicetree/bindings/dma/fsl,elo-dma.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..d1f4978a672c1217c322c27f243470b2de8c99d4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/fsl,elo-dma.yaml
> @@ -0,0 +1,129 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/dma/fsl,elo-dma.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale Elo DMA Controller
> +
> +maintainers:
> + - J. Neuschäfer <j.ne@posteo.net>
> +
> +description: |
> + This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
> + series chips such as mpc8315, mpc8349, mpc8379 etc.
> +
> + Note on DMA channel compatible properties: The compatible property must say
> + "fsl,elo-dma-channel" or "fsl,eloplus-dma-channel" to be used by the Elo DMA
> + driver (fsldma). Any DMA channel used by fsldma cannot be used by another
> + DMA driver, such as the SSI sound drivers for the MPC8610. Therefore, any
> + DMA channel that should be used for another driver should not use
> + "fsl,elo-dma-channel" or "fsl,eloplus-dma-channel". For the SSI drivers, for
> + example, the compatible property should be "fsl,ssi-dma-channel". See
> + ssi.txt for more information.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - fsl,mpc8313-dma
> + - fsl,mpc8315-dma
> + - fsl,mpc8323-dma
> + - fsl,mpc8347-dma
> + - fsl,mpc8349-dma
> + - fsl,mpc8360-dma
> + - fsl,mpc8377-dma
> + - fsl,mpc8378-dma
> + - fsl,mpc8379-dma
> + - const: fsl,elo-dma
> +
> + reg:
> + maxItems: 1
> + description:
> + DMA General Status Register, i.e. DGSR which contains status for
> + all the 4 DMA channels.
> +
> + ranges: true
> +
> + cell-index:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: Controller index. 0 for controller @ 0x8100.
> +
> + interrupts:
> + maxItems: 1
> +
> +patternProperties:
> + "^dma-channel@.*$":
> + type: object
additionalProperties: false
(The tools should have highlighted this)
> +
> + properties:
> + compatible:
> + items:
> + - enum:
> + - fsl,mpc8315-dma-channel
> + - fsl,mpc8323-dma-channel
> + - fsl,mpc8347-dma-channel
> + - fsl,mpc8349-dma-channel
> + - fsl,mpc8360-dma-channel
> + - fsl,mpc8377-dma-channel
> + - fsl,mpc8378-dma-channel
> + - fsl,mpc8379-dma-channel
> + - const: fsl,elo-dma-channel
> +
> + reg:
> + maxItems: 1
> +
> + cell-index:
> + description: DMA channel index starts at 0.
> +
> + interrupts: true
You have to define how many interrupts and what they are.
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> +
> +additionalProperties: true
> +
> +examples:
> + - |
> + dma@82a8 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
> + reg = <0x82a8 4>;
> + ranges = <0 0x8100 0x1a4>;
> + interrupt-parent = <&ipic>;
> + interrupts = <71 8>;
> + cell-index = <0>;
> + dma-channel@0 {
> + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
> + cell-index = <0>;
> + reg = <0 0x80>;
> + interrupt-parent = <&ipic>;
> + interrupts = <71 8>;
> + };
> + dma-channel@80 {
> + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
> + cell-index = <1>;
> + reg = <0x80 0x80>;
> + interrupt-parent = <&ipic>;
> + interrupts = <71 8>;
> + };
> + dma-channel@100 {
> + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
> + cell-index = <2>;
> + reg = <0x100 0x80>;
> + interrupt-parent = <&ipic>;
> + interrupts = <71 8>;
> + };
> + dma-channel@180 {
> + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
> + cell-index = <3>;
> + reg = <0x180 0x80>;
> + interrupt-parent = <&ipic>;
> + interrupts = <71 8>;
> + };
> + };
> +
> +...
> diff --git a/Documentation/devicetree/bindings/dma/fsl,elo3-dma.yaml b/Documentation/devicetree/bindings/dma/fsl,elo3-dma.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..d4853ffd40dc75c7fcdc0dfb15e497ec56f3e1ba
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/fsl,elo3-dma.yaml
> @@ -0,0 +1,105 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/dma/fsl,elo3-dma.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale Elo3 DMA Controller
> +
> +maintainers:
> + - J. Neuschäfer <j.ne@posteo.net>
> +
> +description: |
> + DMA controller which has same function as EloPlus except that Elo3 has 8
> + channels while EloPlus has only 4, it is used in Freescale Txxx and Bxxx
> + series chips, such as t1040, t4240, b4860.
> +
> + Note on DMA channel compatible properties: The compatible property must say
> + "fsl,elo-dma-channel" or "fsl,eloplus-dma-channel" to be used by the Elo DMA
> + driver (fsldma). Any DMA channel used by fsldma cannot be used by another
> + DMA driver, such as the SSI sound drivers for the MPC8610. Therefore, any DMA
> + channel that should be used for another driver should not use
> + "fsl,elo-dma-channel" or "fsl,eloplus-dma-channel". For the SSI drivers, for
> + example, the compatible property should be "fsl,ssi-dma-channel". See ssi.txt
> + for more information.
> +
> +properties:
> + compatible:
> + const: fsl,elo3-dma
> +
> + reg:
> + maxItems: 2
> + description: |
> + contains two entries for DMA General Status Registers, i.e. DGSR0 which
> + includes status for channel 1~4, and DGSR1 for channel 5~8
> +
> + interrupts:
> + maxItems: 1
> +
> +patternProperties:
> + "^dma-channel@.*$":
> + type: object
additionalProperties: false
> +
> + properties:
> + compatible:
> + const: fsl,eloplus-dma-channel
> +
> + reg:
> + maxItems: 1
> +
> + interrupts: true
You have to define how many interrupts.
> +
> +examples:
> + - |
> + dma@100300 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "fsl,elo3-dma";
> + reg = <0x100300 0x4>,
> + <0x100600 0x4>;
> + ranges = <0x0 0x100100 0x500>;
> + dma-channel@0 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x0 0x80>;
> + interrupts = <28 2 0 0>;
> + };
> + dma-channel@80 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x80 0x80>;
> + interrupts = <29 2 0 0>;
> + };
> + dma-channel@100 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x100 0x80>;
> + interrupts = <30 2 0 0>;
> + };
> + dma-channel@180 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x180 0x80>;
> + interrupts = <31 2 0 0>;
> + };
> + dma-channel@300 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x300 0x80>;
> + interrupts = <76 2 0 0>;
> + };
> + dma-channel@380 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x380 0x80>;
> + interrupts = <77 2 0 0>;
> + };
> + dma-channel@400 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x400 0x80>;
> + interrupts = <78 2 0 0>;
> + };
> + dma-channel@480 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x480 0x80>;
> + interrupts = <79 2 0 0>;
> + };
> + };
> +
> +additionalProperties: true
> +
> +...
> diff --git a/Documentation/devicetree/bindings/dma/fsl,eloplus-dma.yaml b/Documentation/devicetree/bindings/dma/fsl,eloplus-dma.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..680d64332ddf4d6d68ee8c607ac71211a7e19e6e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/fsl,eloplus-dma.yaml
> @@ -0,0 +1,120 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/dma/fsl,eloplus-dma.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale EloPlus DMA Controller
> +
> +maintainers:
> + - J. Neuschäfer <j.ne@posteo.net>
> +
> +description: |
> + This is a 4-channel DMA controller with extended addresses and chaining,
> + mainly used in Freescale mpc85xx/86xx, Pxxx and BSC series chips, such as
> + mpc8540, mpc8641 p4080, bsc9131 etc.
> +
> + Note on DMA channel compatible properties: The compatible property must say
> + "fsl,elo-dma-channel" or "fsl,eloplus-dma-channel" to be used by the Elo DMA
> + driver (fsldma). Any DMA channel used by fsldma cannot be used by another
> + DMA driver, such as the SSI sound drivers for the MPC8610. Therefore, any DMA
> + channel that should be used for another driver should not use
> + "fsl,elo-dma-channel" or "fsl,eloplus-dma-channel". For the SSI drivers, for
> + example, the compatible property should be "fsl,ssi-dma-channel". See ssi.txt
> + for more information.
> +
> +properties:
> + compatible:
> + oneOf:
> + - items:
> + - enum:
> + - fsl,mpc8540-dma
> + - fsl,mpc8541-dma
> + - fsl,mpc8548-dma
> + - fsl,mpc8555-dma
> + - fsl,mpc8560-dma
> + - fsl,mpc8572-dma
> + - fsl,mpc8641-dma
> + - const: fsl,eloplus-dma
> + - const: fsl,eloplus-dma
> +
> + reg:
> + maxItems: 1
> + description:
> + DMA General Status Register, i.e. DGSR which contains
> + status for all the 4 DMA channels
> +
> + cell-index:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: |
> + controller index. 0 for controller @ 0x21000, 1 for controller @ 0xc000
> +
> + interrupts:
> + maxItems: 1
> +
> +patternProperties:
> + "^dma-channel@.*$":
> + type: object
additionalProperties: false
> +
> + properties:
> + compatible:
> + items:
> + - enum:
> + - fsl,mpc8540-dma-channel
> + - fsl,mpc8541-dma-channel
> + - fsl,mpc8548-dma-channel
> + - fsl,mpc8555-dma-channel
> + - fsl,mpc8560-dma-channel
> + - fsl,mpc8572-dma-channel
> + - const: fsl,eloplus-dma-channel
> +
> + reg:
> + maxItems: 1
> +
> + cell-index:
> + description: DMA channel index starts at 0.
> +
> + interrupts: true
How many?
> +
> +examples:
> + - |
> + dma@21300 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
> + reg = <0x21300 4>;
> + ranges = <0 0x21100 0x200>;
> + cell-index = <0>;
> + dma-channel@0 {
> + compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
> + reg = <0 0x80>;
> + cell-index = <0>;
> + interrupt-parent = <&mpic>;
> + interrupts = <20 2>;
> + };
> + dma-channel@80 {
> + compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
> + reg = <0x80 0x80>;
> + cell-index = <1>;
> + interrupt-parent = <&mpic>;
> + interrupts = <21 2>;
> + };
> + dma-channel@100 {
> + compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
> + reg = <0x100 0x80>;
> + cell-index = <2>;
> + interrupt-parent = <&mpic>;
> + interrupts = <22 2>;
> + };
> + dma-channel@180 {
> + compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
> + reg = <0x180 0x80>;
> + cell-index = <3>;
> + interrupt-parent = <&mpic>;
> + interrupts = <23 2>;
> + };
> + };
> +
> +additionalProperties: true
> +
> +...
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH 5/9] dt-bindings: dma: Convert fsl,elo*-dma bindings to YAML
2025-01-27 4:47 ` Rob Herring
@ 2025-01-31 14:03 ` J. Neuschäfer
2025-01-31 22:16 ` Rob Herring
0 siblings, 1 reply; 41+ messages in thread
From: J. Neuschäfer @ 2025-01-31 14:03 UTC (permalink / raw)
To: Rob Herring
Cc: J. Neuschäfer, devicetree, linuxppc-dev, Scott Wood,
Madhavan Srinivasan, Michael Ellerman, Nicholas Piggin,
Christophe Leroy, Naveen N Rao, Krzysztof Kozlowski, Conor Dooley,
Damien Le Moal, Niklas Cassel, Herbert Xu, David S. Miller,
Lee Jones, Vinod Koul, Lorenzo Pieralisi,
Krzysztof Wilczyński, Manivannan Sadhasivam, Bjorn Helgaas,
J. Neuschäfer, Wim Van Sebroeck, Guenter Roeck, Mark Brown,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-kernel, linux-ide, linux-crypto, dmaengine, linux-pci,
linux-watchdog, linux-spi, linux-mtd
On Sun, Jan 26, 2025 at 10:47:35PM -0600, Rob Herring wrote:
> On Sun, Jan 26, 2025 at 07:59:00PM +0100, J. Neuschäfer wrote:
> > The devicetree bindings for Freescale DMA engines have so far existed as
> > a text file. This patch converts them to YAML, and specifies all the
> > compatible strings currently in use in arch/powerpc/boot/dts.
> >
> > Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
> > ---
> > .../devicetree/bindings/dma/fsl,elo-dma.yaml | 129 +++++++++++++
> > .../devicetree/bindings/dma/fsl,elo3-dma.yaml | 105 +++++++++++
> > .../devicetree/bindings/dma/fsl,eloplus-dma.yaml | 120 ++++++++++++
> > .../devicetree/bindings/powerpc/fsl/dma.txt | 204 ---------------------
> > 4 files changed, 354 insertions(+), 204 deletions(-)
[...]
> > +patternProperties:
> > + "^dma-channel@.*$":
> > + type: object
>
> additionalProperties: false
I'll add it.
> (The tools should have highlighted this)
With dtschema 2024.11 installed, "make dt_binding_check
DT_SCHEMA_FILES=fsl,elo-dma.yaml" does not highlight this.
> > +
> > + properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - fsl,mpc8315-dma-channel
> > + - fsl,mpc8323-dma-channel
> > + - fsl,mpc8347-dma-channel
> > + - fsl,mpc8349-dma-channel
> > + - fsl,mpc8360-dma-channel
> > + - fsl,mpc8377-dma-channel
> > + - fsl,mpc8378-dma-channel
> > + - fsl,mpc8379-dma-channel
> > + - const: fsl,elo-dma-channel
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + cell-index:
> > + description: DMA channel index starts at 0.
> > +
> > + interrupts: true
>
> You have to define how many interrupts and what they are.
Will do.
(and the same for the other two files)
Best regards,
J. Neuschäfer
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 5/9] dt-bindings: dma: Convert fsl,elo*-dma bindings to YAML
2025-01-31 14:03 ` J. Neuschäfer
@ 2025-01-31 22:16 ` Rob Herring
2025-02-04 18:19 ` J. Neuschäfer
0 siblings, 1 reply; 41+ messages in thread
From: Rob Herring @ 2025-01-31 22:16 UTC (permalink / raw)
To: J. Neuschäfer
Cc: devicetree, linuxppc-dev, Scott Wood, Madhavan Srinivasan,
Michael Ellerman, Nicholas Piggin, Christophe Leroy, Naveen N Rao,
Krzysztof Kozlowski, Conor Dooley, Damien Le Moal, Niklas Cassel,
Herbert Xu, David S. Miller, Lee Jones, Vinod Koul,
Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Bjorn Helgaas, J. Neuschäfer,
Wim Van Sebroeck, Guenter Roeck, Mark Brown, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-kernel, linux-ide,
linux-crypto, dmaengine, linux-pci, linux-watchdog, linux-spi,
linux-mtd
On Fri, Jan 31, 2025 at 8:03 AM J. Neuschäfer <j.ne@posteo.net> wrote:
>
> On Sun, Jan 26, 2025 at 10:47:35PM -0600, Rob Herring wrote:
> > On Sun, Jan 26, 2025 at 07:59:00PM +0100, J. Neuschäfer wrote:
> > > The devicetree bindings for Freescale DMA engines have so far existed as
> > > a text file. This patch converts them to YAML, and specifies all the
> > > compatible strings currently in use in arch/powerpc/boot/dts.
> > >
> > > Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
> > > ---
> > > .../devicetree/bindings/dma/fsl,elo-dma.yaml | 129 +++++++++++++
> > > .../devicetree/bindings/dma/fsl,elo3-dma.yaml | 105 +++++++++++
> > > .../devicetree/bindings/dma/fsl,eloplus-dma.yaml | 120 ++++++++++++
> > > .../devicetree/bindings/powerpc/fsl/dma.txt | 204 ---------------------
> > > 4 files changed, 354 insertions(+), 204 deletions(-)
> [...]
> > > +patternProperties:
> > > + "^dma-channel@.*$":
> > > + type: object
> >
> > additionalProperties: false
>
> I'll add it.
>
> > (The tools should have highlighted this)
>
> With dtschema 2024.11 installed, "make dt_binding_check
> DT_SCHEMA_FILES=fsl,elo-dma.yaml" does not highlight this.
Actually, it's the top-level 'addtionalProperties: true' that disables
the check here. That should be false as well.
Rob
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 5/9] dt-bindings: dma: Convert fsl,elo*-dma bindings to YAML
2025-01-31 22:16 ` Rob Herring
@ 2025-02-04 18:19 ` J. Neuschäfer
0 siblings, 0 replies; 41+ messages in thread
From: J. Neuschäfer @ 2025-02-04 18:19 UTC (permalink / raw)
To: Rob Herring
Cc: J. Neuschäfer, devicetree, linuxppc-dev, Scott Wood,
Madhavan Srinivasan, Michael Ellerman, Nicholas Piggin,
Christophe Leroy, Naveen N Rao, Krzysztof Kozlowski, Conor Dooley,
Damien Le Moal, Niklas Cassel, Herbert Xu, David S. Miller,
Lee Jones, Vinod Koul, Lorenzo Pieralisi,
Krzysztof Wilczyński, Manivannan Sadhasivam, Bjorn Helgaas,
J. Neuschäfer, Wim Van Sebroeck, Guenter Roeck, Mark Brown,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-kernel, linux-ide, linux-crypto, dmaengine, linux-pci,
linux-watchdog, linux-spi, linux-mtd
On Fri, Jan 31, 2025 at 04:16:07PM -0600, Rob Herring wrote:
> On Fri, Jan 31, 2025 at 8:03 AM J. Neuschäfer <j.ne@posteo.net> wrote:
> >
> > On Sun, Jan 26, 2025 at 10:47:35PM -0600, Rob Herring wrote:
> > > On Sun, Jan 26, 2025 at 07:59:00PM +0100, J. Neuschäfer wrote:
> > > > The devicetree bindings for Freescale DMA engines have so far existed as
> > > > a text file. This patch converts them to YAML, and specifies all the
> > > > compatible strings currently in use in arch/powerpc/boot/dts.
> > > >
> > > > Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
> > > > ---
> > > > .../devicetree/bindings/dma/fsl,elo-dma.yaml | 129 +++++++++++++
> > > > .../devicetree/bindings/dma/fsl,elo3-dma.yaml | 105 +++++++++++
> > > > .../devicetree/bindings/dma/fsl,eloplus-dma.yaml | 120 ++++++++++++
> > > > .../devicetree/bindings/powerpc/fsl/dma.txt | 204 ---------------------
> > > > 4 files changed, 354 insertions(+), 204 deletions(-)
> > [...]
> > > > +patternProperties:
> > > > + "^dma-channel@.*$":
> > > > + type: object
> > >
> > > additionalProperties: false
> >
> > I'll add it.
> >
> > > (The tools should have highlighted this)
> >
> > With dtschema 2024.11 installed, "make dt_binding_check
> > DT_SCHEMA_FILES=fsl,elo-dma.yaml" does not highlight this.
>
> Actually, it's the top-level 'addtionalProperties: true' that disables
> the check here. That should be false as well.
Noted. This did indeed help me find more errors.
Best regards,
J. Neuschäfer
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 5/9] dt-bindings: dma: Convert fsl,elo*-dma bindings to YAML
2025-01-26 18:59 ` [PATCH 5/9] dt-bindings: dma: Convert fsl,elo*-dma bindings " J. Neuschäfer via B4 Relay
2025-01-27 4:47 ` Rob Herring
@ 2025-01-29 22:52 ` Frank Li
2025-02-04 21:47 ` J. Neuschäfer
1 sibling, 1 reply; 41+ messages in thread
From: Frank Li @ 2025-01-29 22:52 UTC (permalink / raw)
To: J. Neuschäfer
Cc: devicetree, linuxppc-dev, Scott Wood, Madhavan Srinivasan,
Michael Ellerman, Nicholas Piggin, Christophe Leroy, Naveen N Rao,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Damien Le Moal,
Niklas Cassel, Herbert Xu, David S. Miller, Lee Jones, Vinod Koul,
Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Bjorn Helgaas, J. Neuschäfer,
Wim Van Sebroeck, Guenter Roeck, Mark Brown, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-kernel, linux-ide,
linux-crypto, dmaengine, linux-pci, linux-watchdog, linux-spi,
linux-mtd
On Sun, Jan 26, 2025 at 07:59:00PM +0100, J. Neuschäfer wrote:
> The devicetree bindings for Freescale DMA engines have so far existed as
> a text file. This patch converts them to YAML, and specifies all the
> compatible strings currently in use in arch/powerpc/boot/dts.
>
> Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
> ---
> .../devicetree/bindings/dma/fsl,elo-dma.yaml | 129 +++++++++++++
> .../devicetree/bindings/dma/fsl,elo3-dma.yaml | 105 +++++++++++
> .../devicetree/bindings/dma/fsl,eloplus-dma.yaml | 120 ++++++++++++
> .../devicetree/bindings/powerpc/fsl/dma.txt | 204 ---------------------
> 4 files changed, 354 insertions(+), 204 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/dma/fsl,elo-dma.yaml b/Documentation/devicetree/bindings/dma/fsl,elo-dma.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..d1f4978a672c1217c322c27f243470b2de8c99d4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/fsl,elo-dma.yaml
> @@ -0,0 +1,129 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/dma/fsl,elo-dma.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale Elo DMA Controller
> +
> +maintainers:
> + - J. Neuschäfer <j.ne@posteo.net>
> +
> +description: |
needn't | here
> + This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
> + series chips such as mpc8315, mpc8349, mpc8379 etc.
> +
> + Note on DMA channel compatible properties: The compatible property must say
> + "fsl,elo-dma-channel" or "fsl,eloplus-dma-channel" to be used by the Elo DMA
There are not 'fsl,eloplus-dma-channel' under "^dma-channel@.*$". I suggest
remove this because 'compatible': items already show such information.
> + driver (fsldma). Any DMA channel used by fsldma cannot be used by another
> + DMA driver, such as the SSI sound drivers for the MPC8610. Therefore, any
> + DMA channel that should be used for another driver should not use
> + "fsl,elo-dma-channel" or "fsl,eloplus-dma-channel". For the SSI drivers, for
> + example, the compatible property should be "fsl,ssi-dma-channel". See
> + ssi.txt for more information.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - fsl,mpc8313-dma
> + - fsl,mpc8315-dma
> + - fsl,mpc8323-dma
> + - fsl,mpc8347-dma
> + - fsl,mpc8349-dma
> + - fsl,mpc8360-dma
> + - fsl,mpc8377-dma
> + - fsl,mpc8378-dma
> + - fsl,mpc8379-dma
> + - const: fsl,elo-dma
> +
> + reg:
> + maxItems: 1
> + description:
> + DMA General Status Register, i.e. DGSR which contains status for
> + all the 4 DMA channels.
> +
> + ranges: true
> +
> + cell-index:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: Controller index. 0 for controller @ 0x8100.
> +
> + interrupts:
> + maxItems: 1
> +
> +patternProperties:
> + "^dma-channel@.*$":
> + type: object
> +
> + properties:
> + compatible:
> + items:
> + - enum:
> + - fsl,mpc8315-dma-channel
> + - fsl,mpc8323-dma-channel
> + - fsl,mpc8347-dma-channel
> + - fsl,mpc8349-dma-channel
> + - fsl,mpc8360-dma-channel
> + - fsl,mpc8377-dma-channel
> + - fsl,mpc8378-dma-channel
> + - fsl,mpc8379-dma-channel
> + - const: fsl,elo-dma-channel
> +
> + reg:
> + maxItems: 1
> +
> + cell-index:
> + description: DMA channel index starts at 0.
> +
> + interrupts: true
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> +
> +additionalProperties: true
> +
> +examples:
> + - |
> + dma@82a8 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
> + reg = <0x82a8 4>;
compatible and reg should be first two property.
> + ranges = <0 0x8100 0x1a4>;
> + interrupt-parent = <&ipic>;
> + interrupts = <71 8>;
> + cell-index = <0>;
need space line here.
> + dma-channel@0 {
> + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
> + cell-index = <0>;
> + reg = <0 0x80>;
> + interrupt-parent = <&ipic>;
> + interrupts = <71 8>;
> + };
need space line here. check other's example dts
> + dma-channel@80 {
> + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
> + cell-index = <1>;
> + reg = <0x80 0x80>;
> + interrupt-parent = <&ipic>;
> + interrupts = <71 8>;
> + };
> + dma-channel@100 {
> + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
> + cell-index = <2>;
> + reg = <0x100 0x80>;
> + interrupt-parent = <&ipic>;
> + interrupts = <71 8>;
> + };
> + dma-channel@180 {
> + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
> + cell-index = <3>;
> + reg = <0x180 0x80>;
> + interrupt-parent = <&ipic>;
> + interrupts = <71 8>;
> + };
> + };
> +
> +...
> diff --git a/Documentation/devicetree/bindings/dma/fsl,elo3-dma.yaml b/Documentation/devicetree/bindings/dma/fsl,elo3-dma.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..d4853ffd40dc75c7fcdc0dfb15e497ec56f3e1ba
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/fsl,elo3-dma.yaml
> @@ -0,0 +1,105 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/dma/fsl,elo3-dma.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale Elo3 DMA Controller
> +
> +maintainers:
> + - J. Neuschäfer <j.ne@posteo.net>
> +
> +description: |
> + DMA controller which has same function as EloPlus except that Elo3 has 8
> + channels while EloPlus has only 4, it is used in Freescale Txxx and Bxxx
> + series chips, such as t1040, t4240, b4860.
> +
> + Note on DMA channel compatible properties: The compatible property must say
> + "fsl,elo-dma-channel" or "fsl,eloplus-dma-channel" to be used by the Elo DMA
> + driver (fsldma). Any DMA channel used by fsldma cannot be used by another
> + DMA driver, such as the SSI sound drivers for the MPC8610. Therefore, any DMA
> + channel that should be used for another driver should not use
> + "fsl,elo-dma-channel" or "fsl,eloplus-dma-channel". For the SSI drivers, for
> + example, the compatible property should be "fsl,ssi-dma-channel". See ssi.txt
> + for more information.
> +
> +properties:
> + compatible:
> + const: fsl,elo3-dma
> +
> + reg:
> + maxItems: 2
> + description: |
> + contains two entries for DMA General Status Registers, i.e. DGSR0 which
> + includes status for channel 1~4, and DGSR1 for channel 5~8
> +
> + interrupts:
> + maxItems: 1
> +
> +patternProperties:
> + "^dma-channel@.*$":
> + type: object
> +
> + properties:
> + compatible:
> + const: fsl,eloplus-dma-channel
> +
> + reg:
> + maxItems: 1
> +
> + interrupts: true
> +
> +examples:
> + - |
> + dma@100300 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "fsl,elo3-dma";
> + reg = <0x100300 0x4>,
> + <0x100600 0x4>;
> + ranges = <0x0 0x100100 0x500>;
> + dma-channel@0 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x0 0x80>;
> + interrupts = <28 2 0 0>;
> + };
> + dma-channel@80 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x80 0x80>;
> + interrupts = <29 2 0 0>;
> + };
> + dma-channel@100 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x100 0x80>;
> + interrupts = <30 2 0 0>;
> + };
> + dma-channel@180 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x180 0x80>;
> + interrupts = <31 2 0 0>;
> + };
> + dma-channel@300 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x300 0x80>;
> + interrupts = <76 2 0 0>;
> + };
> + dma-channel@380 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x380 0x80>;
> + interrupts = <77 2 0 0>;
> + };
> + dma-channel@400 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x400 0x80>;
> + interrupts = <78 2 0 0>;
> + };
> + dma-channel@480 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x480 0x80>;
> + interrupts = <79 2 0 0>;
> + };
> + };
> +
> +additionalProperties: true
> +
> +...
> diff --git a/Documentation/devicetree/bindings/dma/fsl,eloplus-dma.yaml b/Documentation/devicetree/bindings/dma/fsl,eloplus-dma.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..680d64332ddf4d6d68ee8c607ac71211a7e19e6e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/fsl,eloplus-dma.yaml
> @@ -0,0 +1,120 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/dma/fsl,eloplus-dma.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale EloPlus DMA Controller
> +
> +maintainers:
> + - J. Neuschäfer <j.ne@posteo.net>
> +
> +description: |
> + This is a 4-channel DMA controller with extended addresses and chaining,
> + mainly used in Freescale mpc85xx/86xx, Pxxx and BSC series chips, such as
> + mpc8540, mpc8641 p4080, bsc9131 etc.
> +
> + Note on DMA channel compatible properties: The compatible property must say
> + "fsl,elo-dma-channel" or "fsl,eloplus-dma-channel" to be used by the Elo DMA
> + driver (fsldma). Any DMA channel used by fsldma cannot be used by another
> + DMA driver, such as the SSI sound drivers for the MPC8610. Therefore, any DMA
> + channel that should be used for another driver should not use
> + "fsl,elo-dma-channel" or "fsl,eloplus-dma-channel". For the SSI drivers, for
> + example, the compatible property should be "fsl,ssi-dma-channel". See ssi.txt
> + for more information.
> +
> +properties:
> + compatible:
> + oneOf:
> + - items:
> + - enum:
> + - fsl,mpc8540-dma
> + - fsl,mpc8541-dma
> + - fsl,mpc8548-dma
> + - fsl,mpc8555-dma
> + - fsl,mpc8560-dma
> + - fsl,mpc8572-dma
> + - fsl,mpc8641-dma
> + - const: fsl,eloplus-dma
> + - const: fsl,eloplus-dma
> +
> + reg:
> + maxItems: 1
> + description:
> + DMA General Status Register, i.e. DGSR which contains
> + status for all the 4 DMA channels
> +
> + cell-index:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: |
> + controller index. 0 for controller @ 0x21000, 1 for controller @ 0xc000
> +
> + interrupts:
> + maxItems: 1
> +
> +patternProperties:
> + "^dma-channel@.*$":
> + type: object
> +
> + properties:
> + compatible:
> + items:
> + - enum:
> + - fsl,mpc8540-dma-channel
> + - fsl,mpc8541-dma-channel
> + - fsl,mpc8548-dma-channel
> + - fsl,mpc8555-dma-channel
> + - fsl,mpc8560-dma-channel
> + - fsl,mpc8572-dma-channel
> + - const: fsl,eloplus-dma-channel
I think you can merge this fsl,mpc83xx-dma yaml file
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: fsl,elo-dma
+ then:
+ patternProperties:
+ "^dma-channel@.*$":
+ properties:
+ compatible:
+ items:
+ - enum:
....
+ else
+ patternProperties:
+ "^dma-channel@.*$":
+ properties:
+ compatible:
+ items:
+ - enum:
....
+ - const: fsl,eloplus-dma-channel
Frank
> +
> + reg:
> + maxItems: 1
> +
> + cell-index:
> + description: DMA channel index starts at 0.
> +
> + interrupts: true
> +
> +examples:
> + - |
> + dma@21300 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
> + reg = <0x21300 4>;
> + ranges = <0 0x21100 0x200>;
> + cell-index = <0>;
> + dma-channel@0 {
> + compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
> + reg = <0 0x80>;
> + cell-index = <0>;
> + interrupt-parent = <&mpic>;
> + interrupts = <20 2>;
> + };
> + dma-channel@80 {
> + compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
> + reg = <0x80 0x80>;
> + cell-index = <1>;
> + interrupt-parent = <&mpic>;
> + interrupts = <21 2>;
> + };
> + dma-channel@100 {
> + compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
> + reg = <0x100 0x80>;
> + cell-index = <2>;
> + interrupt-parent = <&mpic>;
> + interrupts = <22 2>;
> + };
> + dma-channel@180 {
> + compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
> + reg = <0x180 0x80>;
> + cell-index = <3>;
> + interrupt-parent = <&mpic>;
> + interrupts = <23 2>;
> + };
> + };
> +
> +additionalProperties: true
> +
> +...
> diff --git a/Documentation/devicetree/bindings/powerpc/fsl/dma.txt b/Documentation/devicetree/bindings/powerpc/fsl/dma.txt
> deleted file mode 100644
> index c11ad5c6db2190bf38c160632d9997122e169945..0000000000000000000000000000000000000000
> --- a/Documentation/devicetree/bindings/powerpc/fsl/dma.txt
> +++ /dev/null
> @@ -1,204 +0,0 @@
> -* Freescale DMA Controllers
> -
> -** Freescale Elo DMA Controller
> - This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
> - series chips such as mpc8315, mpc8349, mpc8379 etc.
> -
> -Required properties:
> -
> -- compatible : must include "fsl,elo-dma"
> -- reg : DMA General Status Register, i.e. DGSR which contains
> - status for all the 4 DMA channels
> -- ranges : describes the mapping between the address space of the
> - DMA channels and the address space of the DMA controller
> -- cell-index : controller index. 0 for controller @ 0x8100
> -- interrupts : interrupt specifier for DMA IRQ
> -
> -- DMA channel nodes:
> - - compatible : must include "fsl,elo-dma-channel"
> - However, see note below.
> - - reg : DMA channel specific registers
> - - cell-index : DMA channel index starts at 0.
> -
> -Optional properties:
> - - interrupts : interrupt specifier for DMA channel IRQ
> - (on 83xx this is expected to be identical to
> - the interrupts property of the parent node)
> -
> -Example:
> - dma@82a8 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
> - reg = <0x82a8 4>;
> - ranges = <0 0x8100 0x1a4>;
> - interrupt-parent = <&ipic>;
> - interrupts = <71 8>;
> - cell-index = <0>;
> - dma-channel@0 {
> - compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
> - cell-index = <0>;
> - reg = <0 0x80>;
> - interrupt-parent = <&ipic>;
> - interrupts = <71 8>;
> - };
> - dma-channel@80 {
> - compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
> - cell-index = <1>;
> - reg = <0x80 0x80>;
> - interrupt-parent = <&ipic>;
> - interrupts = <71 8>;
> - };
> - dma-channel@100 {
> - compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
> - cell-index = <2>;
> - reg = <0x100 0x80>;
> - interrupt-parent = <&ipic>;
> - interrupts = <71 8>;
> - };
> - dma-channel@180 {
> - compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
> - cell-index = <3>;
> - reg = <0x180 0x80>;
> - interrupt-parent = <&ipic>;
> - interrupts = <71 8>;
> - };
> - };
> -
> -** Freescale EloPlus DMA Controller
> - This is a 4-channel DMA controller with extended addresses and chaining,
> - mainly used in Freescale mpc85xx/86xx, Pxxx and BSC series chips, such as
> - mpc8540, mpc8641 p4080, bsc9131 etc.
> -
> -Required properties:
> -
> -- compatible : must include "fsl,eloplus-dma"
> -- reg : DMA General Status Register, i.e. DGSR which contains
> - status for all the 4 DMA channels
> -- cell-index : controller index. 0 for controller @ 0x21000,
> - 1 for controller @ 0xc000
> -- ranges : describes the mapping between the address space of the
> - DMA channels and the address space of the DMA controller
> -
> -- DMA channel nodes:
> - - compatible : must include "fsl,eloplus-dma-channel"
> - However, see note below.
> - - cell-index : DMA channel index starts at 0.
> - - reg : DMA channel specific registers
> - - interrupts : interrupt specifier for DMA channel IRQ
> -
> -Example:
> - dma@21300 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
> - reg = <0x21300 4>;
> - ranges = <0 0x21100 0x200>;
> - cell-index = <0>;
> - dma-channel@0 {
> - compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
> - reg = <0 0x80>;
> - cell-index = <0>;
> - interrupt-parent = <&mpic>;
> - interrupts = <20 2>;
> - };
> - dma-channel@80 {
> - compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
> - reg = <0x80 0x80>;
> - cell-index = <1>;
> - interrupt-parent = <&mpic>;
> - interrupts = <21 2>;
> - };
> - dma-channel@100 {
> - compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
> - reg = <0x100 0x80>;
> - cell-index = <2>;
> - interrupt-parent = <&mpic>;
> - interrupts = <22 2>;
> - };
> - dma-channel@180 {
> - compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
> - reg = <0x180 0x80>;
> - cell-index = <3>;
> - interrupt-parent = <&mpic>;
> - interrupts = <23 2>;
> - };
> - };
> -
> -** Freescale Elo3 DMA Controller
> - DMA controller which has same function as EloPlus except that Elo3 has 8
> - channels while EloPlus has only 4, it is used in Freescale Txxx and Bxxx
> - series chips, such as t1040, t4240, b4860.
> -
> -Required properties:
> -
> -- compatible : must include "fsl,elo3-dma"
> -- reg : contains two entries for DMA General Status Registers,
> - i.e. DGSR0 which includes status for channel 1~4, and
> - DGSR1 for channel 5~8
> -- ranges : describes the mapping between the address space of the
> - DMA channels and the address space of the DMA controller
> -
> -- DMA channel nodes:
> - - compatible : must include "fsl,eloplus-dma-channel"
> - - reg : DMA channel specific registers
> - - interrupts : interrupt specifier for DMA channel IRQ
> -
> -Example:
> -dma@100300 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - compatible = "fsl,elo3-dma";
> - reg = <0x100300 0x4>,
> - <0x100600 0x4>;
> - ranges = <0x0 0x100100 0x500>;
> - dma-channel@0 {
> - compatible = "fsl,eloplus-dma-channel";
> - reg = <0x0 0x80>;
> - interrupts = <28 2 0 0>;
> - };
> - dma-channel@80 {
> - compatible = "fsl,eloplus-dma-channel";
> - reg = <0x80 0x80>;
> - interrupts = <29 2 0 0>;
> - };
> - dma-channel@100 {
> - compatible = "fsl,eloplus-dma-channel";
> - reg = <0x100 0x80>;
> - interrupts = <30 2 0 0>;
> - };
> - dma-channel@180 {
> - compatible = "fsl,eloplus-dma-channel";
> - reg = <0x180 0x80>;
> - interrupts = <31 2 0 0>;
> - };
> - dma-channel@300 {
> - compatible = "fsl,eloplus-dma-channel";
> - reg = <0x300 0x80>;
> - interrupts = <76 2 0 0>;
> - };
> - dma-channel@380 {
> - compatible = "fsl,eloplus-dma-channel";
> - reg = <0x380 0x80>;
> - interrupts = <77 2 0 0>;
> - };
> - dma-channel@400 {
> - compatible = "fsl,eloplus-dma-channel";
> - reg = <0x400 0x80>;
> - interrupts = <78 2 0 0>;
> - };
> - dma-channel@480 {
> - compatible = "fsl,eloplus-dma-channel";
> - reg = <0x480 0x80>;
> - interrupts = <79 2 0 0>;
> - };
> -};
> -
> -Note on DMA channel compatible properties: The compatible property must say
> -"fsl,elo-dma-channel" or "fsl,eloplus-dma-channel" to be used by the Elo DMA
> -driver (fsldma). Any DMA channel used by fsldma cannot be used by another
> -DMA driver, such as the SSI sound drivers for the MPC8610. Therefore, any DMA
> -channel that should be used for another driver should not use
> -"fsl,elo-dma-channel" or "fsl,eloplus-dma-channel". For the SSI drivers, for
> -example, the compatible property should be "fsl,ssi-dma-channel". See ssi.txt
> -for more information.
>
> --
> 2.48.0.rc1.219.gb6b6757d772
>
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH 5/9] dt-bindings: dma: Convert fsl,elo*-dma bindings to YAML
2025-01-29 22:52 ` Frank Li
@ 2025-02-04 21:47 ` J. Neuschäfer
0 siblings, 0 replies; 41+ messages in thread
From: J. Neuschäfer @ 2025-02-04 21:47 UTC (permalink / raw)
To: Frank Li
Cc: J. Neuschäfer, devicetree, linuxppc-dev, Scott Wood,
Madhavan Srinivasan, Michael Ellerman, Nicholas Piggin,
Christophe Leroy, Naveen N Rao, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Damien Le Moal, Niklas Cassel, Herbert Xu,
David S. Miller, Lee Jones, Vinod Koul, Lorenzo Pieralisi,
Krzysztof Wilczyński, Manivannan Sadhasivam, Bjorn Helgaas,
J. Neuschäfer, Wim Van Sebroeck, Guenter Roeck, Mark Brown,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-kernel, linux-ide, linux-crypto, dmaengine, linux-pci,
linux-watchdog, linux-spi, linux-mtd
On Wed, Jan 29, 2025 at 05:52:31PM -0500, Frank Li wrote:
> On Sun, Jan 26, 2025 at 07:59:00PM +0100, J. Neuschäfer wrote:
> > The devicetree bindings for Freescale DMA engines have so far existed as
> > a text file. This patch converts them to YAML, and specifies all the
> > compatible strings currently in use in arch/powerpc/boot/dts.
> >
> > Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
> > ---
> > .../devicetree/bindings/dma/fsl,elo-dma.yaml | 129 +++++++++++++
> > .../devicetree/bindings/dma/fsl,elo3-dma.yaml | 105 +++++++++++
> > .../devicetree/bindings/dma/fsl,eloplus-dma.yaml | 120 ++++++++++++
> > .../devicetree/bindings/powerpc/fsl/dma.txt | 204 ---------------------
> > 4 files changed, 354 insertions(+), 204 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/dma/fsl,elo-dma.yaml b/Documentation/devicetree/bindings/dma/fsl,elo-dma.yaml
> > new file mode 100644
> > index 0000000000000000000000000000000000000000..d1f4978a672c1217c322c27f243470b2de8c99d4
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/dma/fsl,elo-dma.yaml
> > @@ -0,0 +1,129 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/dma/fsl,elo-dma.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Freescale Elo DMA Controller
> > +
> > +maintainers:
> > + - J. Neuschäfer <j.ne@posteo.net>
> > +
> > +description: |
>
> needn't | here
Will remove.
>
> > + This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
> > + series chips such as mpc8315, mpc8349, mpc8379 etc.
> > +
> > + Note on DMA channel compatible properties: The compatible property must say
> > + "fsl,elo-dma-channel" or "fsl,eloplus-dma-channel" to be used by the Elo DMA
>
> There are not 'fsl,eloplus-dma-channel' under "^dma-channel@.*$". I suggest
> remove this because 'compatible': items already show such information.
Good point, I'll trim this text down.
> > + driver (fsldma). Any DMA channel used by fsldma cannot be used by another
> > + DMA driver, such as the SSI sound drivers for the MPC8610. Therefore, any
> > + DMA channel that should be used for another driver should not use
> > + "fsl,elo-dma-channel" or "fsl,eloplus-dma-channel". For the SSI drivers, for
> > + example, the compatible property should be "fsl,ssi-dma-channel". See
> > + ssi.txt for more information.
I noticed fsl,ssi.txt has been converted to YAML since this text was
originally written, so I'll make reference to that.
[...]
> > +examples:
> > + - |
> > + dma@82a8 {
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
> > + reg = <0x82a8 4>;
>
> compatible and reg should be first two property.
Will fix.
>
> > + ranges = <0 0x8100 0x1a4>;
> > + interrupt-parent = <&ipic>;
> > + interrupts = <71 8>;
> > + cell-index = <0>;
>
> need space line here.
Will fix.
> > + dma-channel@0 {
> > + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
> > + cell-index = <0>;
> > + reg = <0 0x80>;
> > + interrupt-parent = <&ipic>;
> > + interrupts = <71 8>;
> > + };
>
> need space line here. check other's example dts
Will fix in all files.
[...]
> > +patternProperties:
> > + "^dma-channel@.*$":
> > + type: object
> > +
> > + properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - fsl,mpc8540-dma-channel
> > + - fsl,mpc8541-dma-channel
> > + - fsl,mpc8548-dma-channel
> > + - fsl,mpc8555-dma-channel
> > + - fsl,mpc8560-dma-channel
> > + - fsl,mpc8572-dma-channel
> > + - const: fsl,eloplus-dma-channel
>
> I think you can merge this fsl,mpc83xx-dma yaml file
>
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: fsl,elo-dma
> + then:
> + patternProperties:
> + "^dma-channel@.*$":
> + properties:
> + compatible:
> + items:
> + - enum:
> ....
> + else
> + patternProperties:
> + "^dma-channel@.*$":
> + properties:
> + compatible:
> + items:
> + - enum:
> ....
> + - const: fsl,eloplus-dma-channel
I suppose that works, but I'm not entirely convinced it would help with
readability, compared to leaving the three variants separate.
Thank you for your review!
Best regards,
J. Neuschäfer
^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH 6/9] dt-bindings: pci: Add fsl,mpc83xx-pcie bindings
2025-01-26 18:58 [PATCH 0/9] YAML conversion of several Freescale/PowerPC DT bindings J. Neuschäfer via B4 Relay
` (4 preceding siblings ...)
2025-01-26 18:59 ` [PATCH 5/9] dt-bindings: dma: Convert fsl,elo*-dma bindings " J. Neuschäfer via B4 Relay
@ 2025-01-26 18:59 ` J. Neuschäfer via B4 Relay
2025-01-27 4:50 ` Rob Herring
2025-01-29 22:55 ` Frank Li
2025-01-26 18:59 ` [PATCH 7/9] dt-bindings: watchdog: Convert mpc8xxx-wdt binding to YAML J. Neuschäfer via B4 Relay
` (3 subsequent siblings)
9 siblings, 2 replies; 41+ messages in thread
From: J. Neuschäfer via B4 Relay @ 2025-01-26 18:59 UTC (permalink / raw)
To: devicetree, linuxppc-dev
Cc: Scott Wood, Madhavan Srinivasan, Michael Ellerman,
Nicholas Piggin, Christophe Leroy, Naveen N Rao, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Damien Le Moal, Niklas Cassel,
Herbert Xu, David S. Miller, Lee Jones, Vinod Koul,
Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Bjorn Helgaas, J. Neuschäfer,
Wim Van Sebroeck, Guenter Roeck, Mark Brown, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-kernel, linux-ide,
linux-crypto, dmaengine, linux-pci, linux-watchdog, linux-spi,
linux-mtd, J. Neuschäfer
From: "J. Neuschäfer" <j.ne@posteo.net>
Supplement Documentation/devicetree/bindings/pci/fsl,pci.txt with a more
formal binding in YAML format.
Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
---
.../devicetree/bindings/pci/fsl,mpc8xxx-pci.yaml | 83 ++++++++++++++++++++++
1 file changed, 83 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/fsl,mpc8xxx-pci.yaml b/Documentation/devicetree/bindings/pci/fsl,mpc8xxx-pci.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..12e86a9c20dfe2362d11f085bd9ae47238c4a37f
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/fsl,mpc8xxx-pci.yaml
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+
+$id: http://devicetree.org/schemas/pci/fsl,mpc8xxx-pci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale MPC83xx PCI/PCI-X/PCIe controllers
+
+description: |
+ Binding for the PCI/PCI-X/PCIe host bridges on MPC8xxx SoCs.
+ See also: Documentation/devicetree/bindings/pci/fsl,pci.txt
+
+maintainers:
+ - J. Neuschäfer <j.neuschaefer@gmx.net>
+
+allOf:
+ - $ref: /schemas/pci/pci-host-bridge.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - fsl,mpc8308-pcie
+ - fsl,mpc8315-pcie
+ - fsl,mpc8377-pcie
+ - fsl,mpc8378-pcie
+ - const: fsl,mpc8314-pcie
+ - const: fsl,mpc8314-pcie
+ - items:
+ - const: fsl,mpc8360-pci
+ - const: fsl,mpc8349-pci
+ - const: fsl,mpc8349-pci
+ - items:
+ - const: fsl,mpc8540-pcix
+ - const: fsl,mpc8540-pci
+ - const: fsl,mpc8540-pci
+ - items:
+ - const: fsl,mpc8540-pcix
+ - const: fsl,mpc8540-pci
+ - const: fsl,mpc8548-pcie
+ - const: fsl,mpc8548-pcie
+ - const: fsl,mpc8641-pcie
+
+ reg:
+ minItems: 1
+ items:
+ - description: internal registers
+ - description: config space access registers
+
+ clock-frequency:
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+required:
+ - reg
+ - compatible
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ pci1: pcie@e0009000 {
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie";
+ reg = <0xe0009000 0x00001000>;
+ ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
+ 0x01000000 0 0x00000000 0xb1000000 0 0x00800000>;
+ bus-range = <0 255>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <0 0 0 1 &ipic 1 IRQ_TYPE_LEVEL_LOW
+ 0 0 0 2 &ipic 1 IRQ_TYPE_LEVEL_LOW
+ 0 0 0 3 &ipic 1 IRQ_TYPE_LEVEL_LOW
+ 0 0 0 4 &ipic 1 IRQ_TYPE_LEVEL_LOW>;
+ clock-frequency = <0>;
+ };
+
+...
--
2.48.0.rc1.219.gb6b6757d772
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [PATCH 6/9] dt-bindings: pci: Add fsl,mpc83xx-pcie bindings
2025-01-26 18:59 ` [PATCH 6/9] dt-bindings: pci: Add fsl,mpc83xx-pcie bindings J. Neuschäfer via B4 Relay
@ 2025-01-27 4:50 ` Rob Herring
2025-02-04 23:31 ` J. Neuschäfer
2025-01-29 22:55 ` Frank Li
1 sibling, 1 reply; 41+ messages in thread
From: Rob Herring @ 2025-01-27 4:50 UTC (permalink / raw)
To: J. Neuschäfer
Cc: devicetree, linuxppc-dev, Scott Wood, Madhavan Srinivasan,
Michael Ellerman, Nicholas Piggin, Christophe Leroy, Naveen N Rao,
Krzysztof Kozlowski, Conor Dooley, Damien Le Moal, Niklas Cassel,
Herbert Xu, David S. Miller, Lee Jones, Vinod Koul,
Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Bjorn Helgaas, J. Neuschäfer,
Wim Van Sebroeck, Guenter Roeck, Mark Brown, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-kernel, linux-ide,
linux-crypto, dmaengine, linux-pci, linux-watchdog, linux-spi,
linux-mtd
On Sun, Jan 26, 2025 at 07:59:01PM +0100, J. Neuschäfer wrote:
> Supplement Documentation/devicetree/bindings/pci/fsl,pci.txt with a more
> formal binding in YAML format.
>
> Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
> ---
> .../devicetree/bindings/pci/fsl,mpc8xxx-pci.yaml | 83 ++++++++++++++++++++++
> 1 file changed, 83 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/fsl,mpc8xxx-pci.yaml b/Documentation/devicetree/bindings/pci/fsl,mpc8xxx-pci.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..12e86a9c20dfe2362d11f085bd9ae47238c4a37f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/fsl,mpc8xxx-pci.yaml
> @@ -0,0 +1,83 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +
> +$id: http://devicetree.org/schemas/pci/fsl,mpc8xxx-pci.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale MPC83xx PCI/PCI-X/PCIe controllers
> +
> +description: |
> + Binding for the PCI/PCI-X/PCIe host bridges on MPC8xxx SoCs.
> + See also: Documentation/devicetree/bindings/pci/fsl,pci.txt
Can you move that information here.
> +
> +maintainers:
> + - J. Neuschäfer <j.neuschaefer@gmx.net>
> +
> +allOf:
> + - $ref: /schemas/pci/pci-host-bridge.yaml#
> +
> +properties:
> + compatible:
> + oneOf:
> + - items:
> + - enum:
> + - fsl,mpc8308-pcie
> + - fsl,mpc8315-pcie
> + - fsl,mpc8377-pcie
> + - fsl,mpc8378-pcie
> + - const: fsl,mpc8314-pcie
> + - const: fsl,mpc8314-pcie
> + - items:
> + - const: fsl,mpc8360-pci
> + - const: fsl,mpc8349-pci
> + - const: fsl,mpc8349-pci
> + - items:
> + - const: fsl,mpc8540-pcix
> + - const: fsl,mpc8540-pci
> + - const: fsl,mpc8540-pci
> + - items:
> + - const: fsl,mpc8540-pcix
> + - const: fsl,mpc8540-pci
> + - const: fsl,mpc8548-pcie
> + - const: fsl,mpc8548-pcie
> + - const: fsl,mpc8641-pcie
Move all the single 'const' to 1 enum entry.
> +
> + reg:
> + minItems: 1
> + items:
> + - description: internal registers
> + - description: config space access registers
> +
> + clock-frequency:
> + $ref: /schemas/types.yaml#/definitions/uint32
Don't need a type for this.
> +
> +required:
> + - reg
> + - compatible
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/irq.h>
> +
> + pci1: pcie@e0009000 {
> + #address-cells = <3>;
> + #size-cells = <2>;
> + #interrupt-cells = <1>;
> + device_type = "pci";
> + compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie";
> + reg = <0xe0009000 0x00001000>;
> + ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
> + 0x01000000 0 0x00000000 0xb1000000 0 0x00800000>;
> + bus-range = <0 255>;
> + interrupt-map-mask = <0xf800 0 0 7>;
> + interrupt-map = <0 0 0 1 &ipic 1 IRQ_TYPE_LEVEL_LOW
> + 0 0 0 2 &ipic 1 IRQ_TYPE_LEVEL_LOW
> + 0 0 0 3 &ipic 1 IRQ_TYPE_LEVEL_LOW
> + 0 0 0 4 &ipic 1 IRQ_TYPE_LEVEL_LOW>;
> + clock-frequency = <0>;
> + };
> +
> +...
>
> --
> 2.48.0.rc1.219.gb6b6757d772
>
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH 6/9] dt-bindings: pci: Add fsl,mpc83xx-pcie bindings
2025-01-27 4:50 ` Rob Herring
@ 2025-02-04 23:31 ` J. Neuschäfer
0 siblings, 0 replies; 41+ messages in thread
From: J. Neuschäfer @ 2025-02-04 23:31 UTC (permalink / raw)
To: Rob Herring
Cc: J. Neuschäfer, devicetree, linuxppc-dev, Scott Wood,
Madhavan Srinivasan, Michael Ellerman, Nicholas Piggin,
Christophe Leroy, Naveen N Rao, Krzysztof Kozlowski, Conor Dooley,
Damien Le Moal, Niklas Cassel, Herbert Xu, David S. Miller,
Lee Jones, Vinod Koul, Lorenzo Pieralisi,
Krzysztof Wilczyński, Manivannan Sadhasivam, Bjorn Helgaas,
J. Neuschäfer, Wim Van Sebroeck, Guenter Roeck, Mark Brown,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-kernel, linux-ide, linux-crypto, dmaengine, linux-pci,
linux-watchdog, linux-spi, linux-mtd
On Sun, Jan 26, 2025 at 10:50:04PM -0600, Rob Herring wrote:
> On Sun, Jan 26, 2025 at 07:59:01PM +0100, J. Neuschäfer wrote:
> > Supplement Documentation/devicetree/bindings/pci/fsl,pci.txt with a more
> > formal binding in YAML format.
> >
> > Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
> > ---
[...]
> > +title: Freescale MPC83xx PCI/PCI-X/PCIe controllers
> > +
> > +description: |
> > + Binding for the PCI/PCI-X/PCIe host bridges on MPC8xxx SoCs.
> > + See also: Documentation/devicetree/bindings/pci/fsl,pci.txt
>
> Can you move that information here.
Will do.
>
> > +
> > +maintainers:
> > + - J. Neuschäfer <j.neuschaefer@gmx.net>
> > +
> > +allOf:
> > + - $ref: /schemas/pci/pci-host-bridge.yaml#
> > +
> > +properties:
> > + compatible:
> > + oneOf:
> > + - items:
> > + - enum:
> > + - fsl,mpc8308-pcie
> > + - fsl,mpc8315-pcie
> > + - fsl,mpc8377-pcie
> > + - fsl,mpc8378-pcie
> > + - const: fsl,mpc8314-pcie
> > + - const: fsl,mpc8314-pcie
> > + - items:
> > + - const: fsl,mpc8360-pci
> > + - const: fsl,mpc8349-pci
> > + - const: fsl,mpc8349-pci
> > + - items:
> > + - const: fsl,mpc8540-pcix
> > + - const: fsl,mpc8540-pci
> > + - const: fsl,mpc8540-pci
> > + - items:
> > + - const: fsl,mpc8540-pcix
> > + - const: fsl,mpc8540-pci
> > + - const: fsl,mpc8548-pcie
> > + - const: fsl,mpc8548-pcie
> > + - const: fsl,mpc8641-pcie
>
> Move all the single 'const' to 1 enum entry.
Will do
> > +
> > + reg:
> > + minItems: 1
> > + items:
> > + - description: internal registers
> > + - description: config space access registers
> > +
> > + clock-frequency:
> > + $ref: /schemas/types.yaml#/definitions/uint32
>
> Don't need a type for this.
Will change.
Thanks,
J. Neuschäfer
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 6/9] dt-bindings: pci: Add fsl,mpc83xx-pcie bindings
2025-01-26 18:59 ` [PATCH 6/9] dt-bindings: pci: Add fsl,mpc83xx-pcie bindings J. Neuschäfer via B4 Relay
2025-01-27 4:50 ` Rob Herring
@ 2025-01-29 22:55 ` Frank Li
2025-02-04 23:34 ` J. Neuschäfer
1 sibling, 1 reply; 41+ messages in thread
From: Frank Li @ 2025-01-29 22:55 UTC (permalink / raw)
To: J. Neuschäfer
Cc: devicetree, linuxppc-dev, Scott Wood, Madhavan Srinivasan,
Michael Ellerman, Nicholas Piggin, Christophe Leroy, Naveen N Rao,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Damien Le Moal,
Niklas Cassel, Herbert Xu, David S. Miller, Lee Jones, Vinod Koul,
Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Bjorn Helgaas, J. Neuschäfer,
Wim Van Sebroeck, Guenter Roeck, Mark Brown, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-kernel, linux-ide,
linux-crypto, dmaengine, linux-pci, linux-watchdog, linux-spi,
linux-mtd
On Sun, Jan 26, 2025 at 07:59:01PM +0100, J. Neuschäfer wrote:
> Supplement Documentation/devicetree/bindings/pci/fsl,pci.txt with a more
> formal binding in YAML format.
>
> Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
> ---
> .../devicetree/bindings/pci/fsl,mpc8xxx-pci.yaml | 83 ++++++++++++++++++++++
> 1 file changed, 83 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/fsl,mpc8xxx-pci.yaml b/Documentation/devicetree/bindings/pci/fsl,mpc8xxx-pci.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..12e86a9c20dfe2362d11f085bd9ae47238c4a37f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/fsl,mpc8xxx-pci.yaml
> @@ -0,0 +1,83 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +
> +$id: http://devicetree.org/schemas/pci/fsl,mpc8xxx-pci.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale MPC83xx PCI/PCI-X/PCIe controllers
> +
> +description: |
> + Binding for the PCI/PCI-X/PCIe host bridges on MPC8xxx SoCs.
> + See also: Documentation/devicetree/bindings/pci/fsl,pci.txt
> +
> +maintainers:
> + - J. Neuschäfer <j.neuschaefer@gmx.net>
> +
> +allOf:
> + - $ref: /schemas/pci/pci-host-bridge.yaml#
> +
> +properties:
> + compatible:
> + oneOf:
> + - items:
> + - enum:
> + - fsl,mpc8308-pcie
> + - fsl,mpc8315-pcie
> + - fsl,mpc8377-pcie
> + - fsl,mpc8378-pcie
> + - const: fsl,mpc8314-pcie
> + - const: fsl,mpc8314-pcie
> + - items:
> + - const: fsl,mpc8360-pci
> + - const: fsl,mpc8349-pci
> + - const: fsl,mpc8349-pci
> + - items:
> + - const: fsl,mpc8540-pcix
> + - const: fsl,mpc8540-pci
> + - const: fsl,mpc8540-pci
> + - items:
> + - const: fsl,mpc8540-pcix
> + - const: fsl,mpc8540-pci
> + - const: fsl,mpc8548-pcie
> + - const: fsl,mpc8548-pcie
> + - const: fsl,mpc8641-pcie
> +
> + reg:
> + minItems: 1
> + items:
> + - description: internal registers
> + - description: config space access registers
> +
> + clock-frequency:
> + $ref: /schemas/types.yaml#/definitions/uint32
> +
> +required:
> + - reg
> + - compatible
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/irq.h>
> +
> + pci1: pcie@e0009000 {
needn't label here
Frank
> + #address-cells = <3>;
> + #size-cells = <2>;
> + #interrupt-cells = <1>;
> + device_type = "pci";
> + compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie";
> + reg = <0xe0009000 0x00001000>;
> + ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
> + 0x01000000 0 0x00000000 0xb1000000 0 0x00800000>;
> + bus-range = <0 255>;
> + interrupt-map-mask = <0xf800 0 0 7>;
> + interrupt-map = <0 0 0 1 &ipic 1 IRQ_TYPE_LEVEL_LOW
> + 0 0 0 2 &ipic 1 IRQ_TYPE_LEVEL_LOW
> + 0 0 0 3 &ipic 1 IRQ_TYPE_LEVEL_LOW
> + 0 0 0 4 &ipic 1 IRQ_TYPE_LEVEL_LOW>;
> + clock-frequency = <0>;
> + };
> +
> +...
>
> --
> 2.48.0.rc1.219.gb6b6757d772
>
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH 6/9] dt-bindings: pci: Add fsl,mpc83xx-pcie bindings
2025-01-29 22:55 ` Frank Li
@ 2025-02-04 23:34 ` J. Neuschäfer
2025-02-06 12:42 ` Mukesh Kumar Savaliya
0 siblings, 1 reply; 41+ messages in thread
From: J. Neuschäfer @ 2025-02-04 23:34 UTC (permalink / raw)
To: Frank Li
Cc: J. Neuschäfer, devicetree, linuxppc-dev, Scott Wood,
Madhavan Srinivasan, Michael Ellerman, Nicholas Piggin,
Christophe Leroy, Naveen N Rao, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Damien Le Moal, Niklas Cassel, Herbert Xu,
David S. Miller, Lee Jones, Vinod Koul, Lorenzo Pieralisi,
Krzysztof Wilczyński, Manivannan Sadhasivam, Bjorn Helgaas,
J. Neuschäfer, Wim Van Sebroeck, Guenter Roeck, Mark Brown,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-kernel, linux-ide, linux-crypto, dmaengine, linux-pci,
linux-watchdog, linux-spi, linux-mtd
On Wed, Jan 29, 2025 at 05:55:26PM -0500, Frank Li wrote:
> On Sun, Jan 26, 2025 at 07:59:01PM +0100, J. Neuschäfer wrote:
> > Supplement Documentation/devicetree/bindings/pci/fsl,pci.txt with a more
> > formal binding in YAML format.
> >
> > Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
> > ---
> > .../devicetree/bindings/pci/fsl,mpc8xxx-pci.yaml | 83 ++++++++++++++++++++++
> > 1 file changed, 83 insertions(+)
[...]
> > +examples:
> > + - |
> > + #include <dt-bindings/interrupt-controller/irq.h>
> > +
> > + pci1: pcie@e0009000 {
>
> needn't label here
Will change.
Thanks,
J. Neuschäfer
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH 6/9] dt-bindings: pci: Add fsl,mpc83xx-pcie bindings
2025-02-04 23:34 ` J. Neuschäfer
@ 2025-02-06 12:42 ` Mukesh Kumar Savaliya
2025-02-07 13:37 ` J. Neuschäfer
0 siblings, 1 reply; 41+ messages in thread
From: Mukesh Kumar Savaliya @ 2025-02-06 12:42 UTC (permalink / raw)
To: J. Neuschäfer, Frank Li
Cc: devicetree, linuxppc-dev, Scott Wood, Madhavan Srinivasan,
Michael Ellerman, Nicholas Piggin, Christophe Leroy, Naveen N Rao,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Damien Le Moal,
Niklas Cassel, Herbert Xu, David S. Miller, Lee Jones, Vinod Koul,
Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Bjorn Helgaas, J. Neuschäfer,
Wim Van Sebroeck, Guenter Roeck, Mark Brown, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-kernel, linux-ide,
linux-crypto, dmaengine, linux-pci, linux-watchdog, linux-spi,
linux-mtd
On 2/5/2025 5:04 AM, J. Neuschäfer wrote:
> On Wed, Jan 29, 2025 at 05:55:26PM -0500, Frank Li wrote:
>> On Sun, Jan 26, 2025 at 07:59:01PM +0100, J. Neuschäfer wrote:
>>> Supplement Documentation/devicetree/bindings/pci/fsl,pci.txt with a more
>>> formal binding in YAML format.
>>>
neat: subject: since binding is already mentioned in the prefix of the
subject, no need to add bindings word again.
>>> Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
>>> ---
>>> .../devicetree/bindings/pci/fsl,mpc8xxx-pci.yaml | 83 ++++++++++++++++++++++
>>> 1 file changed, 83 insertions(+)
> [...]
>>> +examples:
>>> + - |
>>> + #include <dt-bindings/interrupt-controller/irq.h>
>>> +
>>> + pci1: pcie@e0009000 {
>>
>> needn't label here
>
> Will change.
>
>
> Thanks,
> J. Neuschäfer
>
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH 6/9] dt-bindings: pci: Add fsl,mpc83xx-pcie bindings
2025-02-06 12:42 ` Mukesh Kumar Savaliya
@ 2025-02-07 13:37 ` J. Neuschäfer
0 siblings, 0 replies; 41+ messages in thread
From: J. Neuschäfer @ 2025-02-07 13:37 UTC (permalink / raw)
To: Mukesh Kumar Savaliya
Cc: J. Neuschäfer, Frank Li, devicetree, linuxppc-dev,
Scott Wood, Madhavan Srinivasan, Michael Ellerman,
Nicholas Piggin, Christophe Leroy, Naveen N Rao, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Damien Le Moal, Niklas Cassel,
Herbert Xu, David S. Miller, Lee Jones, Vinod Koul,
Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Bjorn Helgaas, J. Neuschäfer,
Wim Van Sebroeck, Guenter Roeck, Mark Brown, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-kernel, linux-ide,
linux-crypto, dmaengine, linux-pci, linux-watchdog, linux-spi,
linux-mtd
On Thu, Feb 06, 2025 at 06:12:47PM +0530, Mukesh Kumar Savaliya wrote:
> neat: subject: since binding is already mentioned in the prefix of the
> subject, no need to add bindings word again.
Sounds reasonable, thanks
J. Neuschäfer
^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH 7/9] dt-bindings: watchdog: Convert mpc8xxx-wdt binding to YAML
2025-01-26 18:58 [PATCH 0/9] YAML conversion of several Freescale/PowerPC DT bindings J. Neuschäfer via B4 Relay
` (5 preceding siblings ...)
2025-01-26 18:59 ` [PATCH 6/9] dt-bindings: pci: Add fsl,mpc83xx-pcie bindings J. Neuschäfer via B4 Relay
@ 2025-01-26 18:59 ` J. Neuschäfer via B4 Relay
2025-01-27 4:51 ` Rob Herring
2025-01-26 18:59 ` [PATCH 8/9] dt-bindings: spi: Convert Freescale SPI bindings " J. Neuschäfer via B4 Relay
` (2 subsequent siblings)
9 siblings, 1 reply; 41+ messages in thread
From: J. Neuschäfer via B4 Relay @ 2025-01-26 18:59 UTC (permalink / raw)
To: devicetree, linuxppc-dev
Cc: Scott Wood, Madhavan Srinivasan, Michael Ellerman,
Nicholas Piggin, Christophe Leroy, Naveen N Rao, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Damien Le Moal, Niklas Cassel,
Herbert Xu, David S. Miller, Lee Jones, Vinod Koul,
Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Bjorn Helgaas, J. Neuschäfer,
Wim Van Sebroeck, Guenter Roeck, Mark Brown, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-kernel, linux-ide,
linux-crypto, dmaengine, linux-pci, linux-watchdog, linux-spi,
linux-mtd, J. Neuschäfer
From: "J. Neuschäfer" <j.ne@posteo.net>
Convert mpc83xx-wdt.txt to YAML to enable automatic schema validation.
Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
---
.../devicetree/bindings/watchdog/mpc8xxx-wdt.txt | 25 ---------
.../devicetree/bindings/watchdog/mpc8xxx-wdt.yaml | 64 ++++++++++++++++++++++
2 files changed, 64 insertions(+), 25 deletions(-)
diff --git a/Documentation/devicetree/bindings/watchdog/mpc8xxx-wdt.txt b/Documentation/devicetree/bindings/watchdog/mpc8xxx-wdt.txt
deleted file mode 100644
index a384ff5b3ce8c62d813fc23d72f74e2158ff543e..0000000000000000000000000000000000000000
--- a/Documentation/devicetree/bindings/watchdog/mpc8xxx-wdt.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-* Freescale mpc8xxx watchdog driver (For 83xx, 86xx and 8xx)
-
-Required properties:
-- compatible: Shall contain one of the following:
- "mpc83xx_wdt" for an mpc83xx
- "fsl,mpc8610-wdt" for an mpc86xx
- "fsl,mpc823-wdt" for an mpc8xx
-- reg: base physical address and length of the area hosting the
- watchdog registers.
- On the 83xx, "Watchdog Timer Registers" area: <0x200 0x100>
- On the 86xx, "Watchdog Timer Registers" area: <0xe4000 0x100>
- On the 8xx, "General System Interface Unit" area: <0x0 0x10>
-
-Optional properties:
-- reg: additional physical address and length (4) of location of the
- Reset Status Register (called RSTRSCR on the mpc86xx)
- On the 83xx, it is located at offset 0x910
- On the 86xx, it is located at offset 0xe0094
- On the 8xx, it is located at offset 0x288
-
-Example:
- WDT: watchdog@0 {
- compatible = "fsl,mpc823-wdt";
- reg = <0x0 0x10 0x288 0x4>;
- };
diff --git a/Documentation/devicetree/bindings/watchdog/mpc8xxx-wdt.yaml b/Documentation/devicetree/bindings/watchdog/mpc8xxx-wdt.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..c78a424388c6e30bc4656f5444e621c1b397366b
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/mpc8xxx-wdt.yaml
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/watchdog/mpc8xxx-wdt.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale MPC8xxx watchdog timer (For 83xx, 86xx and 8xx)
+
+maintainers:
+ - J. Neuschäfer <j.ne@posteo.net>
+
+properties:
+ compatible:
+ enum:
+ - mpc83xx_wdt # for an mpc83xx
+ - fsl,mpc8610-wdt # for an mpc86xx
+ - fsl,mpc823-wdt # for an mpc8xx
+
+ device_type:
+ const: watchdog
+
+ reg:
+ minItems: 1
+ items:
+ - description: |
+ Base physical address and length of the area hosting the watchdog
+ registers.
+
+ On the 83xx, "Watchdog Timer Registers" area: <0x200 0x100>
+ On the 86xx, "Watchdog Timer Registers" area: <0xe4000 0x100>
+ On the 8xx, "General System Interface Unit" area: <0x0 0x10>
+
+ - description: |
+ Additional optional physical address and length (4) of location of
+ the Reset Status Register (called RSTRSCR on the mpc86xx)
+
+ On the 83xx, it is located at offset 0x910
+ On the 86xx, it is located at offset 0xe0094
+ On the 8xx, it is located at offset 0x288
+
+required:
+ - compatible
+ - reg
+
+allOf:
+ - $ref: watchdog.yaml#
+
+additionalProperties: false
+
+examples:
+ - |
+ WDT: watchdog@0 {
+ compatible = "fsl,mpc823-wdt";
+ reg = <0x0 0x10 0x288 0x4>;
+ };
+
+ - |
+ wdt: watchdog@200 {
+ device_type = "watchdog";
+ compatible = "mpc83xx_wdt";
+ reg = <0x200 0x100>;
+ };
+
+...
--
2.48.0.rc1.219.gb6b6757d772
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [PATCH 7/9] dt-bindings: watchdog: Convert mpc8xxx-wdt binding to YAML
2025-01-26 18:59 ` [PATCH 7/9] dt-bindings: watchdog: Convert mpc8xxx-wdt binding to YAML J. Neuschäfer via B4 Relay
@ 2025-01-27 4:51 ` Rob Herring
0 siblings, 0 replies; 41+ messages in thread
From: Rob Herring @ 2025-01-27 4:51 UTC (permalink / raw)
To: J. Neuschäfer
Cc: devicetree, linuxppc-dev, Scott Wood, Madhavan Srinivasan,
Michael Ellerman, Nicholas Piggin, Christophe Leroy, Naveen N Rao,
Krzysztof Kozlowski, Conor Dooley, Damien Le Moal, Niklas Cassel,
Herbert Xu, David S. Miller, Lee Jones, Vinod Koul,
Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Bjorn Helgaas, J. Neuschäfer,
Wim Van Sebroeck, Guenter Roeck, Mark Brown, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-kernel, linux-ide,
linux-crypto, dmaengine, linux-pci, linux-watchdog, linux-spi,
linux-mtd
On Sun, Jan 26, 2025 at 07:59:02PM +0100, J. Neuschäfer wrote:
> Convert mpc83xx-wdt.txt to YAML to enable automatic schema validation.
>
> Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
> ---
> .../devicetree/bindings/watchdog/mpc8xxx-wdt.txt | 25 ---------
> .../devicetree/bindings/watchdog/mpc8xxx-wdt.yaml | 64 ++++++++++++++++++++++
> 2 files changed, 64 insertions(+), 25 deletions(-)
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH 8/9] dt-bindings: spi: Convert Freescale SPI bindings to YAML
2025-01-26 18:58 [PATCH 0/9] YAML conversion of several Freescale/PowerPC DT bindings J. Neuschäfer via B4 Relay
` (6 preceding siblings ...)
2025-01-26 18:59 ` [PATCH 7/9] dt-bindings: watchdog: Convert mpc8xxx-wdt binding to YAML J. Neuschäfer via B4 Relay
@ 2025-01-26 18:59 ` J. Neuschäfer via B4 Relay
2025-01-27 5:09 ` Rob Herring
2025-01-26 18:59 ` [PATCH RFC 9/9] dt-bindings: nand: Convert fsl,elbc " J. Neuschäfer via B4 Relay
2025-01-29 22:29 ` [PATCH 0/9] YAML conversion of several Freescale/PowerPC DT bindings Frank Li
9 siblings, 1 reply; 41+ messages in thread
From: J. Neuschäfer via B4 Relay @ 2025-01-26 18:59 UTC (permalink / raw)
To: devicetree, linuxppc-dev
Cc: Scott Wood, Madhavan Srinivasan, Michael Ellerman,
Nicholas Piggin, Christophe Leroy, Naveen N Rao, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Damien Le Moal, Niklas Cassel,
Herbert Xu, David S. Miller, Lee Jones, Vinod Koul,
Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Bjorn Helgaas, J. Neuschäfer,
Wim Van Sebroeck, Guenter Roeck, Mark Brown, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-kernel, linux-ide,
linux-crypto, dmaengine, linux-pci, linux-watchdog, linux-spi,
linux-mtd, J. Neuschäfer
From: "J. Neuschäfer" <j.ne@posteo.net>
fsl-spi.txt contains the bindings for the fsl,spi and fsl,espi
contollers. Convert them to YAML.
Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
---
.../devicetree/bindings/spi/fsl,espi.yaml | 56 +++++++++++++++++
Documentation/devicetree/bindings/spi/fsl,spi.yaml | 71 ++++++++++++++++++++++
Documentation/devicetree/bindings/spi/fsl-spi.txt | 62 -------------------
3 files changed, 127 insertions(+), 62 deletions(-)
diff --git a/Documentation/devicetree/bindings/spi/fsl,espi.yaml b/Documentation/devicetree/bindings/spi/fsl,espi.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..350275760210c5763af0c7b1e1522ccbfb97eec7
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/fsl,espi.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/fsl,espi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale eSPI (Enhanced Serial Peripheral Interface) controller
+
+maintainers:
+ - J. Neuschäfer <j.ne@posteo.net>
+
+properties:
+ compatible:
+ const: fsl,mpc8536-espi
+
+ reg:
+ maxItems: 1
+
+ interrupts: true
+
+ fsl,espi-num-chipselects:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: The number of the chipselect signals.
+
+ fsl,csbef:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Chip select assertion time in bits before frame starts
+
+ fsl,csaft:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Chip select negation time in bits after frame ends
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - fsl,espi-num-chipselects
+
+allOf:
+ - $ref: spi-controller.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ spi@110000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,mpc8536-espi";
+ reg = <0x110000 0x1000>;
+ interrupts = <53 0x2>;
+ interrupt-parent = <&mpic>;
+ fsl,espi-num-chipselects = <4>;
+ fsl,csbef = <1>;
+ fsl,csaft = <1>;
+ };
diff --git a/Documentation/devicetree/bindings/spi/fsl,spi.yaml b/Documentation/devicetree/bindings/spi/fsl,spi.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..8efa971b5954a93665cb624345774f2966bb5648
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/fsl,spi.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/fsl,spi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale SPI (Serial Peripheral Interface) controller
+
+maintainers:
+ - J. Neuschäfer <j.ne@posteo.net>
+
+properties:
+ compatible:
+ enum:
+ - fsl,spi
+ - aeroflexgaisler,spictrl
+
+ reg:
+ maxItems: 1
+
+ cell-index:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ QE SPI subblock index.
+ 0: QE subblock SPI1
+ 1: QE subblock SPI2
+
+ mode:
+ description: SPI operation mode
+ enum:
+ - cpu
+ - cpu-qe
+
+ interrupts: true
+
+ clock-frequency:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: input clock frequency to non FSL_SOC cores
+
+ cs-gpios: true
+
+ fsl,spisel_boot:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ For the MPC8306 and MPC8309, specifies that the SPISEL_BOOT signal is used
+ as chip select for a slave device. Use reg = <number of gpios> in the
+ corresponding child node, i.e. 0 if the cs-gpios property is not present.
+
+required:
+ - compatible
+ - reg
+ - mode
+ - interrupts
+
+allOf:
+ - $ref: spi-controller.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ spi@4c0 {
+ cell-index = <0>;
+ compatible = "fsl,spi";
+ reg = <0x4c0 0x40>;
+ interrupts = <82 0>;
+ interrupt-parent = <&intc>;
+ mode = "cpu";
+ cs-gpios = <&gpio 18 1 // device reg=<0>
+ &gpio 19 1>; // device reg=<1>
+ };
diff --git a/Documentation/devicetree/bindings/spi/fsl-spi.txt b/Documentation/devicetree/bindings/spi/fsl-spi.txt
deleted file mode 100644
index 0654380eb7515d8bda80eea1486e77b939ac38d8..0000000000000000000000000000000000000000
--- a/Documentation/devicetree/bindings/spi/fsl-spi.txt
+++ /dev/null
@@ -1,62 +0,0 @@
-* SPI (Serial Peripheral Interface)
-
-Required properties:
-- cell-index : QE SPI subblock index.
- 0: QE subblock SPI1
- 1: QE subblock SPI2
-- compatible : should be "fsl,spi" or "aeroflexgaisler,spictrl".
-- mode : the SPI operation mode, it can be "cpu" or "cpu-qe".
-- reg : Offset and length of the register set for the device
-- interrupts : <a b> where a is the interrupt number and b is a
- field that represents an encoding of the sense and level
- information for the interrupt. This should be encoded based on
- the information in section 2) depending on the type of interrupt
- controller you have.
-- clock-frequency : input clock frequency to non FSL_SOC cores
-
-Optional properties:
-- cs-gpios : specifies the gpio pins to be used for chipselects.
- The gpios will be referred to as reg = <index> in the SPI child nodes.
- If unspecified, a single SPI device without a chip select can be used.
-- fsl,spisel_boot : for the MPC8306 and MPC8309, specifies that the
- SPISEL_BOOT signal is used as chip select for a slave device. Use
- reg = <number of gpios> in the corresponding child node, i.e. 0 if
- the cs-gpios property is not present.
-
-Example:
- spi@4c0 {
- cell-index = <0>;
- compatible = "fsl,spi";
- reg = <4c0 40>;
- interrupts = <82 0>;
- interrupt-parent = <700>;
- mode = "cpu";
- cs-gpios = <&gpio 18 1 // device reg=<0>
- &gpio 19 1>; // device reg=<1>
- };
-
-
-* eSPI (Enhanced Serial Peripheral Interface)
-
-Required properties:
-- compatible : should be "fsl,mpc8536-espi".
-- reg : Offset and length of the register set for the device.
-- interrupts : should contain eSPI interrupt, the device has one interrupt.
-- fsl,espi-num-chipselects : the number of the chipselect signals.
-
-Optional properties:
-- fsl,csbef: chip select assertion time in bits before frame starts
-- fsl,csaft: chip select negation time in bits after frame ends
-
-Example:
- spi@110000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,mpc8536-espi";
- reg = <0x110000 0x1000>;
- interrupts = <53 0x2>;
- interrupt-parent = <&mpic>;
- fsl,espi-num-chipselects = <4>;
- fsl,csbef = <1>;
- fsl,csaft = <1>;
- };
--
2.48.0.rc1.219.gb6b6757d772
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [PATCH 8/9] dt-bindings: spi: Convert Freescale SPI bindings to YAML
2025-01-26 18:59 ` [PATCH 8/9] dt-bindings: spi: Convert Freescale SPI bindings " J. Neuschäfer via B4 Relay
@ 2025-01-27 5:09 ` Rob Herring
2025-02-05 14:29 ` J. Neuschäfer
0 siblings, 1 reply; 41+ messages in thread
From: Rob Herring @ 2025-01-27 5:09 UTC (permalink / raw)
To: J. Neuschäfer
Cc: devicetree, linuxppc-dev, Scott Wood, Madhavan Srinivasan,
Michael Ellerman, Nicholas Piggin, Christophe Leroy, Naveen N Rao,
Krzysztof Kozlowski, Conor Dooley, Damien Le Moal, Niklas Cassel,
Herbert Xu, David S. Miller, Lee Jones, Vinod Koul,
Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Bjorn Helgaas, J. Neuschäfer,
Wim Van Sebroeck, Guenter Roeck, Mark Brown, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-kernel, linux-ide,
linux-crypto, dmaengine, linux-pci, linux-watchdog, linux-spi,
linux-mtd
On Sun, Jan 26, 2025 at 07:59:03PM +0100, J. Neuschäfer wrote:
> fsl-spi.txt contains the bindings for the fsl,spi and fsl,espi
> contollers. Convert them to YAML.
>
> Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
> ---
> .../devicetree/bindings/spi/fsl,espi.yaml | 56 +++++++++++++++++
> Documentation/devicetree/bindings/spi/fsl,spi.yaml | 71 ++++++++++++++++++++++
> Documentation/devicetree/bindings/spi/fsl-spi.txt | 62 -------------------
> 3 files changed, 127 insertions(+), 62 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/spi/fsl,espi.yaml b/Documentation/devicetree/bindings/spi/fsl,espi.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..350275760210c5763af0c7b1e1522ccbfb97eec7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/fsl,espi.yaml
> @@ -0,0 +1,56 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/spi/fsl,espi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale eSPI (Enhanced Serial Peripheral Interface) controller
> +
> +maintainers:
> + - J. Neuschäfer <j.ne@posteo.net>
> +
> +properties:
> + compatible:
> + const: fsl,mpc8536-espi
> +
> + reg:
> + maxItems: 1
> +
> + interrupts: true
How many?
> +
> + fsl,espi-num-chipselects:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: The number of the chipselect signals.
Constraints?
> +
> + fsl,csbef:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: Chip select assertion time in bits before frame starts
Constraints?
> +
> + fsl,csaft:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: Chip select negation time in bits after frame ends
Constraints?
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - fsl,espi-num-chipselects
> +
> +allOf:
> + - $ref: spi-controller.yaml#
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + spi@110000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,mpc8536-espi";
> + reg = <0x110000 0x1000>;
> + interrupts = <53 0x2>;
> + interrupt-parent = <&mpic>;
> + fsl,espi-num-chipselects = <4>;
> + fsl,csbef = <1>;
> + fsl,csaft = <1>;
> + };
> diff --git a/Documentation/devicetree/bindings/spi/fsl,spi.yaml b/Documentation/devicetree/bindings/spi/fsl,spi.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..8efa971b5954a93665cb624345774f2966bb5648
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/fsl,spi.yaml
> @@ -0,0 +1,71 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/spi/fsl,spi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale SPI (Serial Peripheral Interface) controller
> +
> +maintainers:
> + - J. Neuschäfer <j.ne@posteo.net>
> +
> +properties:
> + compatible:
> + enum:
> + - fsl,spi
> + - aeroflexgaisler,spictrl
> +
> + reg:
> + maxItems: 1
> +
> + cell-index:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: |
> + QE SPI subblock index.
> + 0: QE subblock SPI1
> + 1: QE subblock SPI2
> +
> + mode:
> + description: SPI operation mode
> + enum:
> + - cpu
> + - cpu-qe
> +
> + interrupts: true
> +
> + clock-frequency:
> + $ref: /schemas/types.yaml#/definitions/uint32
Don't need a type.
> + description: input clock frequency to non FSL_SOC cores
> +
> + cs-gpios: true
> +
> + fsl,spisel_boot:
> + $ref: /schemas/types.yaml#/definitions/flag
> + description:
> + For the MPC8306 and MPC8309, specifies that the SPISEL_BOOT signal is used
> + as chip select for a slave device. Use reg = <number of gpios> in the
> + corresponding child node, i.e. 0 if the cs-gpios property is not present.
> +
> +required:
> + - compatible
> + - reg
> + - mode
> + - interrupts
> +
> +allOf:
> + - $ref: spi-controller.yaml#
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + spi@4c0 {
> + cell-index = <0>;
> + compatible = "fsl,spi";
> + reg = <0x4c0 0x40>;
> + interrupts = <82 0>;
> + interrupt-parent = <&intc>;
> + mode = "cpu";
> + cs-gpios = <&gpio 18 1 // device reg=<0>
> + &gpio 19 1>; // device reg=<1>
> + };
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH 8/9] dt-bindings: spi: Convert Freescale SPI bindings to YAML
2025-01-27 5:09 ` Rob Herring
@ 2025-02-05 14:29 ` J. Neuschäfer
0 siblings, 0 replies; 41+ messages in thread
From: J. Neuschäfer @ 2025-02-05 14:29 UTC (permalink / raw)
To: Rob Herring
Cc: J. Neuschäfer, devicetree, linuxppc-dev, Scott Wood,
Madhavan Srinivasan, Michael Ellerman, Nicholas Piggin,
Christophe Leroy, Naveen N Rao, Krzysztof Kozlowski, Conor Dooley,
Damien Le Moal, Niklas Cassel, Herbert Xu, David S. Miller,
Lee Jones, Vinod Koul, Lorenzo Pieralisi,
Krzysztof Wilczyński, Manivannan Sadhasivam, Bjorn Helgaas,
J. Neuschäfer, Wim Van Sebroeck, Guenter Roeck, Mark Brown,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-kernel, linux-ide, linux-crypto, dmaengine, linux-pci,
linux-watchdog, linux-spi, linux-mtd
On Sun, Jan 26, 2025 at 11:09:01PM -0600, Rob Herring wrote:
> On Sun, Jan 26, 2025 at 07:59:03PM +0100, J. Neuschäfer wrote:
> > fsl-spi.txt contains the bindings for the fsl,spi and fsl,espi
> > contollers. Convert them to YAML.
> >
> > Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
> > ---
> > .../devicetree/bindings/spi/fsl,espi.yaml | 56 +++++++++++++++++
> > Documentation/devicetree/bindings/spi/fsl,spi.yaml | 71 ++++++++++++++++++++++
> > Documentation/devicetree/bindings/spi/fsl-spi.txt | 62 -------------------
> > 3 files changed, 127 insertions(+), 62 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/spi/fsl,espi.yaml b/Documentation/devicetree/bindings/spi/fsl,espi.yaml
> > new file mode 100644
> > index 0000000000000000000000000000000000000000..350275760210c5763af0c7b1e1522ccbfb97eec7
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/spi/fsl,espi.yaml
> > @@ -0,0 +1,56 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/spi/fsl,espi.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Freescale eSPI (Enhanced Serial Peripheral Interface) controller
> > +
> > +maintainers:
> > + - J. Neuschäfer <j.ne@posteo.net>
> > +
> > +properties:
> > + compatible:
> > + const: fsl,mpc8536-espi
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + interrupts: true
>
> How many?
>
> > +
> > + fsl,espi-num-chipselects:
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + description: The number of the chipselect signals.
>
> Constraints?
>
> > +
> > + fsl,csbef:
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + description: Chip select assertion time in bits before frame starts
>
> Constraints?
>
> > +
> > + fsl,csaft:
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + description: Chip select negation time in bits after frame ends
>
> Constraints?
I'll add appropriate constraints to all of these.
> > diff --git a/Documentation/devicetree/bindings/spi/fsl,spi.yaml b/Documentation/devicetree/bindings/spi/fsl,spi.yaml
[...]
> > + clock-frequency:
> > + $ref: /schemas/types.yaml#/definitions/uint32
>
> Don't need a type.
Will remove
>
> > + description: input clock frequency to non FSL_SOC cores
> > +
> > + cs-gpios: true
> > +
> > + fsl,spisel_boot:
> > + $ref: /schemas/types.yaml#/definitions/flag
I do wonder, what's the difference between
$ref: /schemas/types.yaml#/definitions/flag and type: boolean?
Thanks for your review.
Best regards,
J. Neuschäfer
^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH RFC 9/9] dt-bindings: nand: Convert fsl,elbc bindings to YAML
2025-01-26 18:58 [PATCH 0/9] YAML conversion of several Freescale/PowerPC DT bindings J. Neuschäfer via B4 Relay
` (7 preceding siblings ...)
2025-01-26 18:59 ` [PATCH 8/9] dt-bindings: spi: Convert Freescale SPI bindings " J. Neuschäfer via B4 Relay
@ 2025-01-26 18:59 ` J. Neuschäfer via B4 Relay
2025-01-27 4:23 ` Rob Herring
` (2 more replies)
2025-01-29 22:29 ` [PATCH 0/9] YAML conversion of several Freescale/PowerPC DT bindings Frank Li
9 siblings, 3 replies; 41+ messages in thread
From: J. Neuschäfer via B4 Relay @ 2025-01-26 18:59 UTC (permalink / raw)
To: devicetree, linuxppc-dev
Cc: Scott Wood, Madhavan Srinivasan, Michael Ellerman,
Nicholas Piggin, Christophe Leroy, Naveen N Rao, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Damien Le Moal, Niklas Cassel,
Herbert Xu, David S. Miller, Lee Jones, Vinod Koul,
Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Bjorn Helgaas, J. Neuschäfer,
Wim Van Sebroeck, Guenter Roeck, Mark Brown, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-kernel, linux-ide,
linux-crypto, dmaengine, linux-pci, linux-watchdog, linux-spi,
linux-mtd, J. Neuschäfer
From: "J. Neuschäfer" <j.ne@posteo.net>
Convert the Freescale localbus controller bindings from text form to
YAML. The list of compatible strings reflects current usage.
Changes compared to the txt version:
- removed the board-control (fsl,mpc8272ads-bcsr) node because it only
appears in this example and nowhere else
- added a new example with NAND flash
Remaining issues:
- The localbus is not really a simple-bus: Unit addresses are not simply
addresses on a memory bus. Instead, they have a format: The first cell
is a chip select number, the remaining one or two cells are bus
addresses.
Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
---
.../devicetree/bindings/mtd/fsl,elbc-fcm-nand.yaml | 61 +++++++++
.../bindings/powerpc/fsl/fsl,elbc-gpcm-uio.yaml | 55 ++++++++
.../devicetree/bindings/powerpc/fsl/fsl,elbc.yaml | 150 +++++++++++++++++++++
.../devicetree/bindings/powerpc/fsl/lbc.txt | 43 ------
4 files changed, 266 insertions(+), 43 deletions(-)
diff --git a/Documentation/devicetree/bindings/mtd/fsl,elbc-fcm-nand.yaml b/Documentation/devicetree/bindings/mtd/fsl,elbc-fcm-nand.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..127f164443972bbaf50fd9daa80c504577ddd7bd
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/fsl,elbc-fcm-nand.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/fsl,elbc-fcm-nand.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NAND flash attached to Freescale eLBC
+
+maintainers:
+ - J. Neuschäfer <j.ne@posteo.net>
+
+allOf:
+ - $ref: nand-chip.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - fsl,mpc8313-fcm-nand
+ - fsl,mpc8315-fcm-nand
+ - fsl,mpc8377-fcm-nand
+ - fsl,mpc8378-fcm-nand
+ - fsl,mpc8379-fcm-nand
+ - fsl,mpc8536-fcm-nand
+ - fsl,mpc8569-fcm-nand
+ - fsl,mpc8572-fcm-nand
+ - fsl,p1020-fcm-nand
+ - fsl,p1021-fcm-nand
+ - fsl,p1025-fcm-nand
+ - fsl,p2020-fcm-nand
+ - const: fsl,elbc-fcm-nand
+ - const: fsl,elbc-fcm-nand
+
+ reg:
+ maxItems: 1
+
+ "#address-cells": true
+
+ "#size-cells": true
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ localbus {
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ nand@1,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8315-fcm-nand",
+ "fsl,elbc-fcm-nand";
+ reg = <0x1 0x0 0x2000>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/fsl,elbc-gpcm-uio.yaml b/Documentation/devicetree/bindings/powerpc/fsl/fsl,elbc-gpcm-uio.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..60f849b79c11a4060f2fa4ab163f9fa9317df130
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/fsl,elbc-gpcm-uio.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/powerpc/fsl/fsl,elbc-gpcm-uio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Userspace I/O interface for Freescale eLBC devices
+
+maintainers:
+ - J. Neuschäfer <j.ne@posteo.net>
+
+properties:
+ compatible:
+ const: fsl,elbc-gpcm-uio
+
+ reg:
+ maxItems: 1
+
+ elbc-gpcm-br:
+ description: Base Register (BR) value to set
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ elbc-gpcm-or:
+ description: Option Register (OR) value to set
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ device_type: true
+
+ interrupts:
+ maxItems: 1
+
+ uio_name:
+ $ref: /schemas/types.yaml#/definitions/string
+
+required:
+ - compatible
+ - reg
+ - elbc-gpcm-br
+ - elbc-gpcm-or
+
+additionalProperties: false
+
+examples:
+ - |
+ localbus {
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ simple-periph@2,0 {
+ compatible = "fsl,elbc-gpcm-uio";
+ reg = <0x2 0x0 0x10000>;
+ elbc-gpcm-br = <0xfd810800>;
+ elbc-gpcm-or = <0xffff09f7>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/fsl,elbc.yaml b/Documentation/devicetree/bindings/powerpc/fsl/fsl,elbc.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..6bbceb82c77826499abe85879e9189b18d396eea
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/fsl,elbc.yaml
@@ -0,0 +1,150 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/powerpc/fsl/fsl,elbc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale Enhanced Local Bus Controller
+
+maintainers:
+ - J. Neuschäfer <j.ne@posteo.net>
+
+properties:
+ $nodename:
+ pattern: "^localbus@[0-9a-f]+$"
+
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - fsl,mpc8313-elbc
+ - fsl,mpc8315-elbc
+ - fsl,mpc8377-elbc
+ - fsl,mpc8378-elbc
+ - fsl,mpc8379-elbc
+ - fsl,mpc8536-elbc
+ - fsl,mpc8569-elbc
+ - fsl,mpc8572-elbc
+ - fsl,p1020-elbc
+ - fsl,p1021-elbc
+ - fsl,p1023-elbc
+ - fsl,p2020-elbc
+ - fsl,p2041-elbc
+ - fsl,p3041-elbc
+ - fsl,p4080-elbc
+ - fsl,p5020-elbc
+ - fsl,p5040-elbc
+ - const: fsl,elbc
+ - const: simple-bus
+
+ - items:
+ - const: fsl,mpc8272-localbus
+ - const: fsl,pq2-localbus
+
+ - items:
+ - enum:
+ - fsl,mpc8247-localbus
+ - fsl,mpc8248-localbus
+ - fsl,mpc8360-localbus
+ - const: fsl,pq2pro-localbus
+ - const: simple-bus
+
+ - items:
+ - enum:
+ - fsl,mpc8540-localbus
+ - fsl,mpc8544-lbc
+ - fsl,mpc8544-localbus
+ - fsl,mpc8548-lbc
+ - fsl,mpc8548-localbus
+ - fsl,mpc8560-localbus
+ - fsl,mpc8568-localbus
+ - const: fsl,pq3-localbus
+ - const: simple-bus
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ "#address-cells":
+ enum: [2, 3]
+ description: |
+ The first cell is the chipselect number, and the remaining cells are the
+ offset into the chipselect.
+
+ "#size-cells":
+ enum: [1, 2]
+ description: |
+ Either one or two, depending on how large each chipselect can be.
+
+ ranges:
+ description: |
+ Each range corresponds to a single chipselect, and covers the entire
+ access window as configured.
+
+patternProperties:
+ "^.*@.*$":
+ type: object
+
+additionalProperties: false
+
+examples:
+ - |
+ localbus@f0010100 {
+ compatible = "fsl,mpc8272-localbus",
+ "fsl,pq2-localbus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ reg = <0xf0010100 0x40>;
+
+ ranges = <0x0 0x0 0xfe000000 0x02000000
+ 0x1 0x0 0xf4500000 0x00008000
+ 0x2 0x0 0xfd810000 0x00010000>;
+
+ flash@0,0 {
+ compatible = "jedec-flash";
+ reg = <0x0 0x0 0x2000000>;
+ bank-width = <4>;
+ device-width = <1>;
+ };
+
+ simple-periph@2,0 {
+ compatible = "fsl,elbc-gpcm-uio";
+ reg = <0x2 0x0 0x10000>;
+ elbc-gpcm-br = <0xfd810800>;
+ elbc-gpcm-or = <0xffff09f7>;
+ };
+ };
+
+ - |
+ localbus@e0005000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
+ reg = <0xe0005000 0x1000>;
+ interrupts = <77 0x8>;
+ interrupt-parent = <&ipic>;
+
+ ranges = <0x0 0x0 0xfe000000 0x00800000
+ 0x1 0x0 0xe0600000 0x00002000
+ 0x2 0x0 0xf0000000 0x00020000
+ 0x3 0x0 0xfa000000 0x00008000>;
+
+ flash@0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x800000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+
+ nand@1,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8315-fcm-nand",
+ "fsl,elbc-fcm-nand";
+ reg = <0x1 0x0 0x2000>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/lbc.txt b/Documentation/devicetree/bindings/powerpc/fsl/lbc.txt
deleted file mode 100644
index 1c80fcedebb52049721fbd61c4dd4c57133bd47c..0000000000000000000000000000000000000000
--- a/Documentation/devicetree/bindings/powerpc/fsl/lbc.txt
+++ /dev/null
@@ -1,43 +0,0 @@
-* Chipselect/Local Bus
-
-Properties:
-- name : Should be localbus
-- #address-cells : Should be either two or three. The first cell is the
- chipselect number, and the remaining cells are the
- offset into the chipselect.
-- #size-cells : Either one or two, depending on how large each chipselect
- can be.
-- ranges : Each range corresponds to a single chipselect, and cover
- the entire access window as configured.
-
-Example:
- localbus@f0010100 {
- compatible = "fsl,mpc8272-localbus",
- "fsl,pq2-localbus";
- #address-cells = <2>;
- #size-cells = <1>;
- reg = <0xf0010100 0x40>;
-
- ranges = <0x0 0x0 0xfe000000 0x02000000
- 0x1 0x0 0xf4500000 0x00008000
- 0x2 0x0 0xfd810000 0x00010000>;
-
- flash@0,0 {
- compatible = "jedec-flash";
- reg = <0x0 0x0 0x2000000>;
- bank-width = <4>;
- device-width = <1>;
- };
-
- board-control@1,0 {
- reg = <0x1 0x0 0x20>;
- compatible = "fsl,mpc8272ads-bcsr";
- };
-
- simple-periph@2,0 {
- compatible = "fsl,elbc-gpcm-uio";
- reg = <0x2 0x0 0x10000>;
- elbc-gpcm-br = <0xfd810800>;
- elbc-gpcm-or = <0xffff09f7>;
- };
- };
--
2.48.0.rc1.219.gb6b6757d772
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [PATCH RFC 9/9] dt-bindings: nand: Convert fsl,elbc bindings to YAML
2025-01-26 18:59 ` [PATCH RFC 9/9] dt-bindings: nand: Convert fsl,elbc " J. Neuschäfer via B4 Relay
@ 2025-01-27 4:23 ` Rob Herring
2025-02-06 22:59 ` J. Neuschäfer
2025-01-27 8:37 ` Krzysztof Kozlowski
2025-01-29 23:01 ` Frank Li
2 siblings, 1 reply; 41+ messages in thread
From: Rob Herring @ 2025-01-27 4:23 UTC (permalink / raw)
To: J. Neuschäfer
Cc: devicetree, linuxppc-dev, Scott Wood, Madhavan Srinivasan,
Michael Ellerman, Nicholas Piggin, Christophe Leroy, Naveen N Rao,
Krzysztof Kozlowski, Conor Dooley, Damien Le Moal, Niklas Cassel,
Herbert Xu, David S. Miller, Lee Jones, Vinod Koul,
Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Bjorn Helgaas, J. Neuschäfer,
Wim Van Sebroeck, Guenter Roeck, Mark Brown, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-kernel, linux-ide,
linux-crypto, dmaengine, linux-pci, linux-watchdog, linux-spi,
linux-mtd
On Sun, Jan 26, 2025 at 07:59:04PM +0100, J. Neuschäfer wrote:
> Convert the Freescale localbus controller bindings from text form to
> YAML. The list of compatible strings reflects current usage.
>
> Changes compared to the txt version:
> - removed the board-control (fsl,mpc8272ads-bcsr) node because it only
> appears in this example and nowhere else
> - added a new example with NAND flash
>
> Remaining issues:
> - The localbus is not really a simple-bus: Unit addresses are not simply
> addresses on a memory bus. Instead, they have a format: The first cell
> is a chip select number, the remaining one or two cells are bus
> addresses.
That's every external parallel bus. See bindings/memory-controllers/*
Probably fine to leave 'simple-bus' if that's your question. It's more
that there is configuration for the chipselect timings that make's this
not a simple-bus. But the address translation should work just fine.
>
> Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
> ---
> .../devicetree/bindings/mtd/fsl,elbc-fcm-nand.yaml | 61 +++++++++
> .../bindings/powerpc/fsl/fsl,elbc-gpcm-uio.yaml | 55 ++++++++
> .../devicetree/bindings/powerpc/fsl/fsl,elbc.yaml | 150 +++++++++++++++++++++
> .../devicetree/bindings/powerpc/fsl/lbc.txt | 43 ------
> 4 files changed, 266 insertions(+), 43 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/mtd/fsl,elbc-fcm-nand.yaml b/Documentation/devicetree/bindings/mtd/fsl,elbc-fcm-nand.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..127f164443972bbaf50fd9daa80c504577ddd7bd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mtd/fsl,elbc-fcm-nand.yaml
> @@ -0,0 +1,61 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mtd/fsl,elbc-fcm-nand.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NAND flash attached to Freescale eLBC
> +
> +maintainers:
> + - J. Neuschäfer <j.ne@posteo.net>
> +
> +allOf:
> + - $ref: nand-chip.yaml#
> +
> +properties:
> + compatible:
> + oneOf:
Don't need oneOf.
> + - items:
> + - enum:
> + - fsl,mpc8313-fcm-nand
> + - fsl,mpc8315-fcm-nand
> + - fsl,mpc8377-fcm-nand
> + - fsl,mpc8378-fcm-nand
> + - fsl,mpc8379-fcm-nand
> + - fsl,mpc8536-fcm-nand
> + - fsl,mpc8569-fcm-nand
> + - fsl,mpc8572-fcm-nand
> + - fsl,p1020-fcm-nand
> + - fsl,p1021-fcm-nand
> + - fsl,p1025-fcm-nand
> + - fsl,p2020-fcm-nand
> + - const: fsl,elbc-fcm-nand
> + - const: fsl,elbc-fcm-nand
> +
> + reg:
> + maxItems: 1
> +
> + "#address-cells": true
> +
> + "#size-cells": true
> +
> +required:
> + - compatible
> + - reg
> +
> +additionalProperties: false
If you use anything from nand-chip.yaml, then you need
unevaluatedProperties here.
> +
> +examples:
> + - |
> + localbus {
> + #address-cells = <2>;
> + #size-cells = <1>;
> +
> + nand@1,0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "fsl,mpc8315-fcm-nand",
> + "fsl,elbc-fcm-nand";
> + reg = <0x1 0x0 0x2000>;
> + };
> + };
> diff --git a/Documentation/devicetree/bindings/powerpc/fsl/fsl,elbc-gpcm-uio.yaml b/Documentation/devicetree/bindings/powerpc/fsl/fsl,elbc-gpcm-uio.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..60f849b79c11a4060f2fa4ab163f9fa9317df130
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/powerpc/fsl/fsl,elbc-gpcm-uio.yaml
> @@ -0,0 +1,55 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/powerpc/fsl/fsl,elbc-gpcm-uio.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Userspace I/O interface for Freescale eLBC devices
> +
> +maintainers:
> + - J. Neuschäfer <j.ne@posteo.net>
> +
> +properties:
> + compatible:
> + const: fsl,elbc-gpcm-uio
> +
> + reg:
> + maxItems: 1
> +
> + elbc-gpcm-br:
> + description: Base Register (BR) value to set
> + $ref: /schemas/types.yaml#/definitions/uint32
> +
> + elbc-gpcm-or:
> + description: Option Register (OR) value to set
> + $ref: /schemas/types.yaml#/definitions/uint32
> +
> + device_type: true
This should be dropped.
> +
> + interrupts:
> + maxItems: 1
> +
> + uio_name:
> + $ref: /schemas/types.yaml#/definitions/string
> +
> +required:
> + - compatible
> + - reg
> + - elbc-gpcm-br
> + - elbc-gpcm-or
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + localbus {
> + #address-cells = <2>;
> + #size-cells = <1>;
> +
> + simple-periph@2,0 {
> + compatible = "fsl,elbc-gpcm-uio";
> + reg = <0x2 0x0 0x10000>;
> + elbc-gpcm-br = <0xfd810800>;
> + elbc-gpcm-or = <0xffff09f7>;
> + };
> + };
> diff --git a/Documentation/devicetree/bindings/powerpc/fsl/fsl,elbc.yaml b/Documentation/devicetree/bindings/powerpc/fsl/fsl,elbc.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..6bbceb82c77826499abe85879e9189b18d396eea
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/powerpc/fsl/fsl,elbc.yaml
> @@ -0,0 +1,150 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/powerpc/fsl/fsl,elbc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale Enhanced Local Bus Controller
> +
> +maintainers:
> + - J. Neuschäfer <j.ne@posteo.net>
> +
> +properties:
> + $nodename:
> + pattern: "^localbus@[0-9a-f]+$"
> +
> + compatible:
> + oneOf:
> + - items:
> + - enum:
> + - fsl,mpc8313-elbc
> + - fsl,mpc8315-elbc
> + - fsl,mpc8377-elbc
> + - fsl,mpc8378-elbc
> + - fsl,mpc8379-elbc
> + - fsl,mpc8536-elbc
> + - fsl,mpc8569-elbc
> + - fsl,mpc8572-elbc
> + - fsl,p1020-elbc
> + - fsl,p1021-elbc
> + - fsl,p1023-elbc
> + - fsl,p2020-elbc
> + - fsl,p2041-elbc
> + - fsl,p3041-elbc
> + - fsl,p4080-elbc
> + - fsl,p5020-elbc
> + - fsl,p5040-elbc
> + - const: fsl,elbc
> + - const: simple-bus
> +
> + - items:
> + - const: fsl,mpc8272-localbus
> + - const: fsl,pq2-localbus
> +
> + - items:
> + - enum:
> + - fsl,mpc8247-localbus
> + - fsl,mpc8248-localbus
> + - fsl,mpc8360-localbus
> + - const: fsl,pq2pro-localbus
> + - const: simple-bus
> +
> + - items:
> + - enum:
> + - fsl,mpc8540-localbus
> + - fsl,mpc8544-lbc
> + - fsl,mpc8544-localbus
> + - fsl,mpc8548-lbc
> + - fsl,mpc8548-localbus
> + - fsl,mpc8560-localbus
> + - fsl,mpc8568-localbus
> + - const: fsl,pq3-localbus
> + - const: simple-bus
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + "#address-cells":
> + enum: [2, 3]
> + description: |
Don't need '|' unless there's some formatting.
> + The first cell is the chipselect number, and the remaining cells are the
> + offset into the chipselect.
> +
> + "#size-cells":
> + enum: [1, 2]
> + description: |
> + Either one or two, depending on how large each chipselect can be.
> +
> + ranges:
> + description: |
> + Each range corresponds to a single chipselect, and covers the entire
> + access window as configured.
> +
> +patternProperties:
> + "^.*@.*$":
You should define the unit-address format here: @<chipselect>,<offset>
> + type: object
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + localbus@f0010100 {
> + compatible = "fsl,mpc8272-localbus",
> + "fsl,pq2-localbus";
> + #address-cells = <2>;
> + #size-cells = <1>;
> + reg = <0xf0010100 0x40>;
> +
> + ranges = <0x0 0x0 0xfe000000 0x02000000
> + 0x1 0x0 0xf4500000 0x00008000
> + 0x2 0x0 0xfd810000 0x00010000>;
> +
> + flash@0,0 {
> + compatible = "jedec-flash";
> + reg = <0x0 0x0 0x2000000>;
> + bank-width = <4>;
> + device-width = <1>;
> + };
> +
> + simple-periph@2,0 {
> + compatible = "fsl,elbc-gpcm-uio";
> + reg = <0x2 0x0 0x10000>;
> + elbc-gpcm-br = <0xfd810800>;
> + elbc-gpcm-or = <0xffff09f7>;
> + };
> + };
> +
> + - |
> + localbus@e0005000 {
> + #address-cells = <2>;
> + #size-cells = <1>;
> + compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
> + reg = <0xe0005000 0x1000>;
> + interrupts = <77 0x8>;
> + interrupt-parent = <&ipic>;
> +
> + ranges = <0x0 0x0 0xfe000000 0x00800000
> + 0x1 0x0 0xe0600000 0x00002000
> + 0x2 0x0 0xf0000000 0x00020000
> + 0x3 0x0 0xfa000000 0x00008000>;
> +
> + flash@0,0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "cfi-flash";
> + reg = <0x0 0x0 0x800000>;
> + bank-width = <2>;
> + device-width = <1>;
> + };
> +
> + nand@1,0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "fsl,mpc8315-fcm-nand",
> + "fsl,elbc-fcm-nand";
> + reg = <0x1 0x0 0x2000>;
> + };
> + };
> diff --git a/Documentation/devicetree/bindings/powerpc/fsl/lbc.txt b/Documentation/devicetree/bindings/powerpc/fsl/lbc.txt
> deleted file mode 100644
> index 1c80fcedebb52049721fbd61c4dd4c57133bd47c..0000000000000000000000000000000000000000
> --- a/Documentation/devicetree/bindings/powerpc/fsl/lbc.txt
> +++ /dev/null
> @@ -1,43 +0,0 @@
> -* Chipselect/Local Bus
> -
> -Properties:
> -- name : Should be localbus
> -- #address-cells : Should be either two or three. The first cell is the
> - chipselect number, and the remaining cells are the
> - offset into the chipselect.
> -- #size-cells : Either one or two, depending on how large each chipselect
> - can be.
> -- ranges : Each range corresponds to a single chipselect, and cover
> - the entire access window as configured.
> -
> -Example:
> - localbus@f0010100 {
> - compatible = "fsl,mpc8272-localbus",
> - "fsl,pq2-localbus";
> - #address-cells = <2>;
> - #size-cells = <1>;
> - reg = <0xf0010100 0x40>;
> -
> - ranges = <0x0 0x0 0xfe000000 0x02000000
> - 0x1 0x0 0xf4500000 0x00008000
> - 0x2 0x0 0xfd810000 0x00010000>;
> -
> - flash@0,0 {
> - compatible = "jedec-flash";
> - reg = <0x0 0x0 0x2000000>;
> - bank-width = <4>;
> - device-width = <1>;
> - };
> -
> - board-control@1,0 {
> - reg = <0x1 0x0 0x20>;
> - compatible = "fsl,mpc8272ads-bcsr";
> - };
> -
> - simple-periph@2,0 {
> - compatible = "fsl,elbc-gpcm-uio";
> - reg = <0x2 0x0 0x10000>;
> - elbc-gpcm-br = <0xfd810800>;
> - elbc-gpcm-or = <0xffff09f7>;
> - };
> - };
>
> --
> 2.48.0.rc1.219.gb6b6757d772
>
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH RFC 9/9] dt-bindings: nand: Convert fsl,elbc bindings to YAML
2025-01-27 4:23 ` Rob Herring
@ 2025-02-06 22:59 ` J. Neuschäfer
0 siblings, 0 replies; 41+ messages in thread
From: J. Neuschäfer @ 2025-02-06 22:59 UTC (permalink / raw)
To: Rob Herring
Cc: J. Neuschäfer, devicetree, linuxppc-dev, Scott Wood,
Madhavan Srinivasan, Michael Ellerman, Nicholas Piggin,
Christophe Leroy, Naveen N Rao, Krzysztof Kozlowski, Conor Dooley,
Damien Le Moal, Niklas Cassel, Herbert Xu, David S. Miller,
Lee Jones, Vinod Koul, Lorenzo Pieralisi,
Krzysztof Wilczyński, Manivannan Sadhasivam, Bjorn Helgaas,
J. Neuschäfer, Wim Van Sebroeck, Guenter Roeck, Mark Brown,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-kernel, linux-ide, linux-crypto, dmaengine, linux-pci,
linux-watchdog, linux-spi, linux-mtd
On Sun, Jan 26, 2025 at 10:23:21PM -0600, Rob Herring wrote:
> On Sun, Jan 26, 2025 at 07:59:04PM +0100, J. Neuschäfer wrote:
> > Convert the Freescale localbus controller bindings from text form to
> > YAML. The list of compatible strings reflects current usage.
> >
> > Changes compared to the txt version:
> > - removed the board-control (fsl,mpc8272ads-bcsr) node because it only
> > appears in this example and nowhere else
> > - added a new example with NAND flash
> >
> > Remaining issues:
> > - The localbus is not really a simple-bus: Unit addresses are not simply
> > addresses on a memory bus. Instead, they have a format: The first cell
> > is a chip select number, the remaining one or two cells are bus
> > addresses.
>
> That's every external parallel bus. See bindings/memory-controllers/*
>
> Probably fine to leave 'simple-bus' if that's your question. It's more
> that there is configuration for the chipselect timings that make's this
> not a simple-bus. But the address translation should work just fine.
My concern mainly stems from the resulting warnings if I allow/use simple-bus:
Documentation/devicetree/bindings/memory-controllers/fsl,elbc.example.dts:77.23-84.15:
Warning (simple_bus_reg): /example-1/localbus@e0005000/flash@0,0: simple-bus unit address format error, expected "0"
Documentation/devicetree/bindings/memory-controllers/fsl,elbc.example.dts:86.22-92.15:
Warning (simple_bus_reg): /example-1/localbus@e0005000/nand@1,0: simple-bus unit address format error, expected "100000000"
Existing devicetrees specify the eLBC with compatible = ..., "simple-bus",
which lead me to include the simple-bus compatible both in the binding
itself and in the examples, which in turn leads to (correct) warnings
from DTC about node names such as nand@1,0 (it expects 100000000).
nand@1,0 was however completely correct for the eLBC bus, because it's
not one big linear address, but rather a chip select (1) and an address (0).
My current idea to resolve this contradiction is to remove simple-bus
from the binding and change affected devicetrees later.
>
> >
> > Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
> > ---
> > .../devicetree/bindings/mtd/fsl,elbc-fcm-nand.yaml | 61 +++++++++
> > .../bindings/powerpc/fsl/fsl,elbc-gpcm-uio.yaml | 55 ++++++++
> > .../devicetree/bindings/powerpc/fsl/fsl,elbc.yaml | 150 +++++++++++++++++++++
> > .../devicetree/bindings/powerpc/fsl/lbc.txt | 43 ------
> > 4 files changed, 266 insertions(+), 43 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/mtd/fsl,elbc-fcm-nand.yaml b/Documentation/devicetree/bindings/mtd/fsl,elbc-fcm-nand.yaml
> > new file mode 100644
> > index 0000000000000000000000000000000000000000..127f164443972bbaf50fd9daa80c504577ddd7bd
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/mtd/fsl,elbc-fcm-nand.yaml
> > @@ -0,0 +1,61 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/mtd/fsl,elbc-fcm-nand.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: NAND flash attached to Freescale eLBC
> > +
> > +maintainers:
> > + - J. Neuschäfer <j.ne@posteo.net>
> > +
> > +allOf:
> > + - $ref: nand-chip.yaml#
> > +
> > +properties:
> > + compatible:
> > + oneOf:
>
> Don't need oneOf.
How would I express "either one of various chip-specific strings
followed by fsl,elbc-fcm-nand, or fsl,elbc-fcm-nand alone"?
>
> > + - items:
> > + - enum:
> > + - fsl,mpc8313-fcm-nand
> > + - fsl,mpc8315-fcm-nand
> > + - fsl,mpc8377-fcm-nand
> > + - fsl,mpc8378-fcm-nand
> > + - fsl,mpc8379-fcm-nand
> > + - fsl,mpc8536-fcm-nand
> > + - fsl,mpc8569-fcm-nand
> > + - fsl,mpc8572-fcm-nand
> > + - fsl,p1020-fcm-nand
> > + - fsl,p1021-fcm-nand
> > + - fsl,p1025-fcm-nand
> > + - fsl,p2020-fcm-nand
> > + - const: fsl,elbc-fcm-nand
> > + - const: fsl,elbc-fcm-nand
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + "#address-cells": true
> > +
> > + "#size-cells": true
> > +
> > +required:
> > + - compatible
> > + - reg
> > +
> > +additionalProperties: false
>
> If you use anything from nand-chip.yaml, then you need
> unevaluatedProperties here.
Noted, will fix.
>
> > +
> > +examples:
> > + - |
> > + localbus {
> > + #address-cells = <2>;
> > + #size-cells = <1>;
> > +
> > + nand@1,0 {
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + compatible = "fsl,mpc8315-fcm-nand",
> > + "fsl,elbc-fcm-nand";
> > + reg = <0x1 0x0 0x2000>;
> > + };
> > + };
> > diff --git a/Documentation/devicetree/bindings/powerpc/fsl/fsl,elbc-gpcm-uio.yaml b/Documentation/devicetree/bindings/powerpc/fsl/fsl,elbc-gpcm-uio.yaml
> > new file mode 100644
> > index 0000000000000000000000000000000000000000..60f849b79c11a4060f2fa4ab163f9fa9317df130
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/powerpc/fsl/fsl,elbc-gpcm-uio.yaml
> > @@ -0,0 +1,55 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/powerpc/fsl/fsl,elbc-gpcm-uio.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Userspace I/O interface for Freescale eLBC devices
> > +
> > +maintainers:
> > + - J. Neuschäfer <j.ne@posteo.net>
> > +
> > +properties:
> > + compatible:
> > + const: fsl,elbc-gpcm-uio
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + elbc-gpcm-br:
> > + description: Base Register (BR) value to set
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > +
> > + elbc-gpcm-or:
> > + description: Option Register (OR) value to set
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > +
> > + device_type: true
>
> This should be dropped.
Will do
> > diff --git a/Documentation/devicetree/bindings/powerpc/fsl/fsl,elbc.yaml b/Documentation/devicetree/bindings/powerpc/fsl/fsl,elbc.yaml
[...]
> > + "#address-cells":
> > + enum: [2, 3]
> > + description: |
>
> Don't need '|' unless there's some formatting.
Will remove.
>
> > + The first cell is the chipselect number, and the remaining cells are the
> > + offset into the chipselect.
> > +
> > + "#size-cells":
> > + enum: [1, 2]
> > + description: |
> > + Either one or two, depending on how large each chipselect can be.
> > +
> > + ranges:
> > + description: |
> > + Each range corresponds to a single chipselect, and covers the entire
> > + access window as configured.
> > +
> > +patternProperties:
> > + "^.*@.*$":
>
> You should define the unit-address format here: @<chipselect>,<offset>
Will do.
Thanks,
J. Neuschäfer
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH RFC 9/9] dt-bindings: nand: Convert fsl,elbc bindings to YAML
2025-01-26 18:59 ` [PATCH RFC 9/9] dt-bindings: nand: Convert fsl,elbc " J. Neuschäfer via B4 Relay
2025-01-27 4:23 ` Rob Herring
@ 2025-01-27 8:37 ` Krzysztof Kozlowski
2025-02-06 22:30 ` J. Neuschäfer
2025-01-29 23:01 ` Frank Li
2 siblings, 1 reply; 41+ messages in thread
From: Krzysztof Kozlowski @ 2025-01-27 8:37 UTC (permalink / raw)
To: J. Neuschäfer
Cc: devicetree, linuxppc-dev, Scott Wood, Madhavan Srinivasan,
Michael Ellerman, Nicholas Piggin, Christophe Leroy, Naveen N Rao,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Damien Le Moal,
Niklas Cassel, Herbert Xu, David S. Miller, Lee Jones, Vinod Koul,
Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Bjorn Helgaas, J. Neuschäfer,
Wim Van Sebroeck, Guenter Roeck, Mark Brown, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-kernel, linux-ide,
linux-crypto, dmaengine, linux-pci, linux-watchdog, linux-spi,
linux-mtd
On Sun, Jan 26, 2025 at 07:59:04PM +0100, J. Neuschäfer wrote:
> Convert the Freescale localbus controller bindings from text form to
> YAML. The list of compatible strings reflects current usage.
simple-bus and 20 other compatibles you used were not present in the
original binding. Does above "list of compatible strings" mean you just
added them?
>
> Changes compared to the txt version:
> - removed the board-control (fsl,mpc8272ads-bcsr) node because it only
> appears in this example and nowhere else
> - added a new example with NAND flash
>
> Remaining issues:
> - The localbus is not really a simple-bus: Unit addresses are not simply
> addresses on a memory bus. Instead, they have a format: The first cell
> is a chip select number, the remaining one or two cells are bus
> addresses.
>
> Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
> ---
> .../devicetree/bindings/mtd/fsl,elbc-fcm-nand.yaml | 61 +++++++++
> .../bindings/powerpc/fsl/fsl,elbc-gpcm-uio.yaml | 55 ++++++++
Please split the conversion from adding new bindings. For example above
file and its compatible fsl,elbc-gpcm-uio was not documented in original
TXT.
...
> diff --git a/Documentation/devicetree/bindings/powerpc/fsl/fsl,elbc.yaml b/Documentation/devicetree/bindings/powerpc/fsl/fsl,elbc.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..6bbceb82c77826499abe85879e9189b18d396eea
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/powerpc/fsl/fsl,elbc.yaml
> @@ -0,0 +1,150 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/powerpc/fsl/fsl,elbc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale Enhanced Local Bus Controller
What sort of bus is it? Memory bus? Then place it with others, see
memory directory.
> +
> +maintainers:
> + - J. Neuschäfer <j.ne@posteo.net>
> +
> +properties:
> + $nodename:
> + pattern: "^localbus@[0-9a-f]+$"
> +
> + compatible:
> + oneOf:
> + - items:
> + - enum:
> + - fsl,mpc8313-elbc
> + - fsl,mpc8315-elbc
> + - fsl,mpc8377-elbc
> + - fsl,mpc8378-elbc
> + - fsl,mpc8379-elbc
> + - fsl,mpc8536-elbc
> + - fsl,mpc8569-elbc
> + - fsl,mpc8572-elbc
> + - fsl,p1020-elbc
> + - fsl,p1021-elbc
> + - fsl,p1023-elbc
> + - fsl,p2020-elbc
> + - fsl,p2041-elbc
> + - fsl,p3041-elbc
> + - fsl,p4080-elbc
> + - fsl,p5020-elbc
> + - fsl,p5040-elbc
> + - const: fsl,elbc
> + - const: simple-bus
> +
> + - items:
> + - const: fsl,mpc8272-localbus
> + - const: fsl,pq2-localbus
> +
> + - items:
> + - enum:
> + - fsl,mpc8247-localbus
> + - fsl,mpc8248-localbus
> + - fsl,mpc8360-localbus
> + - const: fsl,pq2pro-localbus
> + - const: simple-bus
> +
> + - items:
> + - enum:
> + - fsl,mpc8540-localbus
> + - fsl,mpc8544-lbc
> + - fsl,mpc8544-localbus
> + - fsl,mpc8548-lbc
> + - fsl,mpc8548-localbus
> + - fsl,mpc8560-localbus
> + - fsl,mpc8568-localbus
> + - const: fsl,pq3-localbus
> + - const: simple-bus
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + "#address-cells":
> + enum: [2, 3]
> + description: |
> + The first cell is the chipselect number, and the remaining cells are the
> + offset into the chipselect.
> +
> + "#size-cells":
> + enum: [1, 2]
> + description: |
> + Either one or two, depending on how large each chipselect can be.
> +
> + ranges:
> + description: |
> + Each range corresponds to a single chipselect, and covers the entire
> + access window as configured.
> +
> +patternProperties:
> + "^.*@.*$":
> + type: object
And probably you need
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + localbus@f0010100 {
> + compatible = "fsl,mpc8272-localbus",
> + "fsl,pq2-localbus";
> + #address-cells = <2>;
> + #size-cells = <1>;
> + reg = <0xf0010100 0x40>;
compatible, then reg - see DTS coding style.
> +
> + ranges = <0x0 0x0 0xfe000000 0x02000000
> + 0x1 0x0 0xf4500000 0x00008000
> + 0x2 0x0 0xfd810000 0x00010000>;
> +
> + flash@0,0 {
> + compatible = "jedec-flash";
> + reg = <0x0 0x0 0x2000000>;
Well, here it is correct
> + bank-width = <4>;
> + device-width = <1>;
> + };
> +
> + simple-periph@2,0 {
> + compatible = "fsl,elbc-gpcm-uio";
> + reg = <0x2 0x0 0x10000>;
> + elbc-gpcm-br = <0xfd810800>;
> + elbc-gpcm-or = <0xffff09f7>;
> + };
> + };
> +
> + - |
> + localbus@e0005000 {
compatible, reg
> + #address-cells = <2>;
> + #size-cells = <1>;
> + compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
> + reg = <0xe0005000 0x1000>;
> + interrupts = <77 0x8>;
> + interrupt-parent = <&ipic>;
> +
> + ranges = <0x0 0x0 0xfe000000 0x00800000
> + 0x1 0x0 0xe0600000 0x00002000
> + 0x2 0x0 0xf0000000 0x00020000
> + 0x3 0x0 0xfa000000 0x00008000>;
> +
> + flash@0,0 {
compatible, reg
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "cfi-flash";
> + reg = <0x0 0x0 0x800000>;
> + bank-width = <2>;
> + device-width = <1>;
> + };
> +
> + nand@1,0 {
compatible, reg
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "fsl,mpc8315-fcm-nand",
> + "fsl,elbc-fcm-nand";
> + reg = <0x1 0x0 0x2000>;
> + };
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH RFC 9/9] dt-bindings: nand: Convert fsl,elbc bindings to YAML
2025-01-27 8:37 ` Krzysztof Kozlowski
@ 2025-02-06 22:30 ` J. Neuschäfer
0 siblings, 0 replies; 41+ messages in thread
From: J. Neuschäfer @ 2025-02-06 22:30 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: J. Neuschäfer, devicetree, linuxppc-dev, Scott Wood,
Madhavan Srinivasan, Michael Ellerman, Nicholas Piggin,
Christophe Leroy, Naveen N Rao, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Damien Le Moal, Niklas Cassel, Herbert Xu,
David S. Miller, Lee Jones, Vinod Koul, Lorenzo Pieralisi,
Krzysztof Wilczyński, Manivannan Sadhasivam, Bjorn Helgaas,
J. Neuschäfer, Wim Van Sebroeck, Guenter Roeck, Mark Brown,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-kernel, linux-ide, linux-crypto, dmaengine, linux-pci,
linux-watchdog, linux-spi, linux-mtd
On Mon, Jan 27, 2025 at 09:37:32AM +0100, Krzysztof Kozlowski wrote:
> On Sun, Jan 26, 2025 at 07:59:04PM +0100, J. Neuschäfer wrote:
> > Convert the Freescale localbus controller bindings from text form to
> > YAML. The list of compatible strings reflects current usage.
>
> simple-bus and 20 other compatibles you used were not present in the
> original binding. Does above "list of compatible strings" mean you just
> added them?
Ah, I should make this clearer:
- by "list of compatible strings" I mean the list as it is after
applying the patch
- by "current usage" I mean what is found in arch/*/boot/dts
>
> >
> > Changes compared to the txt version:
> > - removed the board-control (fsl,mpc8272ads-bcsr) node because it only
> > appears in this example and nowhere else
> > - added a new example with NAND flash
> >
> > Remaining issues:
> > - The localbus is not really a simple-bus: Unit addresses are not simply
> > addresses on a memory bus. Instead, they have a format: The first cell
> > is a chip select number, the remaining one or two cells are bus
> > addresses.
> >
> > Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
> > ---
> > .../devicetree/bindings/mtd/fsl,elbc-fcm-nand.yaml | 61 +++++++++
> > .../bindings/powerpc/fsl/fsl,elbc-gpcm-uio.yaml | 55 ++++++++
>
> Please split the conversion from adding new bindings. For example above
> file and its compatible fsl,elbc-gpcm-uio was not documented in original
> TXT.
Fair point, I'll split them.
>
> ...
>
> > diff --git a/Documentation/devicetree/bindings/powerpc/fsl/fsl,elbc.yaml b/Documentation/devicetree/bindings/powerpc/fsl/fsl,elbc.yaml
> > new file mode 100644
> > index 0000000000000000000000000000000000000000..6bbceb82c77826499abe85879e9189b18d396eea
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/powerpc/fsl/fsl,elbc.yaml
> > @@ -0,0 +1,150 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/powerpc/fsl/fsl,elbc.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Freescale Enhanced Local Bus Controller
>
> What sort of bus is it? Memory bus? Then place it with others, see
> memory directory.
Yes, a memory bus controller with explicit chip-select lines, for
various kinds of memory (flash, RAM), and possibly other peripherals.
I'll move it to bindings/memory-controllers.
>
> > +
> > +maintainers:
> > + - J. Neuschäfer <j.ne@posteo.net>
> > +
> > +properties:
> > + $nodename:
> > + pattern: "^localbus@[0-9a-f]+$"
> > +
> > + compatible:
> > + oneOf:
> > + - items:
> > + - enum:
> > + - fsl,mpc8313-elbc
> > + - fsl,mpc8315-elbc
> > + - fsl,mpc8377-elbc
> > + - fsl,mpc8378-elbc
> > + - fsl,mpc8379-elbc
> > + - fsl,mpc8536-elbc
> > + - fsl,mpc8569-elbc
> > + - fsl,mpc8572-elbc
> > + - fsl,p1020-elbc
> > + - fsl,p1021-elbc
> > + - fsl,p1023-elbc
> > + - fsl,p2020-elbc
> > + - fsl,p2041-elbc
> > + - fsl,p3041-elbc
> > + - fsl,p4080-elbc
> > + - fsl,p5020-elbc
> > + - fsl,p5040-elbc
> > + - const: fsl,elbc
> > + - const: simple-bus
> > +
> > + - items:
> > + - const: fsl,mpc8272-localbus
> > + - const: fsl,pq2-localbus
> > +
> > + - items:
> > + - enum:
> > + - fsl,mpc8247-localbus
> > + - fsl,mpc8248-localbus
> > + - fsl,mpc8360-localbus
> > + - const: fsl,pq2pro-localbus
> > + - const: simple-bus
> > +
> > + - items:
> > + - enum:
> > + - fsl,mpc8540-localbus
> > + - fsl,mpc8544-lbc
> > + - fsl,mpc8544-localbus
> > + - fsl,mpc8548-lbc
> > + - fsl,mpc8548-localbus
> > + - fsl,mpc8560-localbus
> > + - fsl,mpc8568-localbus
> > + - const: fsl,pq3-localbus
> > + - const: simple-bus
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + interrupts:
> > + maxItems: 1
> > +
> > + "#address-cells":
> > + enum: [2, 3]
> > + description: |
> > + The first cell is the chipselect number, and the remaining cells are the
> > + offset into the chipselect.
> > +
> > + "#size-cells":
> > + enum: [1, 2]
> > + description: |
> > + Either one or two, depending on how large each chipselect can be.
> > +
> > + ranges:
> > + description: |
> > + Each range corresponds to a single chipselect, and covers the entire
> > + access window as configured.
> > +
> > +patternProperties:
> > + "^.*@.*$":
> > + type: object
>
> And probably you need
?
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + localbus@f0010100 {
> > + compatible = "fsl,mpc8272-localbus",
> > + "fsl,pq2-localbus";
> > + #address-cells = <2>;
> > + #size-cells = <1>;
> > + reg = <0xf0010100 0x40>;
>
> compatible, then reg - see DTS coding style.
I'll clean up the various style issues in the examples.
(These examples are quite old, either from the old version of this
binding or from existing dts files.)
Best regards,
J. Neuschäfer
>
> > +
> > + ranges = <0x0 0x0 0xfe000000 0x02000000
> > + 0x1 0x0 0xf4500000 0x00008000
> > + 0x2 0x0 0xfd810000 0x00010000>;
> > +
> > + flash@0,0 {
> > + compatible = "jedec-flash";
> > + reg = <0x0 0x0 0x2000000>;
>
> Well, here it is correct
>
> > + bank-width = <4>;
> > + device-width = <1>;
> > + };
> > +
> > + simple-periph@2,0 {
> > + compatible = "fsl,elbc-gpcm-uio";
> > + reg = <0x2 0x0 0x10000>;
> > + elbc-gpcm-br = <0xfd810800>;
> > + elbc-gpcm-or = <0xffff09f7>;
> > + };
> > + };
> > +
> > + - |
> > + localbus@e0005000 {
>
> compatible, reg
>
> > + #address-cells = <2>;
> > + #size-cells = <1>;
> > + compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
> > + reg = <0xe0005000 0x1000>;
> > + interrupts = <77 0x8>;
> > + interrupt-parent = <&ipic>;
> > +
> > + ranges = <0x0 0x0 0xfe000000 0x00800000
> > + 0x1 0x0 0xe0600000 0x00002000
> > + 0x2 0x0 0xf0000000 0x00020000
> > + 0x3 0x0 0xfa000000 0x00008000>;
> > +
> > + flash@0,0 {
>
> compatible, reg
>
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + compatible = "cfi-flash";
> > + reg = <0x0 0x0 0x800000>;
> > + bank-width = <2>;
> > + device-width = <1>;
> > + };
> > +
> > + nand@1,0 {
>
> compatible, reg
>
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + compatible = "fsl,mpc8315-fcm-nand",
> > + "fsl,elbc-fcm-nand";
> > + reg = <0x1 0x0 0x2000>;
> > + };
>
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH RFC 9/9] dt-bindings: nand: Convert fsl,elbc bindings to YAML
2025-01-26 18:59 ` [PATCH RFC 9/9] dt-bindings: nand: Convert fsl,elbc " J. Neuschäfer via B4 Relay
2025-01-27 4:23 ` Rob Herring
2025-01-27 8:37 ` Krzysztof Kozlowski
@ 2025-01-29 23:01 ` Frank Li
2025-02-06 22:59 ` J. Neuschäfer
2 siblings, 1 reply; 41+ messages in thread
From: Frank Li @ 2025-01-29 23:01 UTC (permalink / raw)
To: J. Neuschäfer
Cc: devicetree, linuxppc-dev, Scott Wood, Madhavan Srinivasan,
Michael Ellerman, Nicholas Piggin, Christophe Leroy, Naveen N Rao,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Damien Le Moal,
Niklas Cassel, Herbert Xu, David S. Miller, Lee Jones, Vinod Koul,
Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Bjorn Helgaas, J. Neuschäfer,
Wim Van Sebroeck, Guenter Roeck, Mark Brown, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-kernel, linux-ide,
linux-crypto, dmaengine, linux-pci, linux-watchdog, linux-spi,
linux-mtd
On Sun, Jan 26, 2025 at 07:59:04PM +0100, J. Neuschäfer wrote:
> Convert the Freescale localbus controller bindings from text form to
> YAML. The list of compatible strings reflects current usage.
>
> Changes compared to the txt version:
> - removed the board-control (fsl,mpc8272ads-bcsr) node because it only
> appears in this example and nowhere else
> - added a new example with NAND flash
>
> Remaining issues:
> - The localbus is not really a simple-bus: Unit addresses are not simply
> addresses on a memory bus. Instead, they have a format: The first cell
> is a chip select number, the remaining one or two cells are bus
> addresses.
>
> Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
> ---
> .../devicetree/bindings/mtd/fsl,elbc-fcm-nand.yaml | 61 +++++++++
> .../bindings/powerpc/fsl/fsl,elbc-gpcm-uio.yaml | 55 ++++++++
> .../devicetree/bindings/powerpc/fsl/fsl,elbc.yaml | 150 +++++++++++++++++++++
> .../devicetree/bindings/powerpc/fsl/lbc.txt | 43 ------
> 4 files changed, 266 insertions(+), 43 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/mtd/fsl,elbc-fcm-nand.yaml b/Documentation/devicetree/bindings/mtd/fsl,elbc-fcm-nand.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..127f164443972bbaf50fd9daa80c504577ddd7bd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mtd/fsl,elbc-fcm-nand.yaml
> @@ -0,0 +1,61 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mtd/fsl,elbc-fcm-nand.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NAND flash attached to Freescale eLBC
> +
> +maintainers:
> + - J. Neuschäfer <j.ne@posteo.net>
> +
> +allOf:
> + - $ref: nand-chip.yaml#
> +
> +properties:
> + compatible:
> + oneOf:
> + - items:
> + - enum:
> + - fsl,mpc8313-fcm-nand
> + - fsl,mpc8315-fcm-nand
> + - fsl,mpc8377-fcm-nand
> + - fsl,mpc8378-fcm-nand
> + - fsl,mpc8379-fcm-nand
> + - fsl,mpc8536-fcm-nand
> + - fsl,mpc8569-fcm-nand
> + - fsl,mpc8572-fcm-nand
> + - fsl,p1020-fcm-nand
> + - fsl,p1021-fcm-nand
> + - fsl,p1025-fcm-nand
> + - fsl,p2020-fcm-nand
> + - const: fsl,elbc-fcm-nand
> + - const: fsl,elbc-fcm-nand
> +
> + reg:
> + maxItems: 1
> +
> + "#address-cells": true
should limit to a number set like
- const: 2
> +
> + "#size-cells": true
the same as #address-cells.
> +
> +required:
> + - compatible
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + localbus {
> + #address-cells = <2>;
> + #size-cells = <1>;
> +
> + nand@1,0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "fsl,mpc8315-fcm-nand",
> + "fsl,elbc-fcm-nand";
> + reg = <0x1 0x0 0x2000>;
> + };
> + };
> diff --git a/Documentation/devicetree/bindings/powerpc/fsl/fsl,elbc-gpcm-uio.yaml b/Documentation/devicetree/bindings/powerpc/fsl/fsl,elbc-gpcm-uio.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..60f849b79c11a4060f2fa4ab163f9fa9317df130
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/powerpc/fsl/fsl,elbc-gpcm-uio.yaml
> @@ -0,0 +1,55 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/powerpc/fsl/fsl,elbc-gpcm-uio.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Userspace I/O interface for Freescale eLBC devices
> +
> +maintainers:
> + - J. Neuschäfer <j.ne@posteo.net>
> +
> +properties:
> + compatible:
> + const: fsl,elbc-gpcm-uio
> +
> + reg:
> + maxItems: 1
> +
> + elbc-gpcm-br:
> + description: Base Register (BR) value to set
> + $ref: /schemas/types.yaml#/definitions/uint32
> +
> + elbc-gpcm-or:
> + description: Option Register (OR) value to set
> + $ref: /schemas/types.yaml#/definitions/uint32
> +
> + device_type: true
> +
> + interrupts:
> + maxItems: 1
> +
> + uio_name:
> + $ref: /schemas/types.yaml#/definitions/string
> +
> +required:
> + - compatible
> + - reg
> + - elbc-gpcm-br
> + - elbc-gpcm-or
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + localbus {
> + #address-cells = <2>;
> + #size-cells = <1>;
> +
> + simple-periph@2,0 {
> + compatible = "fsl,elbc-gpcm-uio";
> + reg = <0x2 0x0 0x10000>;
> + elbc-gpcm-br = <0xfd810800>;
> + elbc-gpcm-or = <0xffff09f7>;
> + };
> + };
> diff --git a/Documentation/devicetree/bindings/powerpc/fsl/fsl,elbc.yaml b/Documentation/devicetree/bindings/powerpc/fsl/fsl,elbc.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..6bbceb82c77826499abe85879e9189b18d396eea
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/powerpc/fsl/fsl,elbc.yaml
> @@ -0,0 +1,150 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/powerpc/fsl/fsl,elbc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale Enhanced Local Bus Controller
> +
> +maintainers:
> + - J. Neuschäfer <j.ne@posteo.net>
> +
> +properties:
> + $nodename:
> + pattern: "^localbus@[0-9a-f]+$"
> +
> + compatible:
> + oneOf:
> + - items:
> + - enum:
> + - fsl,mpc8313-elbc
> + - fsl,mpc8315-elbc
> + - fsl,mpc8377-elbc
> + - fsl,mpc8378-elbc
> + - fsl,mpc8379-elbc
> + - fsl,mpc8536-elbc
> + - fsl,mpc8569-elbc
> + - fsl,mpc8572-elbc
> + - fsl,p1020-elbc
> + - fsl,p1021-elbc
> + - fsl,p1023-elbc
> + - fsl,p2020-elbc
> + - fsl,p2041-elbc
> + - fsl,p3041-elbc
> + - fsl,p4080-elbc
> + - fsl,p5020-elbc
> + - fsl,p5040-elbc
> + - const: fsl,elbc
> + - const: simple-bus
> +
> + - items:
> + - const: fsl,mpc8272-localbus
> + - const: fsl,pq2-localbus
> +
> + - items:
> + - enum:
> + - fsl,mpc8247-localbus
> + - fsl,mpc8248-localbus
> + - fsl,mpc8360-localbus
> + - const: fsl,pq2pro-localbus
> + - const: simple-bus
> +
> + - items:
> + - enum:
> + - fsl,mpc8540-localbus
> + - fsl,mpc8544-lbc
> + - fsl,mpc8544-localbus
> + - fsl,mpc8548-lbc
> + - fsl,mpc8548-localbus
> + - fsl,mpc8560-localbus
> + - fsl,mpc8568-localbus
> + - const: fsl,pq3-localbus
> + - const: simple-bus
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + "#address-cells":
> + enum: [2, 3]
> + description: |
> + The first cell is the chipselect number, and the remaining cells are the
> + offset into the chipselect.
> +
> + "#size-cells":
> + enum: [1, 2]
> + description: |
> + Either one or two, depending on how large each chipselect can be.
> +
> + ranges:
> + description: |
> + Each range corresponds to a single chipselect, and covers the entire
> + access window as configured.
> +
> +patternProperties:
> + "^.*@.*$":
> + type: object
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + localbus@f0010100 {
> + compatible = "fsl,mpc8272-localbus",
> + "fsl,pq2-localbus";
> + #address-cells = <2>;
> + #size-cells = <1>;
> + reg = <0xf0010100 0x40>;
> +
> + ranges = <0x0 0x0 0xfe000000 0x02000000
> + 0x1 0x0 0xf4500000 0x00008000
> + 0x2 0x0 0xfd810000 0x00010000>;
> +
> + flash@0,0 {
> + compatible = "jedec-flash";
> + reg = <0x0 0x0 0x2000000>;
> + bank-width = <4>;
> + device-width = <1>;
> + };
> +
> + simple-periph@2,0 {
> + compatible = "fsl,elbc-gpcm-uio";
> + reg = <0x2 0x0 0x10000>;
> + elbc-gpcm-br = <0xfd810800>;
> + elbc-gpcm-or = <0xffff09f7>;
> + };
> + };
> +
> + - |
> + localbus@e0005000 {
> + #address-cells = <2>;
> + #size-cells = <1>;
> + compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
> + reg = <0xe0005000 0x1000>;
> + interrupts = <77 0x8>;
> + interrupt-parent = <&ipic>;
> +
> + ranges = <0x0 0x0 0xfe000000 0x00800000
> + 0x1 0x0 0xe0600000 0x00002000
> + 0x2 0x0 0xf0000000 0x00020000
> + 0x3 0x0 0xfa000000 0x00008000>;
> +
> + flash@0,0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "cfi-flash";
> + reg = <0x0 0x0 0x800000>;
> + bank-width = <2>;
> + device-width = <1>;
> + };
> +
> + nand@1,0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "fsl,mpc8315-fcm-nand",
> + "fsl,elbc-fcm-nand";
> + reg = <0x1 0x0 0x2000>;
> + };
> + };
> diff --git a/Documentation/devicetree/bindings/powerpc/fsl/lbc.txt b/Documentation/devicetree/bindings/powerpc/fsl/lbc.txt
> deleted file mode 100644
> index 1c80fcedebb52049721fbd61c4dd4c57133bd47c..0000000000000000000000000000000000000000
> --- a/Documentation/devicetree/bindings/powerpc/fsl/lbc.txt
> +++ /dev/null
> @@ -1,43 +0,0 @@
> -* Chipselect/Local Bus
> -
> -Properties:
> -- name : Should be localbus
> -- #address-cells : Should be either two or three. The first cell is the
> - chipselect number, and the remaining cells are the
> - offset into the chipselect.
> -- #size-cells : Either one or two, depending on how large each chipselect
> - can be.
> -- ranges : Each range corresponds to a single chipselect, and cover
> - the entire access window as configured.
> -
> -Example:
> - localbus@f0010100 {
> - compatible = "fsl,mpc8272-localbus",
> - "fsl,pq2-localbus";
> - #address-cells = <2>;
> - #size-cells = <1>;
> - reg = <0xf0010100 0x40>;
> -
> - ranges = <0x0 0x0 0xfe000000 0x02000000
> - 0x1 0x0 0xf4500000 0x00008000
> - 0x2 0x0 0xfd810000 0x00010000>;
> -
> - flash@0,0 {
> - compatible = "jedec-flash";
> - reg = <0x0 0x0 0x2000000>;
> - bank-width = <4>;
> - device-width = <1>;
> - };
> -
> - board-control@1,0 {
> - reg = <0x1 0x0 0x20>;
> - compatible = "fsl,mpc8272ads-bcsr";
> - };
> -
> - simple-periph@2,0 {
> - compatible = "fsl,elbc-gpcm-uio";
> - reg = <0x2 0x0 0x10000>;
> - elbc-gpcm-br = <0xfd810800>;
> - elbc-gpcm-or = <0xffff09f7>;
> - };
> - };
>
> --
> 2.48.0.rc1.219.gb6b6757d772
>
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH RFC 9/9] dt-bindings: nand: Convert fsl,elbc bindings to YAML
2025-01-29 23:01 ` Frank Li
@ 2025-02-06 22:59 ` J. Neuschäfer
0 siblings, 0 replies; 41+ messages in thread
From: J. Neuschäfer @ 2025-02-06 22:59 UTC (permalink / raw)
To: Frank Li
Cc: J. Neuschäfer, devicetree, linuxppc-dev, Scott Wood,
Madhavan Srinivasan, Michael Ellerman, Nicholas Piggin,
Christophe Leroy, Naveen N Rao, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Damien Le Moal, Niklas Cassel, Herbert Xu,
David S. Miller, Lee Jones, Vinod Koul, Lorenzo Pieralisi,
Krzysztof Wilczyński, Manivannan Sadhasivam, Bjorn Helgaas,
J. Neuschäfer, Wim Van Sebroeck, Guenter Roeck, Mark Brown,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-kernel, linux-ide, linux-crypto, dmaengine, linux-pci,
linux-watchdog, linux-spi, linux-mtd
On Wed, Jan 29, 2025 at 06:01:04PM -0500, Frank Li wrote:
> On Sun, Jan 26, 2025 at 07:59:04PM +0100, J. Neuschäfer wrote:
> > Convert the Freescale localbus controller bindings from text form to
> > YAML. The list of compatible strings reflects current usage.
> >
> > Changes compared to the txt version:
> > - removed the board-control (fsl,mpc8272ads-bcsr) node because it only
> > appears in this example and nowhere else
> > - added a new example with NAND flash
> >
> > Remaining issues:
> > - The localbus is not really a simple-bus: Unit addresses are not simply
> > addresses on a memory bus. Instead, they have a format: The first cell
> > is a chip select number, the remaining one or two cells are bus
> > addresses.
> >
> > Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
> > ---
> > .../devicetree/bindings/mtd/fsl,elbc-fcm-nand.yaml | 61 +++++++++
> > .../bindings/powerpc/fsl/fsl,elbc-gpcm-uio.yaml | 55 ++++++++
> > .../devicetree/bindings/powerpc/fsl/fsl,elbc.yaml | 150 +++++++++++++++++++++
> > .../devicetree/bindings/powerpc/fsl/lbc.txt | 43 ------
> > 4 files changed, 266 insertions(+), 43 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/mtd/fsl,elbc-fcm-nand.yaml b/Documentation/devicetree/bindings/mtd/fsl,elbc-fcm-nand.yaml
[...]
> > + "#address-cells": true
>
> should limit to a number set like
>
> - const: 2
Will do
> > +
> > + "#size-cells": true
>
> the same as #address-cells.
Will do
Thanks,
J. Neuschäfer
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 0/9] YAML conversion of several Freescale/PowerPC DT bindings
2025-01-26 18:58 [PATCH 0/9] YAML conversion of several Freescale/PowerPC DT bindings J. Neuschäfer via B4 Relay
` (8 preceding siblings ...)
2025-01-26 18:59 ` [PATCH RFC 9/9] dt-bindings: nand: Convert fsl,elbc " J. Neuschäfer via B4 Relay
@ 2025-01-29 22:29 ` Frank Li
2025-01-31 11:33 ` J. Neuschäfer
9 siblings, 1 reply; 41+ messages in thread
From: Frank Li @ 2025-01-29 22:29 UTC (permalink / raw)
To: J. Neuschäfer
Cc: devicetree, linuxppc-dev, Scott Wood, Madhavan Srinivasan,
Michael Ellerman, Nicholas Piggin, Christophe Leroy, Naveen N Rao,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Damien Le Moal,
Niklas Cassel, Herbert Xu, David S. Miller, Lee Jones, Vinod Koul,
Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Bjorn Helgaas, J. Neuschäfer,
Wim Van Sebroeck, Guenter Roeck, Mark Brown, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-kernel, linux-ide,
linux-crypto, dmaengine, linux-pci, linux-watchdog, linux-spi,
linux-mtd
On Sun, Jan 26, 2025 at 07:58:55PM +0100, J. Neuschäfer wrote:
> This is a spin-off of the series titled
> "powerpc: MPC83xx cleanup and LANCOM NWAPP2 board".
>
> During the development of that series, it became clear that many
> devicetree bindings for Freescale MPC8xxx platforms are still in the old
> plain-text format, or don't exist at all, and in any case don't mention
> all valid compatible strings.
>
> Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
Please cc imx@lists.linux.dev next time
Frank
> ---
> J. Neuschäfer (9):
> dt-bindings: powerpc: Add binding for Freescale/NXP MPC83xx SoCs
> dt-bindings: ata: Convert fsl,pq-sata binding to YAML
> dt-bindings: crypto: Convert fsl,sec-2.0 binding to YAML
> dt-bindings: mfd: Convert fsl,mcu-mpc8349emitx binding to YAML
> dt-bindings: dma: Convert fsl,elo*-dma bindings to YAML
> dt-bindings: pci: Add fsl,mpc83xx-pcie bindings
> dt-bindings: watchdog: Convert mpc8xxx-wdt binding to YAML
> dt-bindings: spi: Convert Freescale SPI bindings to YAML
> [RFC] dt-bindings: nand: Convert fsl,elbc bindings to YAML
>
> .../devicetree/bindings/ata/fsl,pq-sata.yaml | 59 ++++++
> Documentation/devicetree/bindings/ata/fsl-sata.txt | 28 ---
> .../devicetree/bindings/crypto/fsl,sec2.0.yaml | 139 ++++++++++++++
> .../devicetree/bindings/crypto/fsl-sec2.txt | 65 -------
> .../devicetree/bindings/dma/fsl,elo-dma.yaml | 129 +++++++++++++
> .../devicetree/bindings/dma/fsl,elo3-dma.yaml | 105 +++++++++++
> .../devicetree/bindings/dma/fsl,eloplus-dma.yaml | 120 ++++++++++++
> .../bindings/mfd/fsl,mcu-mpc8349emitx.yaml | 53 ++++++
> .../devicetree/bindings/mtd/fsl,elbc-fcm-nand.yaml | 61 ++++++
> .../devicetree/bindings/pci/fsl,mpc8xxx-pci.yaml | 83 +++++++++
> .../devicetree/bindings/powerpc/fsl/dma.txt | 204 ---------------------
> .../bindings/powerpc/fsl/fsl,elbc-gpcm-uio.yaml | 55 ++++++
> .../devicetree/bindings/powerpc/fsl/fsl,elbc.yaml | 150 +++++++++++++++
> .../bindings/powerpc/fsl/fsl,mpc83xx.yaml | 67 +++++++
> .../devicetree/bindings/powerpc/fsl/lbc.txt | 43 -----
> .../bindings/powerpc/fsl/mcu-mpc8349emitx.txt | 17 --
> .../devicetree/bindings/spi/fsl,espi.yaml | 56 ++++++
> Documentation/devicetree/bindings/spi/fsl,spi.yaml | 71 +++++++
> Documentation/devicetree/bindings/spi/fsl-spi.txt | 62 -------
> .../devicetree/bindings/watchdog/mpc8xxx-wdt.txt | 25 ---
> .../devicetree/bindings/watchdog/mpc8xxx-wdt.yaml | 64 +++++++
> 21 files changed, 1212 insertions(+), 444 deletions(-)
> ---
> base-commit: ffd294d346d185b70e28b1a28abe367bbfe53c04
> change-id: 20250126-ppcyaml-680ccd8b3fc2
>
> Best regards,
> --
> J. Neuschäfer <j.ne@posteo.net>
>
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH 0/9] YAML conversion of several Freescale/PowerPC DT bindings
2025-01-29 22:29 ` [PATCH 0/9] YAML conversion of several Freescale/PowerPC DT bindings Frank Li
@ 2025-01-31 11:33 ` J. Neuschäfer
0 siblings, 0 replies; 41+ messages in thread
From: J. Neuschäfer @ 2025-01-31 11:33 UTC (permalink / raw)
To: Frank Li
Cc: J. Neuschäfer, devicetree, linuxppc-dev, Scott Wood,
Madhavan Srinivasan, Michael Ellerman, Nicholas Piggin,
Christophe Leroy, Naveen N Rao, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Damien Le Moal, Niklas Cassel, Herbert Xu,
David S. Miller, Lee Jones, Vinod Koul, Lorenzo Pieralisi,
Krzysztof Wilczyński, Manivannan Sadhasivam, Bjorn Helgaas,
J. Neuschäfer, Wim Van Sebroeck, Guenter Roeck, Mark Brown,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-kernel, linux-ide, linux-crypto, dmaengine, linux-pci,
linux-watchdog, linux-spi, linux-mtd
On Wed, Jan 29, 2025 at 05:29:41PM -0500, Frank Li wrote:
> On Sun, Jan 26, 2025 at 07:58:55PM +0100, J. Neuschäfer wrote:
> > This is a spin-off of the series titled
> > "powerpc: MPC83xx cleanup and LANCOM NWAPP2 board".
> >
> > During the development of that series, it became clear that many
> > devicetree bindings for Freescale MPC8xxx platforms are still in the old
> > plain-text format, or don't exist at all, and in any case don't mention
> > all valid compatible strings.
> >
> > Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
>
> Please cc imx@lists.linux.dev next time
>
> Frank
Will do.
Best regards,
J. Neuschäfer
^ permalink raw reply [flat|nested] 41+ messages in thread