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[79.41.239.37]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab772fd6ba1sm235401366b.79.2025.02.07.01.49.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Feb 2025 01:49:53 -0800 (PST) From: Andrea della Porta X-Google-Original-From: Andrea della Porta Date: Fri, 7 Feb 2025 10:50:52 +0100 To: Bjorn Helgaas Cc: Andrea della Porta , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Broadcom internal kernel review list , Lorenzo Pieralisi , Krzysztof Wilczynski , Manivannan Sadhasivam , Bjorn Helgaas , Linus Walleij , Catalin Marinas , Will Deacon , Bartosz Golaszewski , Derek Kiernan , Dragan Cvetic , Arnd Bergmann , Greg Kroah-Hartman , Saravana Kannan , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-gpio@vger.kernel.org, Masahiro Yamada , Stefan Wahren , Herve Codina , Luca Ceresoli , Thomas Petazzoni , Andrew Lunn Subject: Re: [PATCH v6 05/10] clk: rp1: Add support for clocks provided by RP1 Message-ID: References: <20250203234443.GA810409@bhelgaas> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250203234443.GA810409@bhelgaas> Hi Bjorn, On 17:44 Mon 03 Feb , Bjorn Helgaas wrote: > On Mon, Jan 13, 2025 at 03:58:04PM +0100, Andrea della Porta wrote: > > RaspberryPi RP1 is an MFD providing, among other peripherals, several > > clock generators and PLLs that drives the sub-peripherals. > > Add the driver to support the clock providers. > > > +#define PLL_PRIM_DIV1_SHIFT 16 > > +#define PLL_PRIM_DIV1_WIDTH 3 > > +#define PLL_PRIM_DIV1_MASK GENMASK(PLL_PRIM_DIV1_SHIFT + \ > > + PLL_PRIM_DIV1_WIDTH - 1, \ > > + PLL_PRIM_DIV1_SHIFT) > > + > > +#define PLL_PRIM_DIV2_SHIFT 12 > > +#define PLL_PRIM_DIV2_WIDTH 3 > > +#define PLL_PRIM_DIV2_MASK GENMASK(PLL_PRIM_DIV2_SHIFT + \ > > + PLL_PRIM_DIV2_WIDTH - 1, \ > > + PLL_PRIM_DIV2_SHIFT) > > Maybe this is standard drivers/clk style, but this seems like overkill > to me. I think this would be sufficient and easier to read: > > #define PLL_PRIM_DIV1_MASK GENMASK(18, 16) > #define PLL_PRIM_DIV2_MASK GENMASK(14, 12) Ack. > > > +static unsigned long rp1_pll_recalc_rate(struct clk_hw *hw, > > + unsigned long parent_rate) > > +{ > > + struct rp1_clk_desc *pll = container_of(hw, struct rp1_clk_desc, hw); > > + struct rp1_clockman *clockman = pll->clockman; > > + const struct rp1_pll_data *data = pll->data; > > + u32 prim, prim_div1, prim_div2; > > + > > + prim = clockman_read(clockman, data->ctrl_reg); > > + prim_div1 = (prim & PLL_PRIM_DIV1_MASK) >> PLL_PRIM_DIV1_SHIFT; > > + prim_div2 = (prim & PLL_PRIM_DIV2_MASK) >> PLL_PRIM_DIV2_SHIFT; > > And then here, I think you can just use FIELD_GET(): > > prim_div1 = FIELD_GET(PLL_PRIM_DIV1_MASK, prim); > prim_div2 = FIELD_GET(PLL_PRIM_DIV2_MASK, prim); > > It looks like the same could be done for PLL_SEC_DIV_MASK, > PLL_CS_REFDIV_SHIFT, PLL_PH_PHASE_SHIFT, CLK_CTRL_AUXSRC_MASK, etc. Ack. Regards, Andrea