RE: [PATCH 1/8] clk: renesas: r9a09g047: Add support for CRU0 clocks, and resets

Biju Das
2025-02-10T11:54:12Z

Hi Tommaso Merciai,

> -----Original Message-----
> From: Tommaso Merciai <tomm.merciai@gmail.com>
> Sent: 10 February 2025 11:46
> Subject: [PATCH 1/8] clk: renesas: r9a09g047: Add support for CRU0 clocks, and resets
>
> Add support for CRU0 clocks and resets along with the corresponding divider.
>
> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> ---
> drivers/clk/renesas/r9a09g047-cpg.c | 24 ++++++++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c
> index 51fd24c20ed5..5d02031219d8 100644
> --- a/drivers/clk/renesas/r9a09g047-cpg.c
> +++ b/drivers/clk/renesas/r9a09g047-cpg.c
> @@ -28,6 +28,7 @@ enum clk_ids {
> CLK_PLLCLN,
> CLK_PLLDTY,
> CLK_PLLCA55,
> + CLK_PLLVDO,
>
> /* Internal Core Clocks */
> CLK_PLLCM33_DIV16,
> @@ -35,7 +36,10 @@ enum clk_ids {
> CLK_PLLCLN_DIV8,
> CLK_PLLCLN_DIV16,
> CLK_PLLDTY_ACPU,
> + CLK_PLLDTY_ACPU_DIV2,
> CLK_PLLDTY_ACPU_DIV4,
> + CLK_PLLDTY_DIV16,
> + CLK_PLLVDO_CRU0,
>
> /* Module Clocks */
> MOD_CLK_BASE,
> @@ -49,6 +53,12 @@ static const struct clk_div_table dtable_1_8[] = {
> {0, 0},
> };
>
> +static const struct clk_div_table dtable_2_4[] = {
> + {0, 2},
> + {1, 4},
> + {0, 0},

Not sure {0, 2}, {1, 4}, {0, 0}, to make lines shorter?

Cheers,
Biju

> +};
> +
> static const struct clk_div_table dtable_2_64[] = {
> {0, 2},
> {1, 4},
> @@ -69,6 +79,7 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
> DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),
> DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
> DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLL_CONF(0x64)),
> + DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2),
>
> /* Internal Core Clocks */
> DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16), @@ -78,7 +89,11 @@ static
> const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
> DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),
>
> DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
> + DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU,
> +1, 2),
> DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
> + DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),
> +
> + DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3,
> +dtable_2_4),
>
> /* Core Clocks */
> DEF_FIXED("sys_0_pclk", R9A09G047_SYS_0_PCLK, CLK_QEXTAL, 1, 1), @@ -154,6 +169,12 @@ static
> const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
> BUS_MSTOP(8, BIT(4))),
> DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
> BUS_MSTOP(8, BIT(4))),
> + DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
> + BUS_MSTOP(9, BIT(4))),
> + DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19,
> + BUS_MSTOP(9, BIT(4))),
> + DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20,
> + BUS_MSTOP(9, BIT(4))),
> };
>
> static const struct rzv2h_reset r9a09g047_resets[] __initconst = { @@ -177,6 +198,9 @@ static const
> struct rzv2h_reset r9a09g047_resets[] __initconst = {
> DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
> DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
> DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
> + DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
> + DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
> + DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */
> };
>
> const struct rzv2h_cpg_info r9a09g047_cpg_info __initconst = {
> --
> 2.34.1