* Re: [PATCH v2 1/2] arm64: dts: s32g: add the eDMA nodes
2025-02-03 8:09 [PATCH v2 1/2] arm64: dts: s32g: add the eDMA nodes Larisa Grigore
@ 2025-02-03 15:38 ` Frank Li
2025-02-04 9:58 ` Matthias Brugger
2025-02-23 6:10 ` Shawn Guo
2 siblings, 0 replies; 4+ messages in thread
From: Frank Li @ 2025-02-03 15:38 UTC (permalink / raw)
To: Larisa Grigore
Cc: Chester Lin, Matthias Brugger, Ghennadi Procopciuc, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-kernel, imx,
devicetree, linux-kernel, s32, clizzi, aruizrui, eballetb
On Mon, Feb 03, 2025 at 10:09:19AM +0200, Larisa Grigore wrote:
> Add the two eDMA nodes in the device tree in order to enable the probing
> of the S32G2/S32G3 eDMA driver.
>
> Signed-off-by: Larisa Grigore <larisa.grigore@oss.nxp.com>
> ---
>
> v2: Moved #dma-cells before dma-channels and clock-names after clocks.
Reviewed-by: Frank Li <Frank.Li@nxp.com>
>
> arch/arm64/boot/dts/freescale/s32g2.dtsi | 34 ++++++++++++++++++++++++
> arch/arm64/boot/dts/freescale/s32g3.dtsi | 34 ++++++++++++++++++++++++
> 2 files changed, 68 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> index 7be430b78c83..64eac1dde05b 100644
> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> @@ -317,6 +317,23 @@ usdhc0-200mhz-grp4 {
> };
> };
>
> + edma0: dma-controller@40144000 {
> + compatible = "nxp,s32g2-edma";
> + reg = <0x40144000 0x24000>,
> + <0x4012c000 0x3000>,
> + <0x40130000 0x3000>;
> + #dma-cells = <2>;
> + dma-channels = <32>;
> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "tx-0-15",
> + "tx-16-31",
> + "err";
> + clocks = <&clks 63>, <&clks 64>;
> + clock-names = "dmamux0", "dmamux1";
> + };
> +
> uart0: serial@401c8000 {
> compatible = "nxp,s32g2-linflexuart",
> "fsl,s32v234-linflexuart";
> @@ -333,6 +350,23 @@ uart1: serial@401cc000 {
> status = "disabled";
> };
>
> + edma1: dma-controller@40244000 {
> + compatible = "nxp,s32g2-edma";
> + reg = <0x40244000 0x24000>,
> + <0x4022c000 0x3000>,
> + <0x40230000 0x3000>;
> + #dma-cells = <2>;
> + dma-channels = <32>;
> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "tx-0-15",
> + "tx-16-31",
> + "err";
> + clocks = <&clks 63>, <&clks 64>;
> + clock-names = "dmamux0", "dmamux1";
> + };
> +
> uart2: serial@402bc000 {
> compatible = "nxp,s32g2-linflexuart",
> "fsl,s32v234-linflexuart";
> diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> index 6c572ffe37ca..4f6201d6c08a 100644
> --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> @@ -374,6 +374,23 @@ usdhc0-200mhz-grp4 {
> };
> };
>
> + edma0: dma-controller@40144000 {
> + compatible = "nxp,s32g3-edma", "nxp,s32g2-edma";
> + reg = <0x40144000 0x24000>,
> + <0x4012c000 0x3000>,
> + <0x40130000 0x3000>;
> + #dma-cells = <2>;
> + dma-channels = <32>;
> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "tx-0-15",
> + "tx-16-31",
> + "err";
> + clocks = <&clks 63>, <&clks 64>;
> + clock-names = "dmamux0", "dmamux1";
> + };
> +
> uart0: serial@401c8000 {
> compatible = "nxp,s32g3-linflexuart",
> "fsl,s32v234-linflexuart";
> @@ -390,6 +407,23 @@ uart1: serial@401cc000 {
> status = "disabled";
> };
>
> + edma1: dma-controller@40244000 {
> + compatible = "nxp,s32g3-edma", "nxp,s32g2-edma";
> + reg = <0x40244000 0x24000>,
> + <0x4022c000 0x3000>,
> + <0x40230000 0x3000>;
> + #dma-cells = <2>;
> + dma-channels = <32>;
> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "tx-0-15",
> + "tx-16-31",
> + "err";
> + clocks = <&clks 63>, <&clks 64>;
> + clock-names = "dmamux0", "dmamux1";
> + };
> +
> uart2: serial@402bc000 {
> compatible = "nxp,s32g3-linflexuart",
> "fsl,s32v234-linflexuart";
> --
> 2.47.0
>
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH v2 1/2] arm64: dts: s32g: add the eDMA nodes
2025-02-03 8:09 [PATCH v2 1/2] arm64: dts: s32g: add the eDMA nodes Larisa Grigore
2025-02-03 15:38 ` Frank Li
@ 2025-02-04 9:58 ` Matthias Brugger
2025-02-23 6:10 ` Shawn Guo
2 siblings, 0 replies; 4+ messages in thread
From: Matthias Brugger @ 2025-02-04 9:58 UTC (permalink / raw)
To: Larisa Grigore, Chester Lin, Ghennadi Procopciuc, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-kernel, imx, devicetree, linux-kernel, s32, clizzi,
aruizrui, eballetb
On 03/02/2025 09:09, Larisa Grigore wrote:
> Add the two eDMA nodes in the device tree in order to enable the probing
> of the S32G2/S32G3 eDMA driver.
>
> Signed-off-by: Larisa Grigore <larisa.grigore@oss.nxp.com>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
> ---
>
> v2: Moved #dma-cells before dma-channels and clock-names after clocks.
>
> arch/arm64/boot/dts/freescale/s32g2.dtsi | 34 ++++++++++++++++++++++++
> arch/arm64/boot/dts/freescale/s32g3.dtsi | 34 ++++++++++++++++++++++++
> 2 files changed, 68 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> index 7be430b78c83..64eac1dde05b 100644
> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> @@ -317,6 +317,23 @@ usdhc0-200mhz-grp4 {
> };
> };
>
> + edma0: dma-controller@40144000 {
> + compatible = "nxp,s32g2-edma";
> + reg = <0x40144000 0x24000>,
> + <0x4012c000 0x3000>,
> + <0x40130000 0x3000>;
> + #dma-cells = <2>;
> + dma-channels = <32>;
> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "tx-0-15",
> + "tx-16-31",
> + "err";
> + clocks = <&clks 63>, <&clks 64>;
> + clock-names = "dmamux0", "dmamux1";
> + };
> +
> uart0: serial@401c8000 {
> compatible = "nxp,s32g2-linflexuart",
> "fsl,s32v234-linflexuart";
> @@ -333,6 +350,23 @@ uart1: serial@401cc000 {
> status = "disabled";
> };
>
> + edma1: dma-controller@40244000 {
> + compatible = "nxp,s32g2-edma";
> + reg = <0x40244000 0x24000>,
> + <0x4022c000 0x3000>,
> + <0x40230000 0x3000>;
> + #dma-cells = <2>;
> + dma-channels = <32>;
> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "tx-0-15",
> + "tx-16-31",
> + "err";
> + clocks = <&clks 63>, <&clks 64>;
> + clock-names = "dmamux0", "dmamux1";
> + };
> +
> uart2: serial@402bc000 {
> compatible = "nxp,s32g2-linflexuart",
> "fsl,s32v234-linflexuart";
> diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> index 6c572ffe37ca..4f6201d6c08a 100644
> --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> @@ -374,6 +374,23 @@ usdhc0-200mhz-grp4 {
> };
> };
>
> + edma0: dma-controller@40144000 {
> + compatible = "nxp,s32g3-edma", "nxp,s32g2-edma";
> + reg = <0x40144000 0x24000>,
> + <0x4012c000 0x3000>,
> + <0x40130000 0x3000>;
> + #dma-cells = <2>;
> + dma-channels = <32>;
> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "tx-0-15",
> + "tx-16-31",
> + "err";
> + clocks = <&clks 63>, <&clks 64>;
> + clock-names = "dmamux0", "dmamux1";
> + };
> +
> uart0: serial@401c8000 {
> compatible = "nxp,s32g3-linflexuart",
> "fsl,s32v234-linflexuart";
> @@ -390,6 +407,23 @@ uart1: serial@401cc000 {
> status = "disabled";
> };
>
> + edma1: dma-controller@40244000 {
> + compatible = "nxp,s32g3-edma", "nxp,s32g2-edma";
> + reg = <0x40244000 0x24000>,
> + <0x4022c000 0x3000>,
> + <0x40230000 0x3000>;
> + #dma-cells = <2>;
> + dma-channels = <32>;
> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "tx-0-15",
> + "tx-16-31",
> + "err";
> + clocks = <&clks 63>, <&clks 64>;
> + clock-names = "dmamux0", "dmamux1";
> + };
> +
> uart2: serial@402bc000 {
> compatible = "nxp,s32g3-linflexuart",
> "fsl,s32v234-linflexuart";
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH v2 1/2] arm64: dts: s32g: add the eDMA nodes
2025-02-03 8:09 [PATCH v2 1/2] arm64: dts: s32g: add the eDMA nodes Larisa Grigore
2025-02-03 15:38 ` Frank Li
2025-02-04 9:58 ` Matthias Brugger
@ 2025-02-23 6:10 ` Shawn Guo
2 siblings, 0 replies; 4+ messages in thread
From: Shawn Guo @ 2025-02-23 6:10 UTC (permalink / raw)
To: Larisa Grigore
Cc: Chester Lin, Matthias Brugger, Ghennadi Procopciuc, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-kernel, imx,
devicetree, linux-kernel, s32, clizzi, aruizrui, eballetb
On Mon, Feb 03, 2025 at 10:09:19AM +0200, Larisa Grigore wrote:
> Add the two eDMA nodes in the device tree in order to enable the probing
> of the S32G2/S32G3 eDMA driver.
>
> Signed-off-by: Larisa Grigore <larisa.grigore@oss.nxp.com>
Applied, thanks!
^ permalink raw reply [flat|nested] 4+ messages in thread