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From: Niklas Cassel <cassel@kernel.org>
To: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Sai Krishna Musham <sai.krishna.musham@amd.com>,
	bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com,
	robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
	linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, michal.simek@amd.com,
	bharat.kumar.gogada@amd.com, thippeswamy.havalige@amd.com
Subject: Re: [PATCH 2/2] PCI: xilinx-cpm: Add support for PCIe RP PERST# signal
Date: Mon, 24 Feb 2025 14:19:45 +0100	[thread overview]
Message-ID: <Z7xx8ZxpD011oCCj@ryzen> (raw)
In-Reply-To: <20250224070236.nhowwz3uwk2rx4qi@thinkpad>

On Mon, Feb 24, 2025 at 12:32:36PM +0530, Manivannan Sadhasivam wrote:
> On Mon, Feb 24, 2025 at 12:00:46PM +0530, Sai Krishna Musham wrote:
> > Add GPIO-based control for the PCIe Root Port PERST# signal.
> > 
> > According to section 2.2 of the PCIe Electromechanical Specification
> > (Revision 6.0), PERST# signal has to be deasserted after a delay of
> > 100 ms (TPVPERL) to ensure proper reset sequencing during PCIe
> > initialization.
> > 
> > Signed-off-by: Sai Krishna Musham <sai.krishna.musham@amd.com>
> > ---
> > This patch depends on the following patch series.
> > https://lore.kernel.org/all/20250217072713.635643-3-thippeswamy.havalige@amd.com/
> > ---
> >  drivers/pci/controller/pcie-xilinx-cpm.c | 23 +++++++++++++++++++++++
> >  1 file changed, 23 insertions(+)
> > 
> > diff --git a/drivers/pci/controller/pcie-xilinx-cpm.c b/drivers/pci/controller/pcie-xilinx-cpm.c
> > index 81e8bfae53d0..0e31b85658e6 100644
> > --- a/drivers/pci/controller/pcie-xilinx-cpm.c
> > +++ b/drivers/pci/controller/pcie-xilinx-cpm.c
> > @@ -6,6 +6,8 @@
> >   */
> >  
> >  #include <linux/bitfield.h>
> > +#include <linux/delay.h>
> > +#include <linux/gpio/consumer.h>
> >  #include <linux/interrupt.h>
> >  #include <linux/irq.h>
> >  #include <linux/irqchip.h>
> > @@ -568,8 +570,29 @@ static int xilinx_cpm_pcie_probe(struct platform_device *pdev)
> >  	struct device *dev = &pdev->dev;
> >  	struct pci_host_bridge *bridge;
> >  	struct resource_entry *bus;
> > +	struct gpio_desc *reset_gpio;
> >  	int err;
> >  
> > +	/* Request the GPIO for PCIe reset signal */
> > +	reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
> 
> You've defined the polarity as 0x1 in the binding. Which corresponds to
> GPIO_ACTIVE_LOW. So if you request the GPIO as GPIOD_OUT_LOW, it means the host
> is going to drive the PERST# line as 'high', which corresponds to PERST#
> deassert. I don't think you'd want that and if that is what is really happening,
> the endpoint state machine would be broken. So I suspect that the polarity of
> your PERST# line is wrong.
> 
> - Mani
> 
> > +	if (IS_ERR(reset_gpio)) {
> > +		dev_err(dev, "Failed to request reset GPIO\n");
> > +		return PTR_ERR(reset_gpio);
> > +	}
> > +
> > +	/* Assert the reset signal */
> > +	gpiod_set_value(reset_gpio, 0);
> > +
> > +	/*
> > +	 * As per section 2.2 of the PCI Express Card Electromechanical
> > +	 * Specification (Revision 6.0), the deassertion of the PERST# signal
> > +	 * should be delayed by 100 ms (TPVPERL).
> > +	 */
> > +	msleep(100);
> > +
> > +	/* Deassert the reset signal */
> > +	gpiod_set_value(reset_gpio, 1);
> > +

Since you are adding PERST# to your DT binding, please make sure that you
define it properly (as active low) in the DT binding.

Then in the driver things should look like this and nothing else:
devm_gpiod_get(..., GPIOD_OUT_HIGH); // will assert PERST#
gpiod_set_value(reset_gpio, 1); // assert PERST# (will be a no-op since PERST# is already asserted)
msleep(100);
gpiod_set_value(reset_gpio, 0); // deassert PERST#



Kind regards,
Niklas

      reply	other threads:[~2025-02-24 13:19 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-24  6:30 [PATCH 0/2] Add support for PCIe RP PERST# Sai Krishna Musham
2025-02-24  6:30 ` [PATCH 1/2] dt-bindings: PCI: xilinx-cpm: Add reset-gpios " Sai Krishna Musham
2025-02-24  6:42   ` Manivannan Sadhasivam
2025-02-24  6:30 ` [PATCH 2/2] PCI: xilinx-cpm: Add support for PCIe RP PERST# signal Sai Krishna Musham
2025-02-24  7:02   ` Manivannan Sadhasivam
2025-02-24 13:19     ` Niklas Cassel [this message]

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