From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail.zeus03.de (zeus03.de [194.117.254.33]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 31DC123F38A for ; Fri, 28 Feb 2025 21:32:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=194.117.254.33 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740778375; cv=none; b=HXRYPwbRqrpFBgvho4hFjfVnSvNpDnBYXiF+vl7du7Ti9XUdd03o2jLNG3Ba1UODj6AYR5Q/7/ekSAuhPArodX+ScxFxKyjqbjiyAhbHhAP5sHcaLnYVF0UJvuXqFPhoOsvYv0Cbv6bENRc75t5kbCrEpQFZXNY8EABYuktSK54= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740778375; c=relaxed/simple; bh=0bn7nOO12Db1/cprnEbj+LcZrOhAAVUZyUCa/CQIcms=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=h1HVDklkoOm25TchShlw67bm1MopnkdS1zluzUOUD82oiZ4grzB2VbE3WxhoPBtJ7/a3YNsaHGAFWzSx2eNi8tBDhFEdIWZ70qsa3BXjxqo7ZIUe6raMbvUZjWJ4J3VgY/VZ8i3eSSSt5CW1jbhLJADSJYbFjFzlvaCbkR3Y3Ho= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=sang-engineering.com; spf=pass smtp.mailfrom=sang-engineering.com; dkim=pass (2048-bit key) header.d=sang-engineering.com header.i=@sang-engineering.com header.b=AHZM/KW2; arc=none smtp.client-ip=194.117.254.33 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=sang-engineering.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sang-engineering.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sang-engineering.com header.i=@sang-engineering.com header.b="AHZM/KW2" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= sang-engineering.com; h=date:from:to:cc:subject:message-id :references:mime-version:content-type:in-reply-to; s=k1; bh=0bn7 nOO12Db1/cprnEbj+LcZrOhAAVUZyUCa/CQIcms=; b=AHZM/KW2y8OvzP1SS/HP f7rcyKf89+xVxVRx7NB+4z0c7wS3TDWUx77Lm/9+vodtjNTlHUGst9gH9gKcCLxI A2AyUrF2+jUL+pXYHjFngBb2eexb04WV35TbUu85TrvRxLpzACreOY+QzwqsnjgN rgHwepI/n/Crk9jZ3kxdI+8B43ZY1bVAyacHmBza2TJYI9VESXbeB+GC4OooLyrE kxQ4ocvWVsX2tw0xTQln5KKksGEMbH9CCc1hN0Ug1xobUW0DiNZcHno8qMyD4LS5 bnHK8OVBCZGs8A+jGLQ2aGsaIUc6UqHBDzU8f6Z9Hi1GbmWrDiE/i6Ee9WI+m+74 ZQ== Received: (qmail 1430828 invoked from network); 28 Feb 2025 22:32:51 +0100 Received: by mail.zeus03.de with ESMTPSA (TLS_AES_256_GCM_SHA384 encrypted, authenticated); 28 Feb 2025 22:32:51 +0100 X-UD-Smtp-Session: l3s3148p1@rzFwjDovNs0gAQnoAE04AOw9xELqAtuS Date: Fri, 28 Feb 2025 22:32:50 +0100 From: Wolfram Sang To: Biju Das Cc: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das , Conor Dooley Subject: Re: [PATCH v4 1/2] dt-bindings: mmc: renesas,sdhi: Document RZ/G3E support Message-ID: Mail-Followup-To: Wolfram Sang , Biju Das , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das , Conor Dooley References: <20250228124713.153979-1-biju.das.jz@bp.renesas.com> <20250228124713.153979-2-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="ZyYpMZHhkxk/PH7b" Content-Disposition: inline In-Reply-To: <20250228124713.153979-2-biju.das.jz@bp.renesas.com> --ZyYpMZHhkxk/PH7b Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Feb 28, 2025 at 12:47:08PM +0000, Biju Das wrote: > The SD/MMC block on the RZ/G3E ("R9A09G047") SoC is similar to that > of the RZ/V2H, but the SD0 channel has only dedicated pins, so we must > use SD_STATUS register to control voltage and power enable (internal > regulator), for non-fixed voltage (SD) MMC interface. However, it is > optional for fixed voltage MMC interface (eMMC). >=20 > For SD1 and SD2 channels, we can either use gpio regulator or internal > regulator (using SD_STATUS register) for voltage switching. >=20 > Document RZ/G3E SDHI IP support with optional internal regulator for > both RZ/G3E and RZ/V2H SoC. >=20 > Acked-by: Conor Dooley > Reviewed-by: Geert Uytterhoeven > Signed-off-by: Biju Das =46rom what I know about bindings, this looks good to me. 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